JP3985727B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-274487
[Patent Document 2]
JP 2000-164525 A.
[0003]
Silicon carbide (hereinafter referred to as SiC) has a wide band gap, and the maximum dielectric breakdown electric field is an order of magnitude larger than that of silicon (hereinafter referred to as Si). Furthermore, the natural oxide of SiC is SiO₂Therefore, a thermal oxide film can be easily formed on the surface of SiC by the same method as Si. For this reason, SiC is expected to be a very excellent material when used as a high-speed / high-voltage switching element for electric vehicles, particularly as a high-power uni / bipolar element.
Vertical MOSFET is an important device for considering application of SiC to power semiconductor devices. Since the MOSFET is a voltage-driven device, the elements can be driven in parallel and the driving circuit is simple. Moreover, since it is a unipolar device, high-speed switching is possible. The SiC power MOSFET in the prior art is disclosed in, for example, Patent Document 1 described above.
In the device cross-sectional structure in the conventional example, high concentration N⁺N on type SiC substrate⁻A type SiC epitaxial region is formed. Then, a P-type well region is formed in a predetermined region in the surface layer portion of the epitaxial region, and N-type in the P-type well region⁺Type source region and P⁺A mold contact region is formed. N on the surface of the P-type well region⁺N connected to the type source region⁻A mold storage channel region is formed. In addition, the surface layer portion of the epitaxial region is connected to the storage channel region and connected to the P-well N⁺A mold region is formed. A gate electrode is disposed on the storage channel region via a gate insulating film, and the gate electrode is covered with an interlayer insulating film. And P⁺Type contact area and N⁺A source electrode is formed so as to contact the type source region, and N⁺A drain electrode is formed on the back surface of the type SiC substrate.
[0004]
The operation of this power MOSFET is as follows. When a positive voltage is applied to the gate electrode while a voltage is applied between the drain electrode and the source electrode, electrons are applied to the surface of the storage channel facing the gate electrode. A storage layer is formed. As a result, drain region to epitaxial region, P well N⁺A current flows to the source electrode through the mold region, the storage channel region, and the source region.
When the voltage applied to the gate electrode is removed, the storage channel is depleted by the built-in potential with the P-type well region. As a result, N between P wells⁺The current stops flowing from the mold region to the storage channel region, and the drain electrode and the source electrode are electrically insulated and exhibit a switching function.
[0005]
An example of a conventional method for manufacturing the SiC power MOSFET will be described.
First N⁺For example, the impurity concentration is 10 on the type SiC substrate.¹⁴~Ten¹⁸cm^-3, N with a thickness of 1-100μm⁻A type SiC epitaxial region is formed.
Next, using a mask material 150, for example, aluminum ions are implanted in a multistage manner at an acceleration voltage of 10 k to 3 MeV at a high temperature of 100 to 1000 ° C. to form a P-type well region. For example, the total dose is 10¹²~Ten¹⁶/cm²It is. Of course, boron or gallium may be used as the P-type impurity in addition to aluminum.
Next, using a mask material, for example, aluminum ions are implanted at a high temperature of 100 to 1000 ° C. with an acceleration voltage of 10 k to 1 MeV, and P⁺A mold contact region is formed. For example, the total dose is 10¹⁴~Ten¹⁶/cm²It is. Of course, boron or gallium may be used as the P-type impurity in addition to aluminum.
Next, using another mask material, for example, phosphorus ions are multi-stage implanted at an acceleration voltage of 10 k to 1 MeV at a high temperature of 100 to 1000 ° C., and N⁺A mold source region is formed. For example, the total dose is 10¹⁴~Ten¹⁶/cm²It is. Of course, as the N-type impurity, nitrogen, arsenic, or the like may be used in addition to phosphorus.
Next, using still another mask material, for example, nitrogen ions are implanted at a high temperature of 100 to 1000 ° C. with an acceleration voltage of 10 k to 1 MeV, and N⁻Type storage channel region and P-well N⁺A mold region is formed. For example, the total dose is 10¹⁴~Ten¹⁶/cm²It is.
Note that the order of ion implantation for forming each region is not limited to that shown in this example.
Next, for example, heat treatment is performed at 1000 to 1800 ° C. to activate the implanted impurities.
Next, a gate insulating film is formed by thermal oxidation at about 1200 ° C., and then a gate electrode is formed from, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as an interlayer film.
After that, N against the interlayer film⁺Type source region and P⁺A contact hole is formed on the mold contact region to form a source electrode. N⁺A metal film is deposited on the back surface of the substrate as a drain electrode and heat-treated at, for example, about 600 to 1400 ° C. to complete the conventional SiC power MOSFET as an ohmic electrode.
[0006]
[Problems to be solved by the invention]
The problems of the conventional SiC power MOSFET will be described below.
As described above, in the conventional SiC power MOSFET in which the P-type well region is formed by ion implantation, it is difficult to form the well region sufficiently deep in the step of forming the well region. Therefore, in order to prevent punch-through, the P-type impurity concentration in the P-type well region is usually designed to be high.
By the way, the above nitrogen ions are implanted and N⁻Type storage channel region and P-well N⁺In the step of forming the mold region, the P-type impurity is compensated for and N⁻In order to form the type storage channel region, the concentration of nitrogen ions implanted into the semiconductor substrate must be equal to or higher than the P-type impurity concentration of the P-type well region. Therefore, P-well N⁺The N type impurity concentration in the type region is formed to be higher than the P type impurity concentration in the P type well region.
However, N having a higher impurity concentration than such a P-type well region under the gate insulating film.⁺When the mold region is formed, a high concentration of N is applied when a high voltage is applied to the drain electrode.⁺The drain electric field is concentrated in the mold region. As a result, the gate insulating film breaks down before the avalanche breakdown occurs in the semiconductor element, causing a problem that a desired breakdown voltage cannot be obtained. In general, power devices are required to withstand a constant current when an avalanche current flows, but in conventional SiC MOSFETs, the avalanche resistance is defined by the dielectric breakdown of the gate insulating film, which is very small. There was a problem of becoming.
The present invention has been made in order to solve the problems of the prior art as described above, and provides a high breakdown voltage semiconductor device and a method for manufacturing the same capable of suppressing a large electric field from being applied to a gate insulating film even with respect to a high drain electric field. The purpose is to provide.
[0007]
[Means for Solving the Problems]
  In order to solve the above-mentioned problems, the present invention is formed in a first conductivity type drain region formed in a semiconductor substrate, a first conductivity type drift region connected to the drain region, and a surface of the drift region. A second conductivity type well region, a first conductivity type source region formed in the well region, and the source region;Formed on the surface of the well regionStorage channel region of first conductivity type and storage channel regionAnd a second conductivity type inversion channel region formed in the surface layer of the well region, and at least on the inversion channel region and the storage channel region.A gate insulating film; a gate electrode formed on the gate insulating film; a drain electrode connected to the drain region; and a source electrode connected to the source region.
[0008]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the high voltage semiconductor device which can suppress that a big electric field is applied to a gate insulating film also with respect to a high drain electric field, and its manufacturing method can be provided.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
The polytype of silicon carbide (SiC) used in this embodiment is typically 4H, but other polytypes such as 6H and 3C may be used. Further, in this embodiment, the semiconductor device has been described in which the drain electrode is formed on the back surface of the semiconductor substrate, the source electrode is disposed on the surface of the substrate, and a current flows in the element in the vertical direction. However, for example, the present invention can also be applied to a semiconductor device having a structure in which a drain electrode is arranged on the surface of a substrate in the same manner as a source electrode and a current flows laterally.
In this embodiment, for example, the drain region is N-type and the well region is P-type. However, the combination of N-type and P-type is not limited to this. For example, the drain region is P-type and well-type. A configuration may be adopted in which the region is N-type.
Moreover, it cannot be overemphasized that the deformation | transformation in the range which does not deviate from the main point of this invention is included.
[0010]
  (Reference example1)
  FIG. 1 shows the present invention.Reference example 1 ofSemiconductor equipmentPlaceShow. As shown in the figure, high concentration N⁺N on type SiC substrate 10⁻A type SiC epitaxial region 20 is formed. Then, a P-type well region 30 is formed in a predetermined region in the surface layer portion of the epitaxial region 20, and the N-type well region 30 includes N-type well region 30.⁺Type source region 40 and P⁺A mold contact region 50 is formed. The surface of the P-type well region 30 has N⁻Type storage channel region 110 is N⁺It is connected to the type source region 40 and is formed so that the side wall substantially coincides with the side wall of the P type well region 30. A gate electrode 80 is disposed on the storage channel region 110 via a gate insulating film 90, and the gate electrode 80 is covered with an interlayer insulating film 70. And P⁺Type contact area 50 and N⁺A source electrode 60 is formed so as to be in contact with the type source region 40, and N⁺A drain electrode 140 is formed on the back surface of the type SiC substrate 10.
[0011]
  ThisHalf ofThe operation of the conductor device will be described. The basic operation is the same as that of the conventional SiC power MOSFET. That is, when a voltage is applied between the drain electrode 140 and the source electrode 60 and a positive voltage is applied to the gate electrode 80, electrons are accumulated in the surface layer of the storage channel 110 facing the gate electrode 80. A layer is formed. As a result, a current flows from the drain region 10 to the source electrode 60 through the epitaxial region 20, the storage channel region 110, and the source region 40.
  Further, when the voltage applied to the gate electrode 80 is removed, the storage channel 110 is depleted by the built-in potential with the P-type well region 30. As a result, no current flows from the epitaxial region 20 to the storage-type channel region 110, and the drain electrode 140 and the source electrode 60 are electrically insulated and exhibit a switching function.
[0012]
  next,hereAn example of the method for manufacturing the semiconductor device shown in FIG. 2 will be described with reference to the cross-sectional views of FIGS. 2 (a) to 3 (g).
[0013]
  In the process of FIG.⁺For example, the impurity concentration is 10 on the SiC substrate 10.¹⁴~Ten¹⁸cm^-3, N with a thickness of 1-100μm⁻A type SiC epitaxial region 20 is formed.
  In the step of FIG. 2 (b), using the mask material 150, for example, aluminum ions 160 are implanted in multiple stages at a high temperature of 100 to 1000 ° C. at an acceleration voltage of 10 k to 3 MeV to form the P-type well region 30. For example, the total dose is 10¹²~Ten¹⁶cm^-2It is. Of course, boron or gallium may be used as the P-type impurity in addition to aluminum.
  In the process of FIG. 2 (c), similarly, using the mask material 150, for example, nitrogen ions 161 are multi-stage implanted at an acceleration voltage of 10 k to 1 MeV at a high temperature of 100 to 1000 ° C., and N⁻A mold storage channel region 110 is formed. For example, the total dose is 10¹⁴~Ten¹⁶cm^-2It is.
  In the process of FIG. 2 (d), using the mask material 151, for example, aluminum ions 162 are multi-stage implanted at an acceleration voltage of 10 k to 1 MeV at a high temperature of 100 to 1000 ° C., and P⁺A mold contact region 50 is formed. For example, the total dose is 10¹⁴~Ten¹⁶cm^-2It is. Of course, boron or gallium may be used as the P-type impurity in addition to aluminum.
  In the step of FIG. 2 (e), phosphorus ions 163 are multi-stage implanted at an acceleration voltage of 10 k to 1 MeV at a high temperature of, for example, 100 to 1000 ° C. using the mask material 152, and N⁺A mold source region 40 is formed. For example, the total dose is 10¹⁴~Ten¹⁶cm^-2It is. Of course, as the N-type impurity, nitrogen, arsenic, or the like may be used in addition to phosphorus.
  Note that the order of ion implantation for forming each region is not limited to that shown in this example.
  In the process of FIG. 2 (f), for example, heat treatment is performed at 1000 to 1800 ° C. The implanted impurity is activated.
  In the step of FIG. 3 (g), the gate insulating film 90 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 80 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer film 70.
  After that, although not shown in the figure, the N relative to the interlayer film 70⁺Type source region 40 and P⁺A contact hole is formed on the mold contact region 50 to form a source electrode 60 (see FIG. 1). N⁺A metal film is deposited on the back surface of the substrate 10 as the drain electrode 140 and heat-treated at about 600 to 1400 ° C., for example, to form an ohmic electrode as shown in FIG.HalfThe conductor device is completed.
[0014]
  Book as aboveReference exampleThe semiconductor device of N is formed on a semiconductor substrate.⁺Type SiC substrate 10 and N formed by being connected to SiC substrate 10⁻Type SiC epitaxial region 20, P type well region 30 formed in a predetermined region of the surface layer of SiC epitaxial region 20, and N formed in well region 30⁺N type source region 40, N connected to source region 40 and formed so that the side wall substantially coincides with the side wall of well region 30⁻Type storage channel region 110, gate insulating film 90 formed on at least storage type channel region 110, gate electrode 80 formed on gate insulating film 90, and drain electrode connected to SiC substrate 10 140 and a source electrode 60 connected to the source region 40. N in Fig. 1⁺Type SiC substrate is formed in the drain region of the first conductivity type in the claims, N⁻Type SiC epitaxial region 20 in the first conductivity type drift region, P type well region 30 in the second conductivity type well region, N⁺Type source region 40 becomes a source region of the first conductivity type, N⁻The storage type channel region 110 corresponds to the storage type channel region of the first conductivity type. In this semiconductor device, an N region having a higher concentration than that of the P-type well region 30 is formed in the region covered by the drain electric field under the gate insulating film 90.⁺Since the mold region is not formed, a large electric field is not applied to the gate insulating film 90 compared to the conventional case. As a result, breakdown of the gate insulating film 90 before avalanche breakdown occurs in the semiconductor device can be prevented, and the element breakdown voltage is improved.
  Also bookReference exampleThe method of manufacturing a semiconductor device includes at least a step of depositing a first mask material 150 on a semiconductor substrate and a step of patterning the mask material 150, and introducing impurities into the semiconductor substrate through the mask material 150. As a result, the step of forming the P-type well region 30 and the introduction of impurities into the semiconductor substrate through the mask material 150 similarly⁻And forming the mold accumulation type channel region 110 at least in random order. Therefore, P-type well region 30 and N⁻Since the type accumulation channel region 110 can be manufactured with the same mask, the P type well region and the N type are used with two masks.⁻Compared to the conventional manufacturing method for forming the mold accumulation channel region, it can be manufactured more easily. In addition, since the storage channel region 110 can be formed in the P-type well region 30 by self-alignment, it is possible to provide a semiconductor device with a simple manufacturing process, low channel resistance, and high breakdown voltage.
  In addition, by using silicon carbide as the semiconductor substrate, high breakdown voltage, high carrier mobility, and high saturation drift velocity can be easily ensured as compared with silicon semiconductors. For this reason, it can be used for a high-speed switching element or a high-power element.
[0015]
  (Embodiment1)
  FIG. 4 shows an embodiment of a semiconductor device manufactured according to the present invention.1Is shown.
  As shown in the figure, high concentration N⁺N on type SiC substrate 10⁻A type SiC epitaxial region 20 is formed. Then, a P-type well region 31 is formed in a predetermined region in the surface layer portion of the epitaxial region 20, and N-type is formed in the P-type well region 31.⁺Type source region 40 and P⁺A mold contact region 50 is formed. The surface of the P-type well region 31 has N⁺N connected to type source region 40⁻A type storage channel region 110 is formed. The P-type inversion channel region 120 is also formed on the surface layer of the P-type well region 31 with N⁻It is connected to the mold storage channel region 110. A gate electrode 80 is disposed on the inversion channel region 120 and the storage channel region 110 via a gate insulating film 90, and the gate electrode 80 is covered with an interlayer insulating film 70. And P⁺Type contact area 50 and N⁺A source electrode 60 is formed so as to be in contact with the type source region 40, and N⁺A drain electrode 140 is formed on the back surface of the type SiC substrate 10.
  As shown in FIG.Reference example 1The difference in structure with the inversion channel region 120 is that N⁻The P type well region 31 is connected to the type storage channel region 110 and formed on the surface layer.
[0016]
The operation of the semiconductor device of this embodiment will be described. When a voltage is applied between the drain electrode 140 and the source electrode 60 and a positive voltage is applied to the gate electrode 80, an electron storage layer is formed on the surface layer of the storage channel 110 facing the gate electrode 80. It is formed. Similarly, an inverted channel region 120 is formed on the surface layer of the P-type well region 31 facing the gate electrode 80. As a result, a current flows from the drain region 10 to the source electrode 60 through the epitaxial region 20, the inversion channel region 120, the storage channel region 110, and the source region 40.
Further, by removing the voltage applied to the gate electrode 80, the drain electrode 140 and the source electrode 60 are electrically insulated, and exhibit a switching function.
[0017]
Next, an example of a method for manufacturing the semiconductor device described in this embodiment will be described with reference to cross-sectional views of FIGS. 5 (a) to 6 (g) and FIGS. 7 (a) to (d).
In the process of FIG.⁺For example, the impurity concentration is 10 on the SiC substrate 10.¹⁴~Ten¹⁸cm^-3, N with a thickness of 1-100μm⁻A type SiC epitaxial region 20 is formed.
In the step of FIG. 5 (b), for example, a CVD oxide film is used to perform etching so that an inclination (taper) is provided on the pattern side wall to form a mask material 153. Here, if the inclination (taper) angle of the pattern side wall with respect to the normal direction of the SiC substrate is 180, 180 indicates the depth of the well region 31 to be formed, the length of the inversion channel region 120, the thickness of the mask material 153, and the well region. 31 is determined in consideration of process and device design items such as what impurity atoms are used for formation, but is preferably about 10 to 30 °, for example.
Using this taper-formed mask material 153, for example, aluminum ions 160 are implanted at a high temperature of 100 to 1000 ° C. at an acceleration voltage of 10 k to 3 MeV to form a P-type well region 31. For example, the total dose is 10¹²~Ten¹⁶cm^-2It is. A part of the aluminum ions implanted at this time is partially introduced into the epitaxial region 20 through the taper portion of the mask material 153 as shown by a region 190 in the figure, and the P-type well region 31 is also formed. Of course, boron or gallium may be used as the P-type impurity in addition to aluminum.
[0018]
Here, taper etching of the CVD oxide film will be described with reference to FIGS.
In the step of FIG. 7A, a CVD oxide film 153 is deposited on a semiconductor substrate to a thickness of about 1.5 μm, for example, and a photoresist 170 is applied thereon.
In the step of FIG. 7 (b), after exposing a part of the photoresist 170, patterning is performed with an organic solvent, and the remaining photoresist 170 is reflowed by a heat treatment of about 100 ° C., for example, as shown in FIG. A gentle resist pattern 170 is formed.
In the process of FIG.₆,SCIENCE FICTION₆, NF₃, C2F₆Etc. and oxygen gas conditions, dry etching is performed so that the etching selectivity of the photoresist 170 and the CVD oxide film 153 is 1, and the inclination of the resist pattern is transferred to the CVD oxide film 153. Let
In the step shown in FIG. 7D, the photoresist 170 is removed by, for example, an asher to complete a mask material 153 having a pattern sidewall provided with an inclination (taper).
The inclination (taper) angle 180 of the mask material 153 is determined by the heat treatment temperature and time when the photoresist 170 is reflowed in FIG. 7B and the etching speed in dry etching.
As the taper etching method, in addition to the above-described dry etching method using resist receding, for example, CHF₃The mask material 153 may be formed by cooling the SiC substrate temperature to about 0 ° C. using a gas and performing dry etching of the CVD oxide film with a photoresist mask. Further, the CVD oxide film is etched with a photoresist mask, for example, wet etching is performed using an HF solution. Then, since the CVD oxide film is isotropically etched to form an undercut, the mask material 153 can be easily tapered.
[0019]
  In the step of FIG. 5C, the storage channel region 110 is formed by using the mask material 153 and implanting nitrogen ions 161 at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV. For example, the total dose is 10¹⁴~Ten¹⁶cm^-2It is. At this time, since the nitrogen ions 161 are implanted shallower than the well region 31 in the depth direction, even if a part of the nitrogen ions partially penetrates the tapered portion of the mask material 153, the surface of the P-type well region 31 Nitrogen ions 161 are not implanted in part. In other words, there is a region where the storage channel region 110 is not formed in the surface layer of the P-type well region 31 like a region indicated by 120 in the figure. This is referred to as an inverted channel region 120.
  As an N-type impurity used for forming the storage channel 110, phosphorus, arsenic, or the like may be used in addition to nitrogen.
  In the step of FIG. 5 (d), using the mask material 151, for example, aluminum ions 162 are multi-stage implanted at an acceleration voltage of 10 k to 1 MeV at a high temperature of 100 to 1000 ° C., and P⁺A mold contact region 50 is formed. For example, the total dose is 10¹⁴~Ten¹⁶cm^-2It is. Of course, boron or gallium may be used as the P-type impurity in addition to aluminum.
  In the step of FIG. 5 (e), phosphorus ions 163 are multi-stage implanted at an acceleration voltage of 10 k to 1 MeV at a high temperature of, for example, 100 to 1000 ° C. using the mask material 152, and N⁺A mold source region 40 is formed. For example, the total dose is 10¹⁴~Ten¹⁶cm^-2It is. Of course, as the N-type impurity, nitrogen, arsenic, or the like may be used in addition to phosphorus.
  Note that the order of ion implantation for forming each region is not limited to that shown in this example.
  In the step of FIG. 5 (f), for example, heat treatment is performed at 1000 to 1800 ° C. The implanted impurity is activated.
  In the step of FIG. 6 (g), the gate insulating film 90 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 80 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer film 70.
  After that, although not shown in the figure, the N relative to the interlayer film 70⁺Type source region 40 and P⁺A contact hole is formed on the mold contact region 50 to form a source electrode 60 (see FIG. 4). N⁺A metal film is deposited as the drain electrode 140 on the back surface of the substrate 10 and heat-treated at, for example, about 600 to 1400 ° C. to complete the semiconductor device as the second embodiment shown in FIG. 4 as an ohmic electrode.
[0020]
  As described above, the semiconductor device according to the present embodiment includes N formed on the semiconductor substrate.⁺Type SiC substrate 10 and N formed by being connected to SiC substrate 10⁻Type SiC epitaxial region 20, P type well region 31 formed in a predetermined region of the surface layer of SiC epitaxial region 20, and N formed in well region 31⁺Type source region 40, N connected to the source region 40 and formed in the surface layer in the well region 31⁻Type storage channel region 110, a P type inversion channel region 120 formed in the surface layer of the well region 31 between the storage type channel region 110 and the SiC epitaxial region 20, and at least the inversion type channel region 120 and A gate insulating film 90 formed on the storage channel region 110, a gate electrode 80 formed on the gate insulating film 90, a drain electrode 140 connected to the SiC substrate 10, and a source region 40 And a source electrode 60. Note that the P-type inversion channel region 120 in FIG. 4 corresponds to the inversion channel region of the second conductivity type in the claims. In this semiconductor device, the inverted channel 120 is formed by being connected to the storage channel 110.Reference exampleCompared with the semiconductor device shown in FIG. 1, the element leakage current with respect to the high drain electric field can be reduced. In particular, the element leakage current increases in the storage channel region 110 at a high temperature, but the semiconductor device has a feature that the leakage current is small even at a high temperature.
  Further, in the method for manufacturing a semiconductor device of this embodiment, the patterning of the mask material 153 is a process of performing etching so that the pattern side wall of the mask material 153 is inclined. According to such a manufacturing method, the P-type well region 31 and N⁻When forming the type accumulation channel region 110 with the same mask, the surface of the P well region 31 is N⁻An inverted channel region 120 is formed by being connected to the type storage channel region 110. For this reason,Reference example1 and embodiments described later2Compared with this manufacturing method, it is possible to manufacture a semiconductor device having less element leakage current with respect to a high drain electric field and having excellent high temperature characteristics.
  If the manufacturing method as shown above is used, the P-type well region 31 and the inversion-type channel region 120 are formed in a self-aligned (self-aligned) process (step of FIG. 5C). Therefore, when the semiconductor device shown in FIG. 4 is a unit cell, the shape of the inversion channel region is equally formed in all unit cells. As a result, variations in channel length can be eliminated, and an increase in on-resistance and a decrease in breakdown voltage caused by the variation can be prevented.
[0021]
  (Reference example 2)
  FIG. 8 shows the present invention.Reference example 2 ofSemiconductor equipmentPlaceShow.
  As shown in the figure, high concentration N⁺N on type SiC substrate 10⁻A type SiC epitaxial region 20 is formed. Then, a P-type well region 30 is formed in a predetermined region in the surface layer portion of the epitaxial region 20, and the N-type well region 30 includes N-type well region 30.⁺Type source region 40 and P⁺A mold contact region 50 is formed. The surface of the P-type well region 30 has N⁻Type storage channel region 110 is N⁺It is connected to the type source region 40 and is formed so that the side wall substantially coincides with the side wall of the P type well region 30. Further, a low P-well N-type region 130 is connected to the storage channel region 110 and formed in the surface layer portion of the epitaxial region 20. A gate electrode 80 is disposed on the storage channel region 110 via a gate insulating film 90, and the gate electrode 80 is covered with an interlayer insulating film 70. And P⁺Type contact area 50 and N⁺A source electrode 60 is formed so as to be in contact with the type source region 40, and N⁺A drain electrode 140 is formed on the back surface of the type SiC substrate 10.
  As shown in FIG.Reference exampleThe structural difference from 1 is that a low concentration N-type region 130 between P wells is formed in the surface layer portion of the epitaxial region 20 connected to the storage channel 110.
[0022]
  Next bookReference exampleAn example of a method for manufacturing the semiconductor device shown in FIG. 2 will be described with reference to the cross-sectional views of FIGS. 2 (a) to 2 (e) and FIGS. 9 (a) to 9 (c).
  2 (a)-(e)Reference exampleSince this is the same as the process described in 1, description thereof is omitted.
  In the process of FIG. 9, using the mask material 154, for example, nitrogen ions 164 are implanted at a high temperature of 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV to form a low concentration N-type region 130 between P wells. For example, the total dose is 10¹⁴~Ten¹⁵cm^-2It is. As the N-type impurity, phosphorus, arsenic, or the like may be used in addition to nitrogen.
  Note that the order of ion implantation for forming each region is not limited to that shown in this example.
  In the process of FIG. 9 (b), for example, heat treatment is performed at 1000 to 1800 ° C. The implanted impurity is activated.
  In the step of FIG. 9C, the gate insulating film 90 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 80 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer film 70.
  After that, although not shown in the figure, the N relative to the interlayer film 70⁺Type source region 40 and P⁺A contact hole is formed on the mold contact region 50 to form a source electrode 60 (see FIG. 8). N⁺A metal film is deposited on the back surface of the substrate 10 as the drain electrode 140, and heat-treated at about 600 to 1400 ° C.Reference example 2As a result, the semiconductor device is completed.
[0023]
  Book as aboveReference exampleThe semiconductor device of N is formed on a semiconductor substrate.⁺Type SiC substrate 10 and N formed by being connected to SiC substrate 10⁻Type SiC epitaxial region 20, P type well region 30 formed in a predetermined region of the surface layer of SiC epitaxial region 20, and N formed in well region 30⁺N type source region 40, N connected to source region 40 and formed so that the side wall substantially coincides with the side wall of well region 30⁻Type storage channel region 110 and formed on the surface layer of SiC epitaxial region 20 connected to storage type channel region 110 and having a higher concentration than SiC epitaxial region 20 and higher than the P-type impurity concentration in well region 30 Low concentration, P-well low concentration N-type region 130, gate insulating film 90 formed on at least storage channel region 110, gate electrode 80 formed on gate insulating film 90, and SiC substrate A drain electrode 140 connected to the source electrode 10 and a source electrode 60 connected to the source region 40 are provided. 8 corresponds to the low-concentration region between wells of the first conductivity type in the claims. In this semiconductor device, the N-type impurity concentration in the low-concentration N-type region 130 between the P-wells is formed so as to be higher than the epitaxial region 20 and lower than the P-type impurity concentration in the P-type well region 30. . For this reason, even when a high drain electric field is applied, the gate insulating film 90 has 3 MVcm.^-1The above high electric field is not applied. In this semiconductor device, by forming such an N-type region 130 in a region below the gate insulating film 90, while suppressing a large electric field from being applied to the gate insulating film 90 with respect to a high drain electric field,Reference exampleThe on-resistance can be further reduced as compared with the first semiconductor device.
  Also bookReference exampleThe manufacturing method of the semiconductor device ofReference exampleIn addition to the semiconductor device manufacturing method of 1, a step of depositing a second mask material 154 on the semiconductor substrate, a step of patterning the mask material 154, and introducing impurities into the semiconductor substrate through the mask material 154 Thus, at least the step of forming the low concentration N-type region 130 between P wells is included. According to such a manufacturing method, the P well having a higher concentration in the region below the gate insulating film 90 than the SiC epitaxial region 20 and a lower N type impurity concentration than the P type impurity concentration in the P type well region 30. Since the low-concentration N-type region 130 is formed, while suppressing a large electric field on the gate insulating film 90 with respect to the high drain electric fieldReference exampleIt is possible to manufacture a semiconductor device in which the on-resistance is further reduced as compared with the first semiconductor device.
[0024]
  (Embodiment2)
  FIG. 10 shows an embodiment of a semiconductor device manufactured according to the present invention.2Is shown.
  As shown in the figure, high concentration N⁺N on type SiC substrate 10⁻A type SiC epitaxial region 20 is formed. Then, a P-type well region 31 is formed in a predetermined region in the surface layer portion of the epitaxial region 20, and N-type is formed in the P-type well region 31.⁺Type source region 40 and P⁺A mold contact region 50 is formed. The surface of the P-type well region 31 has N⁺N connected to type source region 40⁻A type storage channel region 110 is formed. The inverted channel region 121 is also formed on the surface layer of the P-type well region 31 with N⁻It is connected to the mold storage channel region 110. Further, a P-well low-concentration N-type region 131 is formed in the surface layer portion of the epitaxial region 20 so as to be connected to the inverted channel region 121. A gate electrode 80 is disposed on the inversion channel region 121 and the storage channel region 110 via a gate insulating film 90, and the gate electrode 80 is covered with an interlayer insulating film 70. And P⁺Type contact area 50 and N⁺A source electrode 60 is formed so as to be in contact with the type source region 40, and N⁺A drain electrode 140 is formed on the back surface of the type SiC substrate 10.
  Embodiment shown in FIG.1The difference in structure is that a low concentration N-type region 131 between P wells is formed in the surface layer portion of the epitaxial region 20 so as to be connected to the inversion channel region 121.
[0025]
  Next, an example of a method for manufacturing the semiconductor device described in this embodiment will be described with reference to cross-sectional views in FIGS. 5 (a) to 5 (e) and FIGS. 11 (a) to 11 (c).
  The steps of FIGS. 5 (a) to (e) are the embodiments.1Since this is the same as the process described in, the description thereof is omitted.
  In the step of FIG. 11 (a), using the mask material 154, for example, nitrogen ions 165 are implanted at a high temperature of 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV, and the low concentration N-type region 131 between the P wells is formed. Form. For example, the total dose is 10¹⁴~Ten¹⁵cm^-2It is. At this time, nitrogen ions are also implanted into the inverted channel region 120 (referred to as the inverted channel region 121), and a part of the P-type impurity is compensated by the nitrogen ions. The amount of nitrogen ions 165 to be implanted is set so as not to exceed the P-type impurity concentration in the inverted channel region 120. As the N-type impurity, phosphorus, arsenic, or the like may be used in addition to nitrogen.
  The order of ion implantation for forming each region is not limited to that shown in this example.
  In the step of FIG. 11 (b), for example, heat treatment is performed at 1000 to 1800 ° C. The implanted impurity is activated.
  In the step of FIG. 11C, the gate insulating film 90 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 80 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer film 70.
  After that, although not shown in the figure, the N relative to the interlayer film 70⁺Type source region 40 and P⁺A contact hole is formed on the mold contact region 50 to form a source electrode 60 (see FIG. 10). N⁺The metal film is deposited on the back surface of the substrate 10 as the drain electrode 140, and heat-treated at about 600 to 1400 ° C., for example, as an ohmic electrode, the embodiment shown in FIG.2As a result, the semiconductor device is completed.
[0026]
  As described above, the semiconductor device according to the present embodiment includes N formed on the semiconductor substrate.⁺Type SiC substrate 10 and N formed by being connected to SiC substrate 10⁻Type SiC epitaxial region 20, P type well region 31 formed in a predetermined region of the surface layer of SiC epitaxial region 20, and N formed in well region 31⁺Type source region 40, N connected to the source region 40 and formed in the surface layer in the well region 31⁻Type storage channel region 110, a P type inversion channel region 121 formed in the surface layer of the well region 31 between the storage type channel region 110 and the SiC epitaxial region 20, and the P type inversion channel region 121 And a low-concentration N-type region 131 between P wells having a higher concentration than the SiC epitaxial region 20 and a lower concentration than the P-type impurity concentration in the well region 31. A gate insulating film 90 formed on at least the inversion channel region 121 and the storage channel region 110, a gate electrode 80 formed on the gate insulating film 90, and a drain electrode 140 connected to the SiC substrate 10. And a source electrode 60 connected to the source region 40. In this semiconductor device, the P-well low concentration is higher in the region below the gate insulating film 90 than in the SiC epitaxial region 20 and has an N-type impurity concentration lower than the P-type impurity concentration in the P-type well region 31. Since the N-type region 131 is formed, it is possible to prevent the gate insulating film 90 from applying a large electric field to the high drain electric field while1The on-resistance can be further reduced as compared with this semiconductor device.
  Further, the P-well low concentration N-type region 131 in this semiconductor device is formed to have a higher concentration than the epitaxial region 20 and a lower concentration than the P-type impurity concentration in the P-type well region 31. For this reason, even when a high drain electric field is applied, the gate insulating film 90 has 3 MVcm.^-1The above high electric field is not applied. In this semiconductor device, the N-type region 131 is formed in a region under the gate insulating film 90, thereby suppressing the application of a large electric field to the gate insulating film 90 with respect to the high drain electric field.1The on-resistance can be further reduced as compared with this semiconductor device.
  Although the present invention has been specifically described above based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the scope of the invention.
[Brief description of the drawings]
FIG. 1 of the present inventionReference example 1Cross section showing
FIG. 2 of the present inventionReference example 1Sectional view showing the manufacturing process
FIG. 3 of the present inventionReference example 1Sectional view showing the manufacturing process
FIG. 4 The present inventionThe fruitForm of application1Cross section showing
FIG. 5 shows the present invention.The fruitForm of application1Sectional view showing the manufacturing process
FIG. 6The fruitForm of application1Sectional view showing the manufacturing process
FIG. 7 is an explanatory diagram of a taper etching process using resist receding.
[Fig. 8] of the present inventionReference example 2Cross section showing
FIG. 9 shows the present invention.Reference example 2Sectional view showing the manufacturing process
FIG. 10 shows the present invention.The fruitForm of application2Cross section showing
FIG. 11 shows the present invention.The fruitForm of application2Sectional view showing the manufacturing process
[Explanation of symbols]
10 ... N⁺Type SiC substrate
20 ... N⁻Type SiC epitaxial region
30, 31 ... P-type well region
40 ... N⁺Type source area
50 ・ ・ ・ P⁺Type contact area
60 ... Source electrode
70 ・ ・ ・ Interlayer film
80 ・ ・ ・ Gate electrode
90 ・ ・ ・ Gate insulation film
110 ... N⁻Type storage channel region
120, 121 ... P-type inverted channel region
130, 131 ... P-well low concentration N-type region
140 ... Drain electrode
150, 151, 152, 153, 154 ... Mask material
160, 162 ... Aluminum ion implantation
161, 164, 165, 166 ... Nitrogen ion implantation
163 ... Phosphorus ion implantation
170 ... Photoresist
180 ・ ・ ・ Mask material taper angle
190 ... P-type well region formed by ions penetrating the mask material

Claims (8)

A drain region of the first conductivity type formed in the semiconductor substrate, a drift region of the first conductivity type formed connected to the drain region, and a second conductivity type formed in a predetermined region of the drift region surface layer A well region; a first conductivity type source region formed in the well region; a first conductivity type storage channel region connected to the source region and formed in a surface layer in the well region; A second conductivity type inversion channel region formed on a surface layer of the well region between the accumulation channel region and the drift region, and formed at least on the inversion channel region and the accumulation channel region A gate insulating film, a gate electrode formed on the gate insulating film, a drain electrode connected to the drain region, a source electrode connected to the source region,
A semiconductor device comprising: A drain region of the first conductivity type formed in the semiconductor substrate, a drift region of the first conductivity type formed connected to the drain region, and a second conductivity type formed in a predetermined region of the drift region surface layer A well region; a first conductivity type source region formed in the well region; a first conductivity type storage channel region connected to the source region and formed in a surface layer in the well region; A second conductivity type inversion channel region formed in a surface layer of the well region between the accumulation type channel region and the drift region, and connected to the inversion channel region in the surface layer of the drift region. A low-concentration inter-well region of a first conductivity type having a higher concentration than the drift region and lower than a second conductivity type impurity concentration in the well region, and at least the inversion channel; A gate insulating film formed on the region and the storage channel region, a gate electrode formed on the gate insulating film, a drain electrode connected to the drain region, and a source electrode connected to the source region When,
A semiconductor device comprising: 3. The semiconductor device according to claim 1 , wherein the semiconductor device is a unit cell, and the shape of the inversion channel region is equal in all the unit cells. Said semiconductor substrate, a semiconductor device according to any one of claims 1 to 3, characterized in that a silicon carbide semiconductor. Depositing a first mask material on the semiconductor substrate; and patterning the first mask material;
Introducing a well region of the second conductivity type by introducing impurities into the semiconductor substrate through the first mask material;
Also in the introducing an impurity into the semiconductor body to the first mask material over, claims 1 to 4, characterized in that it comprises at least a step of forming a storage-type channel region of the first conductivity type in random order A method for manufacturing a semiconductor device according to any one of the above. A method of manufacturing a semiconductor device according to claim 2,
Depositing a first mask material on the semiconductor substrate; and patterning the first mask material;
Introducing a well region of the second conductivity type by introducing impurities into the semiconductor substrate through the first mask material;
A step of forming an accumulation channel region of the first conductivity type by introducing impurities into the semiconductor substrate also through the first mask material;
At least in random order,
Furthermore, a step of depositing a second mask material on the semiconductor substrate, a step of patterning the second mask material, and introducing impurities into the semiconductor substrate through the second mask material, Forming a low-concentration region between wells of the first conductivity type;
A method for manufacturing a semiconductor device, comprising: The patterning of the first mask material, manufacturing method of a semiconductor device according to claim 5 or 6, wherein the tilt pattern sidewalls of the first mask material is a step of etching to be provided. Wherein the semiconductor substrate manufacturing method of a semiconductor device according to any one of claims 5-7, characterized by using a silicon carbide semiconductor.

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