CN106531736B - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN106531736B
CN106531736B CN201610687196.5A CN201610687196A CN106531736B CN 106531736 B CN106531736 B CN 106531736B CN 201610687196 A CN201610687196 A CN 201610687196A CN 106531736 B CN106531736 B CN 106531736B
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薮内诚
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Renesas Electronics Corp
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Abstract

本申请涉及半导体器件。控制数据保持时间而不额外增加电路面积。半导体器件包括由鳍形成的数据缓冲器和触发器。作为延迟线,与鳍的栅极电极位于同一层中的栅极布线被设置在从数据缓冲器的数据输出节点到触发器的数据输入节点的数据信号路径中。

Description

半导体器件
相关申请的交叉引用
这里通过参考并入2015年9月11日提交的日本专利申请No.2015-179439的全部公开内容,包括说明书、附图和摘要。
技术领域
本发明涉及半导体器件,并且可适用于例如使用鳍型场效应晶体管(FET)的半导体器件。
背景技术
在与时钟同步操作的半导体集成电路的定时设计中重要的是,将数据信号的设置时间和保持时间保持在预定范围内。为此,在通常使用的半导体集成电路中,通过在数据信号线中提供串联的多个数据缓冲器来调整定时(例如,参见日本未审查专利公开No.Hei 7(1995)-66293[专利文献1])。
[专利文献]
[专利文献1]日本未审查专利公开No.Hei 7(1995)-66293
发明内容
随着半导体集成电路的小型化的进展,时钟信号线中的延迟量增加,尤其带来数据保持时间的增加的问题。尤其是,在使用鳍型FET(称为“鳍式FET”)的半导体集成电路中,数据保持时间的增加非常显著。为了解决该问题,当过去试图通过提供串联的多个数据缓冲器来调整数据信号的延迟量时,要求数据缓冲器的数量,增加了电路面积。
其他问题和新颖性特征将从本文的说明书和附图中变得显而易见。
在一个实施例中,半导体器件包括由鳍式FET形成的触发器和数据缓冲器。对于延迟线,在从数据缓冲器的数据输出节点到触发器的数据输入节点的数据信号的路径中,设置与鳍式FET的栅极电极位于同一层中的栅极布线。
根据上述实施例,可以控制数据保持时间而不过量增加电路面积。
附图说明
图1是示出根据第一实施例的半导体器件的一般结构的框图;
图2是示出图1的存储电路的结构的框图;
图3是用于说明设置时间和保持时间的定时图;
图4是示意性示出鳍型场效应晶体管的结构的立体图;
图5是示出图2所示的数据缓冲器、延迟线和触发器的数据输入部的具体结构的平面图;
图6是沿着图5的线VI-VI截取的截面图;
图7是沿着图5的线VII-VII截取的截面图;
图8是图5所示数据缓冲器31和33以及延迟线32的等效电路图;
图9以表格形式示出了数据设置时间和数据保持时间的模拟结果;
图10示意性示出了数据保持时间与PVT条件之间的关系;
图11是示出根据第二实施例的半导体器件中的存储电路的结构的框图;
图12是示出根据第三实施例的半导体器件中的存储电路的结构的框图;以及
图13是示出根据第四实施例的半导体器件中的存储电路的结构的框图。
具体实施方式
现在,参照附图,将详细描述每个实施例。以下将计算机芯片示为半导体器件1的示例,并且将具体解释其存储单元中的输入/输出电路。然而,以下技术不限于用于存储单元,通常它们可被广泛用于与时钟信号同步操作的半导体电路。
在以下每个实施例的附图中,相同或对应的部分可以通过相同的参考符号表示,并且不再重复其描述。为了使附图清楚,示出半导体器件的结构的平面图、截面图和立体图中的尺寸大小与半导体器件中的实际尺寸大小不成比例。
<第一实施例>
[半导体器件的一般结构]图1是示出根据第一实施例的半导体器件的一般结构的框图。在图1中,半导体芯片被示为半导体器件1的示例。参照图1,半导体器件1包括:CPU(中央处理单元)2;存储电路3;接口(I/O:输入和输出)电路4;其他外围电路(未示出);以及内部总线5,用于耦合这些组成元件。
CPU 2通过根据程序进行操作来执行整个半导体器件1的控制。存储电路3用作主存储装置,诸如RAM(随机存取存储器)和ROM(只读存储器)。尽管在图1中将一个存储电路3示为典型示例,但实际上,包括有多种存储电路,诸如DRAM(动态随机存取存储器)、SRAM(静态随机存取存储器)和闪存。接口电路4被用于半导体器件的外部耦合。这些组成元件相互之间通过内部总线5交换数据信号D、地址信号ADR、控制信号CS等。
[存储电路的结构]图2是示出图1的存储电路的结构的框图。参照图2,存储电路3包括:存储单元阵列10;I/O电路11;字线驱动器12;以及控制电路13。形成存储电路3的每个晶体管包括鳍式FET。
存储单元阵列10包括在行方向(Y方向)和列方向(X方向)上以行和列布置的多个存储单元(未示出)。每个存储单元都存储一位的信息。在存储单元阵列中,设置有与相应行相对应的字线(未示出)以及与相应列相对应的位线BL[0]-BL[127]。此外,位线的数量仅仅是示例而不用于限制。
I/O电路11是用于在图1所示内部总线5和存储单元阵列10之间执行写数据的输入和读数据的输出的接口。在图2中,仅示出了用于输入写数据的电路部分。具体地,I/O电路11接收来自图1所示内部总线5的128位数据信号D[0]-D[127],并将它们输出至相应的位线BL[0]-BL[127]。
如图2所示,对应于每个数据信号D,I/O电路11包括:数据缓冲器31和33;延迟线32;以及D型触发器34。针对输入至存储电路3的每一位的数据信号D被进一步通过数据缓冲器31、延迟线32和数据缓冲器33输入至触发器34的数据输入节点。设置数据缓冲器33以对已经经过延迟线32的数据信号进行整形,但这不是必须的。将在图5至图7中解释延迟线32以及数据缓冲器31和33的更详细的结构。如稍后所描述的,根据本实施例,延迟线32被形成为利用以鳍式FET为特征的结构。
此外,代替图2的D型触发器34,可以使用D型锁存电路。响应于时钟信号的边缘(例如,前缘),D型触发器34在时钟信号的边缘紧前保持输入信号。另一方面,例如,D型锁存电路使得信号在时钟信号处于高电平(H电平)时允许信号通过,并且在时钟信号切换至低电平(L电平)紧前保持输入信号(H电平和L电平可以相反)。触发器34和锁存电路的相似之处在于,它们是用于与时钟信号CLK同步地保持数据信号D的逻辑电路。
字线驱动器12激活行(从中读取数据或者向其写入数据)的字线(未示出)。因此,从中读取数据或者向其写入数据的行的每个存储单元耦合至对应的位线BL。
控制电路13通过内部总线5接收来自图1的CPU 2或DMA(直接存储器存取)控制器(未示出)等的控制信号CS,并且基于控制信号CS控制存储电路3的整体操作。控制信号CS包括提供给I/O电路11中设置的每个触发器34的时钟信号CLK。通过设置在控制电路13中的时钟缓冲器20,时钟信号CLK被输入至每个触发器34的时钟输入节点(图8中的参考符号“CKin”)。
[定时控制的问题]以下将解释图2所示存储电路3的I/O电路11中的定时控制的问题。
图3是用于解释设置时间和保持时间的定时图。在图3的定时图中,示出了将被输入至图2的每个触发器34中的时钟信号CLK和数据信号D。
参照图3,在时钟信号CLK的前缘(时间t1)处,触发器34接收数据信号D。为了确保数据信号D的接收,需要在时钟信号的前缘之前的规定时间内确定数据。该时段被称为数据信号D的“设置时间TSU(从时间t0到时间t1)”。另一方面,在时钟信号的后缘之后,应该保持数据信号的时段被称为数据信号D的“保持时间TH(从时间t1到时间t2)”。
如图2所示,在存储电路3的I/O电路11中,通常时钟信号CLK的传输路径(时钟路径25)长于数据信号D的传输路径(数据路径)。因此,如以下的等式(1)所示,保持时间TH被定义为通过从时钟信号的延迟时间DLY(CLK)中减去数据信号的延迟时间DLY(D)而得到的值。
TH=delay(CLK)-delay(D) (1)
时钟信号CLK的延迟时间通过时钟缓冲器20的延迟时间DLY(CLK;Tr)与图2的时钟路径的延迟时间DLY(CLK;wire)的总和来给出。另一方面,数据信号D的延迟时间通过数据缓冲器31和33的延迟时间n×DLY(D;Tr)(其中,“b”是数据缓冲器的级数)与延迟线32的延迟时间DLY(D;line)的总和来给出。由于数据路径本身的延迟时间较短,所以其无关紧要。因此,上述等式(1)被重写为以下等式(2)。
TH=DLY(CLK;Tr)+DLY(CLK;wire)-n×DLY(D;Tr)-DLY(D;line) (2)
当每个数据缓冲器和触发器34由鳍式FET形成时,由于布线的减薄引起的布线阻抗的增加以及局部布线(LIC:局部互连)与鳍式FET的栅极电极之间的寄生电容的增加影响布线延迟DLY(CLK;wire)。结果,数据保持时间TH趋于变得比通常使用的平面型FET更长。
为了解决上述问题,当串联耦合多个数据缓冲器31和33而不设置图2的延迟线32时,电路面积将增加。此外,当多个数据缓冲器31和33串联耦合时,即使PVT条件(工艺、电压、温度)被设定为最小化延迟量(称为“MIN条件”),也会产生数据保持时间几乎不减少的问题。由以下原因引起该问题:在MIN条件的情况下,即使时钟缓冲器的延迟时间DLY(CLK;Tr)和数据缓冲器的延迟时间n×DLY(D;Tr)减少,时钟路径的延迟时间DLY(CLK;wire)也几乎不减少。
考虑上述方面,根据本实施例,在每一位的数据信号D的路径中设置延迟线32。如将在图5至图7中解释的,根据本实施例,延迟线32的面积减小通过利用以鳍式FET为特征的结构来实现。
[鳍式FET的结构]首先,将简要说明鳍式FET的结构及其制造方法。
图4是示意性示出鳍式FET的结构的立体图。参照图4,鳍式FET例如包括设置在P型半导体衬底SUB上方的多个鳍式布线F1和F2。每个鳍式布线F1和F2都在X方向上沿着衬底平面延伸。每个鳍式布线F1和F2都通过选择性地蚀刻半导体衬底SUB的表面来形成。在相邻的鳍式布线F之间(不形成鳍式布线F1和F2的部分),设置例如通过使用CVD(化学气相沉积)方法形成的氧化硅膜作为元件隔离膜ISO。
栅极电极G被形成为通过栅极绝缘膜GI覆盖相应鳍式布线F1和F2的上表面和侧表面。栅极电极G在Y方向(其是与鳍式布线F1和F2相交的方向)上延伸。栅极电极G例如可以由半导体(诸如多晶硅)、导电化合物(诸如氮化钛)和单金属(诸如钨)或包含上述任何组成的层压膜来形成。
在形成栅极电极G之后,通过将栅极电极G用作掩膜在鳍布线F中引入杂质,在除被栅极电极G包围的沟道区域之外的部分中形成源极区域和漏极区域(未示出)。关于这点,当提供PMOS(P沟道金属氧化物半导体)晶体管时,鳍式布线F形成在N型阱上方,并且P型杂质被引入到鳍式布线F中。另一方面,当提供NMOS(N沟道金属氧化物半导体)晶体管时,鳍式布线F形成在P型衬底或P型阱上方,并且N型杂质被引入鳍式布线F中。
为了与源极区域和漏极区域的上表面和侧表面欧姆接触,使用诸如钨的单金属,分别形成在Y方向上延伸的局部布线(LIC:局部互连)LA1和LA2。即,局部布线LA1和LA2分别用作源极电极和漏极电极。栅极布线G、源极电极LA1和漏极电极LA2进一步直接耦合至在X方向上延伸的局部布线(未示出)或者通过形成在层间绝缘层(未示出)中的过孔耦合至上部金属布线层(未示出)。
[延迟线和数据缓冲器的结构]基于鳍式FET的上述结构,形成图2所示的数据缓冲器31、33、延迟线32和触发器34。
图5是示出图2所示的数据缓冲器、延迟线和触发器的数据输入部的具体结构的平面图。图6是沿着图5的线VI-VI截取的截面图。图7是沿着图5的线VII-VII截取的截面图。图8是图5所示数据缓冲器31和33以及延迟线32的等效电路图。在图5至图7中,作为触发器34的数据输入部分,示出了由PMOS晶体管和NMOS晶体管形成的CMOS反相器。在图5的平面图中,为了使附图清楚,对鳍式布线F1-F18赋予倾斜线图案的阴影,以及对N型阱NW1和NW2赋予点图案的阴影。在图5至图7中,衬底平面中的方向被称为“X方向”和“Y方向”,以及垂直于衬底的方向被称为“Z方向”。
参照图5至图7,在P型半导体衬底SUB(包括N型阱NW1和NW2的区域)上方,形成均在X方向上延伸的多个鳍式布线F1-F18。为了使图案化更加精确,鳍式布线F1-F18具有相等宽度,并且基本以规则的间隔来布置。还具有衬底上方没有形成鳍式布线的部分。用作PMOS晶体管的鳍式布线F1和F2形成在N型阱NW1上方。类似地,用作PMOS晶体管的鳍式布线F11、F12、F15和F16形成在N型阱NW2上方。
多个栅极布线G1-G16被形成为使得分别在与鳍式布线F1-F18的延伸方向(X)方向相交的Y方向上延伸。为了使图案化更加精确,栅极布线G1-G16具有相等宽度,并且以规则的间隔在X方向上布置。栅极绝缘膜GI放置在栅极布线G1-G3、G5-G8、G10-G12、G14-G16与鳍式布线F之间。
栅极布线G1-G16包括被用作鳍式FET的栅极电极的那些布线(G2、G11和G15)、仅用作局部布线的那些布线(G1、G3、G4、G5、G8、G9、G10、G12、G13、G14和G16)以及被用作栅极电极和局部布线二者的那些布线(G6和G7)。在图5和图6中,仅用作局部布线的栅极布线(诸如G1、G3、G5、G8、G10、G12、G14和G16)也通过栅极绝缘膜GI耦合至鳍式布线F。然而,这些栅极布线不是必须电耦合至鳍式布线。
在相邻的栅极布线G之间,局部布线LA1-LA9被分别设置为覆盖鳍式布线F的一部分并且与鳍式布线F欧姆接触。每个局部布线LA1-LA9都被形成为在Y方向上延伸(沿着栅极布线G的延伸方向)。
在相邻的栅极布线G和局部布线LA1之间以及在相邻的栅极布线G之间,存在通过使用CVD方法形成的填充绝缘膜(未示出),诸如氧化硅膜。每个局部布线LB1-LB9都形成在填充绝缘膜之上以在X方向上延伸。在X方向上延伸的每个局部布线LB1-LB9都耦合在Y方向上延伸的相邻的栅极布线G或相邻的栅极布线G和局部布线LA。在这种情况下,每个局部布线LB都直接与局部布线LA耦合(即,不经过形成在层间绝缘层中的过孔)。局部布线LB还分别直接与栅极布线G耦合(不经过形成在绝缘层中的过孔)。
例如,在图7中,局部布线LB2直接耦合至栅极布线G3和G4的上表面。局部布线LB4直接耦合至栅极布线G5和G6的上表面。局部布线LB6直接耦合至栅极布线G7和G8的上表面。局部布线LB8直接耦合至栅极布线G9和G10的上表面。局部布线LB10直接耦合至在Y方向上延伸的局部布线LA9的侧表面并且还直接耦合至栅极布线G12的上表面。局部布线LB12直接耦合至栅极布线G13和G14的上表面。
如图8所示,反相器IN1和IN2分别被用作数据缓冲器31和33。参照图5至图7,反相器INV1(数据缓冲器31)包括:鳍式布线F1-F4;栅极布线G2;以及局部布线LA1-LA3。鳍式布线F1和F2被用作用于形成反相器IN1的PMOS晶体管的沟道区域、源极区域和漏极区域。局部布线LA1被用作PMOS晶体管的源极电极,并且通过形成在层间绝缘层(未示出)中的过孔(未示出)耦合至上金属布线层中设置的电源布线(未示出)。结果,向局部布线LA1给出电源电位VDD。
类似地,鳍式布线F3和F4被用作用于形成反相器INV1的NMOS晶体管的沟道区域、源极区域和漏极区域。局部布线LA2被用作NMOS晶体管的源极电极,并且通过形成在层间绝缘层(未示出)中的过孔(未示出)耦合至上金属布线层中设置的接地布线(未示出)。结果,向局部布线LA1给出接地电位VSS。栅极布线G2对应于图8所示反相器INV1的数据输入节点Nin1,并且作为栅极电极在形成反相器INV1的NMOS晶体管和PMOS晶体管之间共享。局部布线LA3(具体地,由图5中的箭头40表示的从鳍式布线F1到鳍式布线F4的部分)对应于图8所示反相器INV1的数据输出节点Nout1,并且在PMOS晶体管和NMOS晶体管之间共享为漏极电极。
反相器INV2(数据缓冲器33)包括鳍式布线F11-F14、栅极布线G11和局部布线LA7-LA9。鳍式布线F11和F12被用作用于形成反相器INV2的PMOS晶体管的沟道区域、源极区域和漏极区域。局部布线LA7被用作PMOS晶体管的源极电极,并且通过形成在层间绝缘层(未示出)中的过孔(未示出)耦合至上金属布线层中设置的电源布线(未示出)。结果,向局部布线LA7给出电源电位VDD。
类似地,鳍式布线F13和F14被用作用于形成反相器INV2的NMOS晶体管的沟道区域、源极区域和漏极区域。局部布线LA8被用作NMOS晶体管的源极电极,并且通过形成在层间绝缘层(未示出)中的过孔(未示出)耦合至上金属布线层中设置的接地布线(未示出)。结果,向局部布线LA7给出接地电位VSS。栅极布线G11对应于图8所示反相器INV2的数据输入节点Nin2,并且在PMOS晶体管和NMOS晶体管之间共享为栅极电极。局部布线LA9对应于图8所示反相器INV2的数据输出节点Nout2,并且在PMOS晶体管和NMOS晶体管之间共享为漏极电极。
图5进一步示出了用于形成触发器34的输入部分的反相器34_Din。用于形成输入部分的反相器34_Din包括鳍式布线F15-F18、栅极布线G15和局部布线LA10-LA12。鳍式布线F15和F16被用作用于形成反相器34_Din的PMOS晶体管的沟道区域、源极区域和漏极区域。局部布线LA10被用作PMOS晶体管的源极电极,并且通过形成在层间绝缘层(未示出)中的过孔(未示出)耦合至上金属布线层中设置的电源布线(未示出)。结果,向局部布线LA10给出电源电位VDD。
类似地,鳍式布线F17和F18被用作用于形成反相器34_Din的NMOS晶体管的沟道区域、源极区域和漏极区域。局部布线LA11被用作NMOS晶体管的源极电极,并且通过形成在层间绝缘层(未示出)中的过孔(未示出)耦合至上金属布线层中设置的接地布线(未示出)。结果,向局部布线LA11给出接地电位VSS。栅极布线G15(具体地,由图5中的箭头41示出的从鳍式布线F15到鳍式布线F18的部分)对应于图8所示触发器34的数据输入节点Din,并且在PMOS晶体管和NMOS晶体管之间共享为栅极电极。
延迟线32设置在上述反相器INV1(数据缓冲器31)的数据输出节点Nout1(局部布线LA3)与反相器INV2(数据缓冲器33)的数据输入节点Nin2(栅极布线G11)之间。延迟线32包括栅极布线G3-G10以及用于耦合相邻的栅极布线的局部布线LB2-LB8。栅极布线G3通过局部布线LB1耦合至反相器INV1(数据缓冲器31)的数据输出节点Nout1(局部布线LA3)。栅极布线G10通过局部布线LB9耦合至反相器INV2(数据缓冲器33)的数据输入节点Nin2(栅极布线G11)。因此,数据信号依次被传输通过局部布线LB1、栅极布线G3、局部布线LB2、栅极布线G4、局部布线LB3、栅极布线G5、局部布线LB4、栅极布线G6、局部布线LB5、栅极布线G7、局部布线LB6、栅极布线G8、局部布线LB7、栅极布线G9、局部布线LB8、栅极布线G10和局部布线LB9。
关于这点,数据信号D从输出缓冲器31(反相器INV1)的数据输出节点Nout1(由箭头40表示的局部布线LA3的部分)到触发器34的数据输入节点Din(由箭头41表示的栅极布线G15的部分)的路径经过栅极布线G3-G14和局部布线LB1-LB13。因此,从垂直于衬底的方向(Z方向)在半导体衬底SUB的平面中看到,数据信号D从数据输出节点Nout1到数据输入节点Din的路径长度长于接合数据输出节点Nout1和数据输入节点Din的直线路径42。如图6所示,直线路径42从局部布线LA3的右端(+X方向侧)到栅极布线G15的左端(-X方向侧)延伸。如图5所示,直线路径42不限于沿着X方向的路径,并且其可以沿着倾斜方向(或者可以沿着任何方向,只要是经过由箭头40和箭头41表示的部分的直线即可)。
此外,优选地,如图8所示,延迟线32与接地节点(接地布线)耦合,这通过电容元件T1和T2给出接地电位VSS。由延迟线32产生的延迟时间可以进一步通过由电容元件带来的CR延迟而增加。
通过使用鳍式FET的栅极电容来形成电容元件T1和T2。具体地,如图5和图6所示,作为电容元件T1的鳍式FET包括:鳍式布线F5-F10;栅极布线G6,用作栅极电极;以及局部布线LA4和LA5,用作源极电极和漏极电极。另一方面,作为电容元件T2的鳍式FET包括:鳍式布线F5-F10;栅极布线G7,用作栅极电极;以及局部布线LA5和LA6,用作源极电极和漏极电极。鳍式布线F5-F10以及局部布线LA5被鳍式FET共享。局部布线LA4-LA6通过形成在层间绝缘层(未示出)中的过孔(未示出)耦合至上金属布线层中设置的接地布线(未示出)。结果,向局部布线LA4-LA6给出接地电位VSS。
[第一实施例的效果]如上所述,可以通过在数据信号D的路径中设置延迟线32以及通过形成包括栅极布线G的延迟线32来使得数据路径的布线长度更长。与仅通过数据缓冲器调整延迟时间的常用方法相比,可以使得整个电路面积更小。
期望使用诸如钨的金属材料形成栅极布线G。金属栅极布线的延迟时间的电压和温度依赖性是类似于上层中的金属布线的特性。因此,可以使得数据保持时间的PVT(工艺,电压,温度)依赖性更大。以下将参照图9和图10所示的模拟结果来给出详细说明。
图9以表格形式示出了数据设置时间和数据保持时间的模拟结果。图10示意性示出了数据保持时间和PVT条件之间的关系。在图9和图10中,存在对设置图5至图8中解释的延迟线32的情况与代替延迟线设置数据缓冲器的情况的比较。
参照图9和图10,MIN条件是数据信号的延迟变得最小的情况。具体地,在MIN条件的情况下,半导体器件的工艺条件是PMOS晶体管和NMOS晶体管的开关速度变为最高(漏极电流变得最大)。半导体器件的操作条件为:高电压(0.88V)和高温度(125℃)。MAX条件是数据信号的延迟变得最大的条件。具体地,在MAX条件的情况下,半导体器件的工艺条件是PMOS晶体管和NMOS晶体管的开关速度变得最低(漏极电流变得最小)。半导体器件的操作条件为:低电压(0.72V)和低温度(-40℃)。
如图9所示,当通过串联耦合多个数据缓冲器形成延迟电路而不使用上述延迟线32时,即使PVT条件从MAX条件切换到MIN条件,数据保持时间(时钟路径的延迟时间与数据路径的延迟时间之间的差)也仅减小至88%。另一方面,当PVT条件从MAX条件切换到MIN条件时,利用本实施例的延迟线32,数据保持时间减小至54%。
如上所述,根据本实施例的半导体器件,数据路径的延迟时间(在常用方法中通过使用多个数据缓冲器来增加)通过代替数据缓冲器设置延迟线32(即,通过加长数据路径的布线)来增加。以这种方式,同样当PVT条件被设置为MIN条件时,数据路径的延迟时间不会显著降低,抵消时钟路径的布线延迟。结果,可以缩短数据保持时间。
此外,与通过串联耦合多个数据缓冲器形成延迟电路的情况相比,可以利用上述延迟线32来减少数据缓冲器的数量,这使得可以减小电路面积。具体地,根据本实施例,对于延迟线32,通过使用与用于鳍式FET的栅极电极位于同一布线层中的栅极布线G来实现进一步的面积减小。
<第二实施例>图11是示出根据第二实施例的半导体器件中的存储电路的结构的框图。图11的存储电路3中的I/O电路11与图2的I/O电路11的不同在于,在用于传输时钟信号CLK的时钟路径25的中部设置中继缓冲器21。具体地,在图11中,中继缓冲器21设置在用于数据信号D[63]的触发器34[63]和用于数据信号D[64]的触发器34[64]之间。由时钟缓冲器20共享的时钟信号CLK进一步被中继缓冲器21整形。由于图11所示的其他方面基本与图2所示相同,所以由相同的参考符号表示相同或对应部分,并且不再重复其描述。
通过设置中继缓冲器21,由时钟缓冲器20驱动的触发器34的数量减少一半,并且时钟路径25的布线长度也减小一半。通过中继缓冲器21来驱动触发器34的剩余一半和时钟路径25的一半。因此,即使中继缓冲器21的栅极延迟增加,由晶体管的栅极引起的布线延迟和寄生电容也可以更多地减小。从而,可以进一步减小整个传输路径的时钟信号的延迟时间。
在上述等式(2)中,通过减小时钟路径的延迟时间DLY(CLK;wire),当PVT条件被设置为MIN条件时,可以更加缩短数据保持时间。此外,当缩短时钟路径的延迟时间时,由延迟线32产生的数据路径的延迟时间可以相应缩短,这允许进一步减小每个延迟线32的面积。
<第三实施例>图12是示出根据第三实施例的半导体器件中的存储电路的结构的框图。图12的存储电路3中的I/O电路11与图2的I/O电路11的不同在于,时钟路径25为树状形状。即,根据第三实施例,时钟信号CLK通过树状信号路径被输入至多个触发器34[0]-34[127]。中继缓冲器被设置在时钟信号CLK的分支点处。
在图12的情况下,具体地,时钟路径被分至为两个。一个时钟路径通过中继缓冲器22耦合至每个触发器34[0]-34[63]的时钟输入节点。另一时钟路径通过中继缓冲器22耦合至每个触发器34[64]-34[127]的时钟输入节点。由于图12所示的其他方面与图2所示的基本相同,所以由相同的参考符号描述相同或对应的部分,并且不再重复其描述。
通过设置中继缓冲器22和23,如第二实施例的情况中那样,可以减小整个传输路径的时钟信号的延迟时间。因此,当PVT条件被设置为MIN条件时,可以使得数据保持时间更短。当缩短时钟路径的延迟时间时,据此可以缩短由延迟线32产生的数据路径的延迟时间,这允许减小每个延迟线32的面积。
此外,通过形成树状形状的时钟路径,从时钟缓冲器20到每个触发器34的时钟输入节点的时钟路径的长度可以一致。因此,由于可以使得用于每个触发器34的时钟信号的延迟时间一致,所以可以改善数据保持时间。
<第四实施例>图13是示出根据第四实施例的半导体器件中的存储电路的结构的框图。图13的存储电路3中的I/O电路11与图2的I/O电路的不同在于,从时钟缓冲器20的数据输出节点到每个触发器34的时钟输入节点的时钟信号的路径长度越长,耦合至数据输出节点的延迟线32的延迟时间越长。具体地,在图13所示的情况下,用于数据信号D[127]的延迟线132[127]的延迟时间最长,并且用于数据信号D[0]的延迟线32[0]的延迟时间最短。延迟线的路径长度设置得越长,或者耦合的电容元件的数量或电容越大,延迟线32的延迟时间变得越长。由于图13所示的其他方面与图2所示基本相同,所以通过相同的参考标号表示相同或对应的部分,并且不再重复其描述。
从时钟缓冲器20的时钟输出节点开始的路径长度越长,输入至每个触发器34的时钟信号的延迟时间越长。因此,通过响应于时钟信号的延迟时间增加数据信号的延迟时间,可以更多地减少数据保持时间。
在上文中,基于实施例具体说明了发明人做出的本发明,但是本发明不限于上述实施例,并且不需要说,在不背离本发明的精神的情况下可以做出各种变化。

Claims (12)

1.一种半导体器件,包括:
至少一个逻辑电路,形成在半导体衬底上方,包括用于接收数据信号的数据输入节点和用于接收时钟信号的时钟输入节点,并且包括鳍型场效应晶体管;以及
至少一个数据缓冲器,形成在所述半导体衬底上方,包括耦合至所述逻辑电路的数据输入节点的数据输出节点,并且包括鳍型场效应晶体管,
其中,从所述数据缓冲器的数据输出节点到所述逻辑电路的数据输入节点的数据信号的路径包括与形成所述逻辑电路和所述数据缓冲器的所述鳍型场效应晶体管的栅极电极位于同一层中的栅极布线,并且
其中,如在所述半导体衬底的平面中看到的,从所述数据输出节点到所述数据输入节点的数据信号的路径长度长于所述数据输出节点和所述数据输入节点之间的直线。
2.根据权利要求1所述的半导体器件,还包括:电容元件,耦合至从所述数据输出节点到所述数据输入节点的数据信号的路径,
其中,所述电容元件是通过使用所述鳍型场效应晶体管的栅极电容来形成的。
3.根据权利要求1所述的半导体器件,
其中,从所述数据输出节点到所述数据输入节点的数据信号的路径包括:
多个栅极布线;以及
局部布线,用于耦合彼此相邻的所述栅极布线。
4.根据权利要求1所述的半导体器件,其中,所述逻辑电路包括D型触发器或D型锁存电路。
5.根据权利要求1所述的半导体器件,其中,所述数据缓冲器包括反相器。
6.根据权利要求1所述的半导体器件,包括:
所述逻辑电路;以及
所述数据缓冲器,分别对应于所述逻辑电路,
其中,每个所述数据缓冲器接收各自对应的数据信号并将整形后的数据信号输出至对应的逻辑电路,并且
其中,每个所述逻辑电路接收所述时钟信号作为公共信号。
7.根据权利要求6所述的半导体器件,包括存储电路,
其中,所述逻辑电路和所述数据缓冲器被设置在所述存储电路的输入/输出电路中,并且
其中,公共时钟信号和各自对应于所述数据缓冲器的数据信号被输入至所述输入/输出电路。
8.根据权利要求6所述的半导体器件,还包括:
第一时钟缓冲器,用于对所述时钟信号进行整形;以及
第二时钟缓冲器,用于对由所述第一时钟缓冲器整形的所述时钟信号进行进一步整形,
其中,由所述第一时钟缓冲器整形的所述时钟信号被输入至所述逻辑电路的一部分,并且
其中,由所述第二时钟缓冲器整形的所述时钟信号被输入至所述逻辑电路的剩余部分。
9.根据权利要求6所述的半导体器件,其中,所述时钟信号通过树状信号路径输入至所述逻辑电路。
10.根据权利要求6所述的半导体器件,还包括用于对时钟信号进行整形的时钟缓冲器,
其中,在每个所述逻辑电路中,从时钟输出节点到所述时钟缓冲器的时钟输入节点的时钟信号的路径长度越长,从所述数据输出节点到对应数据缓冲器的数据输入节点的数据信号的路径长度变得越长。
11.根据权利要求6所述的半导体器件,还包括:
时钟缓冲器,用于对所述时钟信号进行整形;以及
电容元件,每一个所述电容元件耦合至从每个所述数据缓冲器的数据输出节点到对应逻辑电路的数据输入节点的数据信号的路径,
其中,使用鳍型场效应晶体管的栅极电容来形成所述电容元件,并且
其中,在每个所述逻辑电路中,从时钟输出节点到所述时钟缓冲器的时钟输入节点的时钟信号的路径长度越长,耦合至从所述数据输出节点到对应数据缓冲器的数据输入节点的数据信号的路径的所述电容元件的电容或数量变得越大。
12.一种半导体器件,包括:
逻辑电路,包括用于接收数据信号的数据输入节点和用于接收时钟信号的时钟输入节点,并且包括鳍型场效应晶体管;
数据缓冲器,包括耦合至所述逻辑电路的数据输入节点的数据输出节点,并且包括鳍型场效应晶体管;以及
延迟线,设置在所述数据缓冲器和所述逻辑电路之间,
其中,所述延迟线包括:
鳍式布线,与形成所述逻辑电路和所述数据缓冲器的鳍型场效应晶体管的鳍形成在同一层中并且在第一方向上延伸;和
第一栅极布线、第二栅极布线和第三栅极布线,在与所述第一方向相交的第二方向上延伸,与所述鳍型场效应晶体管的栅极电极形成在同一层中,并且依次布置在所述第一方向上,
其中,所述第二栅极布线通过栅极绝缘膜耦合至所述鳍式布线,
其中,所述延迟线还包括:
第一局部布线,设置在所述第一栅极布线和所述第二栅极布线之间,耦合至所述鳍式布线,并且给出参考电位;和
第二局部布线,设置在所述第二栅极布线和所述第三栅极布线之间,耦合至所述鳍式布线,并且给出所述参考电位,以及
其中,所述逻辑电路的数据输入节点和所述数据缓冲器的数据输出节点通过所述第一至第三栅极布线耦合。
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