CN106340456B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN106340456B
CN106340456B CN201510793708.1A CN201510793708A CN106340456B CN 106340456 B CN106340456 B CN 106340456B CN 201510793708 A CN201510793708 A CN 201510793708A CN 106340456 B CN106340456 B CN 106340456B
Authority
CN
China
Prior art keywords
layer
semiconductor layer
semiconductor
fin structure
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510793708.1A
Other languages
English (en)
Other versions
CN106340456A (zh
Inventor
陈昭雄
陈豪育
林其渊
赵元舜
李国龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106340456A publication Critical patent/CN106340456A/zh
Application granted granted Critical
Publication of CN106340456B publication Critical patent/CN106340456B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

在一种制造半导体装置的方法中，形成鳍片结构，包含第一半导体层、置于第一半导体层上的氧化层及置于氧化层上的第二半导体层。形成隔离绝缘层，使得鳍片结构内的第二半导体层突出自隔离绝缘层；而氧化层及第一半导体层则埋于阻隔绝缘层之中。形成第三半导体层于裸露的第二半导体层之上，以形成通道层。藉由此通道层以回复通道宽度，能进行氧化制程以完全形成氧化层，而毋须顾及通道宽度的减小。这使得形成氧化层的制程视窗(process window)变得更广。此外，由于能缩小鳍片结构的宽度(蚀刻制程后)，所以完全形成氧化层的时间可以缩短，因此降低热经历(thermal history)。

Description

半导体装置及其制造方法
技术领域
本揭示内容是有关于半导体集成电路领域，特别是有关于一种具有鳍片结构的半导体集成电路及其制造方法。
背景技术
随着半导体产业已进入纳米等级，为了追求更高的装置密度、更佳的效能及更低的成本，于是发展出三维结构的设计，例如：鳍式场效晶体管(Fin FET)，以克服制造和设计上的瓶颈。一般来说，鳍式场效晶体管包含高深宽比的半导体鳍片，并于半导体鳍片中形成半导体晶体管的装置，像是通道和源极/漏极区域。栅极形成于鳍片之上并沿着鳍片的侧边(即包裹着鳍片)。藉由增加通道和源极/漏极区域的表面面积，以产生更快、更可靠且更易控制的半导体晶体管装置。在一些装置中，鳍式场效晶体管的源极/漏极部分使用应变材料(例如：锗化硅(SiGe)、磷化硅(SiP)或碳化硅(SiC))以提高载子迁移性。此外，通道位于氧化物结构之上可提升载子迁移性和维持笔直的鳍片形状。而且，鳍式场效晶体管的源极/漏极部分也可使用变形材料如选择性成长的锗化硅，以提升载子迁移性。举例来说，施加收缩应力于P型金氧半晶体管(PMOS)的通道可优化通道中的空穴迁移性。同样地，施加拉伸应力于N型金氧半导体(NMOS)的通道可优化通道中的电子迁移性。然而，在互补式金氧半场效晶体管(CMOS)制造中，实施上述的特征或制程是有困难的。
发明内容
根据本揭露内容的一面向，在一种制造半导体装置的方法中，形成鳍片结构、第一半导体层、置于第一半导体层上的氧化层和置于氧化层上的第二半导体层。形成隔离绝缘层，使得鳍片结构的第二半导体层突出于隔离绝缘层并裸露出来；而氧化层及第一半导体层则埋于隔离绝缘层之中。形成第三半导体层于暴露的第二半导体层上以形成通道层。
根据本揭露内容的另一面向，在一种制造半导体装置的方法中，形成堆叠半导体层。此堆叠包含第一半导体层、形成于第一半导体层上的中间半导体层和形成于中间半导体层上的第二半导体层。藉由图案化第一半导体层、中间半导体层及第二半导体层，以形成鳍片结构。氧化鳍片结构内的中间半导体层。形成隔离绝缘层，使得鳍片结构的第二半导体层突出于隔离绝缘层并裸露出来；而氧化的中间半导体层及第一半导体层则埋入隔离绝缘层之中。形成第三半导体层于裸露的第二半导体层之上以形成通道层。
根据本揭露内容的另一面向，半导体装置包含鳍式场效晶体管装置。鳍式场效晶体管装置包含鳍片结构及栅极堆叠。鳍片结构沿着第一方向延伸并突出于隔离绝缘层。鳍片结构包含阱层、置于阱层上的氧化层和置于氧化层上的通道层。栅极堆叠包含栅极电极层及栅极介电层，此栅极堆叠覆盖一部分的通道层并沿着垂直于第一方向的第二方向延伸。沿着第二方向的阱层的宽度小于沿着第一方向的阱层的宽度。
附图说明
当读到随附的附图时，从以下详细的叙述可充分了解本发明的各方面。值得注意的是，根据工业上的标准实务，各种特征不是按比例绘制。事实上，为了清楚的讨论，各种特征的尺寸可任意增加或减少。
图1为根据本揭露内容的一实施例，一种半导体场效晶体管装置的示意制造流程图；
图2至图8为根据本揭露内容的一实施例，一种制造半导体场效晶体管装置的示意流程；
其中，符号说明：
S101、S102、S103、S104、S105、S106、S107 步骤
10基板 15第一半导体层
17二氧化硅层 20中间半导体层
25锗化硅氧化层 30第二半导体层
32二氧化硅层 40鳍片结构
42通道层 44阱层
45第三半导体层 50隔离绝缘层
60栅极结构 70栅极介电层
80电极层 100掩模层
102衬垫氧化物层 104氮化硅掩模层
X X方向 Y Y方向
Z Z方向。
具体实施方式
以下的揭露内容提供许多不同的实施例或实例，以实现本发明的不同特征。特定实例的组成及布局叙述如下，以简化本发明。当然这些仅是实例，并非用以限制。举例而言，在叙述中，第一特征形成于第二特征上方或之上时，随之而来可包含实施例，其中第一及第二特征形成以直接接触；且亦可包含实施例，其中额外的特征可形成于第一及第二特征之间，因此第一及第二特征可不直接接触。此外，本发明可在各实例中重复元件编号及/或文字。重复的目的在于简化且明确，但不在其中决定介于所讨论的多种实施例及/或组态的间的相对关系。
此外，空间上的相对用语，例如「在..之下」、「以下」、「下」、「上方」、「上」及其类，在此为了易于叙述可用以描述如图所示的元件或特征对于其他元件或特征的相对关系。除了图示所描绘的面向之外，空间上的相对用语意旨于围绕所使用或操作的装置的不同面向。要不然就是，设备可被导向(旋转90度或于其他面向)，且在此所用的空间上的相对描述符号可据此同样的被解读。此外，「由…所制成」其意思表示「包含…」或「由…所构成」。
图1为根据本揭露内容的一实施例，一种制造半导体场效晶体管装置的示意流程图。此流程图仅绘示完整制造过程的某些相关部分。可于图1所示的步骤进行前、进行期间与进行后提供额外的步骤，且如下所述的一些步骤可由本方法中额外的实施例所取代、删除或变动。步骤/制程的顺序可进行自由交换。
如图2所示，在图1的步骤S101中，半导体材料的堆叠层形成于基板之上。此半导体材料的堆叠层形成于基板10之上，且包含第一半导体层15、中间半导体层20和第二半导体层30。
基板10为，举例来说，P型(p-type)硅基板，具有杂质浓度介于1015ions/cm-3至3×1015ions/cm-3之间的。在其他实施例中，基板10为N型(n-type)硅基板，具有杂质浓度介于1015ions/cm-3至3×1015ions/cm-3之间的。在一些实施例中，基板10为硅基板，具有(100)上表面。
或着，基板10可能包含另一基本半导体(例如：锗)、包含4-4族(IV-IV)元素的化合物半导体(例如：碳化硅和锗化硅)、包含3-5族(III-V)元素的化合物半导体(例如：砷化镓、磷化镓、氮化镓、磷化铟、砷化铟、锑化铟、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP或其任意的组合。在一实施例中，基板10为绝缘体上硅(silicon-on-insulator；SOI)基板中的硅层。当采用绝缘体上硅(SOI)基板时，鳍片结构可能突出于绝缘体上硅基板中的硅层或绝缘体上硅基板中的绝缘层。于后者的情况中，绝缘体上硅(SOI)基板中的硅层则用于形成鳍片结构。可使用非晶形基板(例如：非晶形硅、非晶形碳化硅或绝缘材料(例如：二氧化硅))作为基板10。基板10可能包含各态样的区域，且此些区域适当地掺杂杂质(例如：P形或N形的导体)。
第一半导体层15可能为经过杂质植入的基板的一部份，此离子植入目的是避免穿隧效应。对于N型鳍式场效晶体管来说，掺杂质为二氟化硼(BF2)；而对于P型鳍式场效晶体管来说，掺杂质为磷。掺杂后，第一半导体层15变成鳍式场效晶体管的阱层(well layer)。
在一些实施例中，第一半导体层15可能外延成长于基板10之上。第一半导体层15可能在原位(in-situ)掺杂或经过离子植入法进行掺杂。
中间半导体层20是外延成长于第一半导体层15的表面之上，而第二半导体层30则外延成长于中间半导体层20的表面之上。此外，形成掩模层100于第二半导体层30之上，其包含第一掩模层102及第二掩模层104。
中间半导体层20为，举例来说，锗或Si(1-x)Gex，其中x介于0.1至0.9之间。在此实施例中，Si(1-x)Gex用作中间半导体层20。在本揭露内容中，Si(1-x)Gex可以简单称作锗化硅(SiGe)。在一些实施例中，中间半导体层20的厚度介于10纳米至100纳米间。在某特定实施例中，中间半导体层20的厚度介于10纳米至20纳米之间；而于其他实施例中，中间半导体层20的厚度介于2纳米至10纳米之间。
锗化硅层的外延成长是以锗烷(GeH4)、硅烷(SiH4)和/或二氯硅烷(SiH2Cl2)为反应气体，进行于温度介于约500℃与约700℃之间及压力介于约10托尔至100托尔(约133帕至约1333帕)之间的环境之中。
第二半导体层30为，举例来说，硅或Si(1-y)Gey，其中y小于x。在此实施例中，第二半导体层为硅。在一些实施例中，第二半导体层30的厚度介于约20纳米至200纳米之间。在某些特定的实施例中，第二半导体层30的厚度介于约50纳米至100纳米之间。硅层的外延成长是以硅烷(SiH4)和/或二氯硅烷(SiH2Cl2)为反应气体，进行于的温度介于约500℃与约700℃之间及压力介于约10托尔至100托尔(约133帕至约1333帕)之间的环境之中。
掩模层100可能包含，举例来说，作为第一掩模层的衬垫氧化物(例如：二氧化硅)层102和作为第二掩模层的氮化硅掩模层104。在一些实施例中，衬垫氧化物层102的厚度介于约2纳米至15纳米之间，而氮化硅掩模层104的厚度则介于约10纳米至50纳米之间。
如图3所示，在图1的步骤S102中，图案化具有掩模层的半导体材料的堆叠层以形成沿着X方向延伸的鳍片结构40。
藉由图案化步骤，掩模层100图案化成掩模图案。在一些实施例中，每个图案的宽度介于约5纳米至40纳米之间。在其他实施例中，每个图案的宽度介于约10纳米至30纳米之间。
如图3所示，将掩模图案作为蚀刻时的掩模，藉由干蚀刻法和/或湿蚀刻法以沟渠蚀刻第三半导体层30、中间半导体层20和第一半导体层15，使的图案化成鳍片结构40。在一些实施例中，部分的基板10可能被蚀刻到。
在图3中，两个鳍片结构40彼此相邻。但鳍片结构的数量并非仅限于两个，其数量可能为一个、三个、四个、五个或多个。此外，一个或多个虚拟鳍片结构可能置于邻近鳍片结构40的两侧以提升图案化制程时的图案拟真度。在一些实施例中，鳍片结构40的宽度(Y方向)介于约5纳米至40纳米之间；而在某些特定的实施例中则介于约7纳米至15纳米之间。在一些实施例中，鳍片结构40的高度(Z方向)介于约100纳米至300纳米之间；而在某些特定的实施例中则介于约50纳米至100纳米之间。在一些实施例中，鳍片结构40间的距离介于约5纳米至80纳米之间；而在某些特定的实施例中则介于约7纳米至15纳米之间。然而，在此领域具通常知识者将了解，描述中所提及的尺寸与数值仅为举例，可任意改变使其符合不同尺寸的集成电路。此外，在一些实施例中，鳍片结构40中至少有一个是用于N型鳍式场效晶体管，且至少有一个是用于P型鳍式场效晶体管。
请知悉，在本揭露内容的一实施例中，鳍片结构40的宽度可设定为小于目标通道宽度的值。
在图1的步骤S103中，其是氧化鳍片结构40中的中间半导体层20。在本揭露内容的一实施例中，中间半导体层20为锗化硅，而第一半导体层15和第二半导体层30则为硅。此外，如图4所示，中间半导体层20氧化成锗化硅氧化层25。
由于锗化硅(尤其是锗)氧化得比硅还快，所以锗化硅氧化层25可选择性形成。然后，第一半导体层15的侧壁和第三半导体层30可能会轻微氧化成二氧化硅层17和32。
可在含有氧气的气氛、氧气、氢气或水蒸气的环境下，藉由回火(annealing)或加热(heating)的方式氧化锗化硅层。在此实施例中，使用水蒸气的湿氧化是进行于约一大气压下且温度介于约400℃至800℃之间的环境中，持续时间约1至4小时。在一些实施例中，锗化硅氧化层25的厚度介于约5纳米至25纳米之间；而在其他实施例中则介于约10纳米至20纳米之间。藉由此氧化步骤以完全氧化中间半导体层20(锗化硅)。
在本揭露内容的一些实施例中，可藉由湿蚀刻，选择性去除二氧化硅层17和32及部分的锗化硅氧化层25。湿蚀刻的蚀刻剂可能为稀释的氢氟酸。藉由调整蚀刻参数(例如：蚀刻时间)，可去除形成于第一和第三半导体层侧壁上的二氧化硅层17和32。锗化硅氧化层25也轻微地蚀刻。
如图5所示，在图1的步骤S103中，隔离绝缘层50形成于基板和鳍片结构40之上。隔离绝缘层50包含一层或多层的绝缘材料，例如：二氧化硅、氮氧化硅(silicon oxynitride)或氮化硅。此绝缘材料可藉由低压化学气相沉积(LPCVD)、等离子化气相沉积(plasma-CVD)或流动式化学气相沉积(flowable CVD)方式形成。在流动式化学气相沉积(flowable CVD)方式中，沉积流动式介电材料而非二氧化硅。流动式介电材料，如其名能于沉积时流动，以填满高深宽比的间隙或空间。不同以往，添加各种化学物质于含硅前驱物，使沉积薄膜得以流动。在一些实施例中，添加氮混成键(nitrogen hybrid bond)于前驱物。流动式介电前驱物，特别是流动性二氧化硅前驱物，举例来说，包含硅酸盐(silicate)、硅氧烷(siloxane)、甲基硅酸盐(methyl silsesquioxane，MSQ)、氢硅酸盐(hydrogen methylsilsesquioxane，HSQ)、甲基硅酸盐与氢硅酸盐混合物(MSQ/HSQ)、perhydrosilazan(TCPS)、per-hydro-polysilazane(PSZ)、四乙氧基硅烷(tetraethoxysilane，TEOS)或甲硅烷基胺(silyl-amine)。这些流动性二氧化硅材料是经过多步骤制程形成。在沉积流动性二氧化硅薄膜之后，经过升温并退火，以去除不理想的元素，形成二氧化硅。不理想的元素去除时，流动性薄膜会致密化和收缩。在一些实施例中，会实施多步骤的退火制程。流动性薄膜会经过不仅一次的升温和退火制程。流动性薄膜可掺杂硼或磷。在一些实施例中，隔离绝缘层50可能由单层或多层的玻璃上旋转(SOG)、一氧化硅(SiO)、氮氧化硅(SiON)、氮碳氧化硅(SiOCN)和/或氟硅玻璃(FSG)所形成。
在形成隔离绝缘层50之后，可进行热制程(例如：退火制程)以提升隔离绝缘层50的性质。可在平坦化步骤进行前或进行后，实施此热制程。
如图6所示，在图1的步骤S105中，藉由平坦化制程(例如：化学机械研磨(CMP)法和/或回蚀制程)减少隔离绝缘层50的厚度，以暴露一部份的鳍片结构40。在平坦化制程中，去除掩模图案100及隔离绝缘层50的上部。此外，藉由回蚀制程以减少隔离绝缘层50的厚度。
一部分的鳍片结构，包含鳍片结构40的裸露部分42，成为鳍式场效晶体管的通道；而一部分的鳍片结构则埋于隔离绝缘层中成为鳍式场效晶体管的阱层(well layer)44。回蚀制程可藉由干蚀刻或湿蚀刻的方式进行。藉由调整蚀刻时间，可得到理想的剩余隔离绝缘层50的厚度。
在图6中，锗化硅氧化层25未裸露出隔离绝缘层50，而通道层42的底端则埋于隔离绝缘层50中。然而，在一些实施例中，锗化硅氧化层25及全部的通道层42可能自隔离绝缘层50中裸露出来。
如图7所示，在图1的步骤S106中，形成第三半导体层45于通道层42之上，以调整鳍式场效晶体管的宽度(Y方向)。
如上所述，在中间半导体层20的氧化过程中，第一半导体层和第三半导体层15和30的侧壁也会氧化。为了完全氧化中间半导体层20，第一半导体层和第三半导体层15和30的侧壁上所形成的二氧化硅层的厚度将增加，反过来降低鳍片结构的宽度。尤其是形成通道的鳍片结构上部的宽度将减少。
然而，藉由形成第三半导体层45于通道层42之上，可回复鳍式场效晶体管的通道宽度以得到理想的通道宽度。如图7所示，加上第三半导体层45的鳍式场效晶体管的通道宽度，大致上会大于阱层44的宽度。
第三半导体层45是以外延的方式形成于通道层42之上，如果通道层42为硅，则包含形成于硅之上。在一些实施例中，第三半导体层可能包含硅和锗，且可能也包含额外的材料(例如：磷和/或碳)。于外延成长时，可能适当掺杂掺杂质或不掺杂第三半导体层45。
第三半导体层45可藉由外延成长的方式形成。外延成长是以硅烷(SiH4)和/或二氯硅烷(SiH2Cl2)为反应气体，进行于的温度介于约500℃与约700℃之间及压力介于约10托尔至100托尔(约133帕至约1333帕)之间的环境之中。
在本实施例中，第三半导体层45是以硅制成，而由通道层42和第三半导体层45所组成的鳍式场效晶体管的通道则不包含锗。如前所述，中间半导体层20完全氧化而无锗化硅半导体层残留。因此，外延成长第三半导体层45时，没有来自锗化硅层的锗扩散。在本揭露内容的一些实施例中，藉由能量散布X光谱分析仪(energy dispersive x-rayspectrometry，EDX)的分析，没有侦测到有关锗的讯号于通道层42的底部，表示锗没有扩散至通道层内。
在图1的步骤S107中，栅极结构60形成于鳍片结构40的部分通道层42之上。栅极结构60沿着Y方向延伸且包含栅极介电层70及电极层80。此处虽然形成一栅极结构60于两个鳍片结构之上(如图8所示)，但也可能各自形成两个栅极结构于两个鳍片结构之上。
栅极介电层和电极材料形成于隔离绝缘层50及通道层42之上。而后进行图案化步骤以得到包含栅极电极层80及栅极介电层70的栅极结构。在本实施例中，栅极电极层80为多晶硅。在一些实施例中，藉由包含氮化硅层的硬掩模以进行多晶硅的图案化步骤。栅极介电层可能为二氧化硅，其是藉由化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、电子束蒸镀(e-beam evaporation)或其他合适的制程形成。
在一实施例中，使用栅极后制程技术(gate-last technology)或称栅极置换技术(gate replacement technology)。在栅极后制程技术中，前述步骤形成的栅极电极层80和栅极介电层70是各别为虚拟电极层和虚拟栅极介电层，于制程的末端会消失。
在一些实施例中，栅极介电层70可能包含单层或多层的二氧化硅、氮化硅、氮氧化硅(silicon oxy-nitride)或高介电常数的介电材料。用作高介电常数的介电材料包含金属氧化物，举例来说，包含锂、铍、镁、钙、锶、钪、钇、锆、铪、铝、镧、铈、镨、钕、钐、铕、钆、铽、镝、钬、铒、铥、镱、镏的氧化物和/或其任意的混合。在一些实施例中，栅极介电层70的厚度介于约1纳米至约5纳米之间。在一些实施例中，栅极介电层70可能包含以二氧化硅制成的介面层。在一些实施例中，栅极电极层80可能包含单层或多层结构。
此外，栅极电极层80可能均匀或非均匀掺杂多晶硅。在一些替代的实施例中，栅极电极层80可能包含金属，例如：铝、铜、钨、钛、钽、氮化钛、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钽、镍硅(NiSi)、硅化钴(CoSi)、其他能与基板材料相容的导电材料或其任意的组合。栅极电极层80的电极层可藉由合适的制程形成，例如：原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、电镀或其任意的组合。在一些实施例中，栅极电极层的宽度(X方向)介于约30纳米至约60纳米之间。
众所皆知的，鳍式场效晶体管装置可能进行后续的互补式金氧半场效晶体管(CMOS)制程以形成各态样的特征，例如：侧壁绝缘层、源极/漏极结构、层间绝缘层、接点/通道、内连线金属层、介电层、钝化层等。
与现有技术相比较，在此描述的各态样的实施例或例子提供多项优点。在本揭露内容的一些实施例中，在通道层自隔离绝缘层裸露之后，形成外延通道层以增加鳍式场效晶体管的通道的宽度，因此得到理想的通道宽度。
藉由形成外延通道层以回复通道宽度，能在氧化锗化硅层的过程中，完全将锗化硅层氧化成锗化硅氧化物，而毋须顾及通道宽度的减小。这使得氧化锗化硅层的制程视窗(process window)变得更广。此外，由于能缩小鳍片结构的宽度(蚀刻制程后)，所以完全氧化锗化硅层的时间可以缩短，因此降低热经历(thermal history)。
请知悉，并非所有的优点皆须于此叙述，也没有特别的优点是所有的实施例和例子皆具备的，其他的实施例或例子可能提供不同的优点。
虽然本发明已以实施方式及实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视后附的申请专利范围所界定者为准。体现本发明特征与优点的典型实施方式已在以上的说明中详细叙述。应理解的是本发明能够在不同的实施例上具有各种的变化，其皆不脱离本发明的范围，且其中的说明及附图在本质上是当作说明之用，而非用以限制本发明。

Claims (20)

1.一种制造半导体装置的方法，其特征在于，包含：
形成鳍片结构，其包含第一半导体层、置于所述第一半导体层上的氧化层及置于所述氧化层上的第二半导体层；
形成隔离绝缘层，使得所述鳍片结构中的第二半导体层突出于所述隔离绝缘层并裸露出来，而所述氧化层及所述第一半导体层则埋于所述隔离绝缘层之中；以及
形成第三半导体层于所述裸露的第二半导体层之上以形成半导体装置的通道。
2.如权利要求1所述的方法，其中所述氧化层包含锗硅氧化物。
3.如权利要求1所述的方法，其中所述第二半导体层包含硅或硅化合物。
4.如权利要求3所述的方法，其中所述第三半导体层包含硅或硅化合物，且是以外延的方式形成于所述裸露的第二半导体层之上。
5.如权利要求1所述的方法，其中所述第一半导体层的宽度小于所述通道的宽度。
6.一种制造半导体装置的方法，其特征在于，包含：
形成堆叠半导体层，包含第一半导体层、形成于所述第一半导体层上的中间半导体层及形成于所述中间半导体层上的第二半导体层；
藉由图案化所述第一半导体层、所述中间半导体层及所述第二半导体层，以形成鳍片结构；
氧化所述鳍片结构中的中间半导体层；
形成隔离绝缘层，使得所述鳍片结构中的第二半导体层突出于所述隔离绝缘层并裸露出来，而所述氧化的中间半导体层及所述第一半导体层则埋于所述隔离绝缘层之中；以及
形成第三半导体层于所述裸露的第二半导体层之上以形成半导体装置的通道。
7.如权利要求6所述的方法，其中所述中间半导体层包含锗化硅。
8.如权利要求7所述的方法，其中在氧化所述鳍片结构中的中间半导体层时，所述锗化硅完全氧化。
9.如权利要求6所述的方法，其中所述第二半导体层是以硅或硅化合物制成。
10.如权利要求9所述的方法，其中所述第三半导体层包含硅或硅化合物，且是以外延的方式形成于所述裸露的第二半导体层之上。
11.如权利要求9所述的方法，其中在氧化所述鳍片结构中的中间半导体层时，所述第一半导体层及所述第二半导体层的侧壁氧化形成二氧化硅。
12.如权利要求11所述的方法，更包含去除形成在所述第一半导体层及所述第二半导体层侧壁上的二氧化硅。
13.如权利要求6所述的方法，其中所述鳍片结构中的第一半导体层的宽度小于所述通道的宽度。
14.如权利要求6所述的方法，其中形成所述隔离绝缘层，包含：
形成绝缘材料于所述鳍片结构之上，使得所述鳍片结构完全埋于所述绝缘材料之中；以及
去除部分的所述绝缘材料，使得所述鳍片结构的第二半导体层突出于所述隔离绝缘层。
15.如权利要求6所述的方法，其中在氧化所述中间半导体层时，包含热氧化法。
16.如权利要求6所述的方法，更包含在所述通道之上形成一栅极结构。
17.一种半导体装置，其特征在于，包含：
鳍式场效晶体管装置，包含：
鳍片结构，沿着第一方向延伸并突出于隔离绝缘层，所述鳍片结构包含阱层、置于所述阱层上的氧化层及置于所述氧化层上的通道层；以及
栅极堆叠，包含栅极电极层及栅极介电层，所述栅极堆叠覆盖一部分的所述通道层，并沿着垂直于第一方向的第二方向延伸；
其中，位于所述第二方向的阱层的宽度小于位于所述第一方向的通道层的宽度。
18.如权利要求17所述的半导体装置，其中所述氧化层包含锗硅氧化物。
19.如权利要求18所述的半导体装置，其中所述氧化层不包含锗化硅半导体。
20.如权利要求17所述的半导体装置，其中所述通道层不包含锗。
CN201510793708.1A 2015-07-07 2015-11-18 半导体装置及其制造方法 Active CN106340456B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/793,632 2015-07-07
US14/793,632 US9425313B1 (en) 2015-07-07 2015-07-07 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN106340456A CN106340456A (zh) 2017-01-18
CN106340456B true CN106340456B (zh) 2019-07-16

Family

ID=56683645

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510793708.1A Active CN106340456B (zh) 2015-07-07 2015-11-18 半导体装置及其制造方法

Country Status (4)

Country Link
US (2) US9425313B1 (zh)
KR (1) KR101799647B1 (zh)
CN (1) CN106340456B (zh)
TW (1) TWI564970B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10164096B2 (en) * 2015-08-21 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10720508B2 (en) * 2015-09-25 2020-07-21 Intel Corporation Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping
CN106611787A (zh) * 2015-10-26 2017-05-03 联华电子股份有限公司 半导体结构及其制作方法
US10020186B2 (en) * 2016-07-29 2018-07-10 Applied Materials, Inc. Silicon germanium selective oxidation process
CN108987476B (zh) * 2017-06-01 2021-05-11 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
WO2019139626A1 (en) 2018-01-12 2019-07-18 Intel Corporation Non-planar semiconductor device including a replacement channel structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064943B1 (en) * 2014-09-30 2015-06-23 International Business Machines Corporation Gate-all-around field effect transistor structures and methods
CN104752508A (zh) * 2013-12-27 2015-07-01 三星电子株式会社 包括具有多倾角的沟槽壁的半导体器件

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725918A (en) 1986-08-22 1988-02-16 General Patent Counsel/Amp Incorporated Protective insert for chip carriers
US5159535A (en) 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US5170931A (en) 1987-03-11 1992-12-15 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US5201451A (en) 1987-03-11 1993-04-13 International Business Machines Corp. Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
JP3518091B2 (ja) 1995-09-25 2004-04-12 株式会社エンプラス Ｉｃソケット
JP2908747B2 (ja) 1996-01-10 1999-06-21 三菱電機株式会社 Ｉｃソケット
US5920200A (en) 1997-07-22 1999-07-06 Hewlett-Packard Company Apparatus and method for precise alignment of a ceramic module to a test apparatus
JP3694166B2 (ja) 1998-02-27 2005-09-14 株式会社エンプラス Ｉｃソケット
JP3714656B2 (ja) 1998-02-27 2005-11-09 株式会社エンプラス Ｉｃソケット
US6057700A (en) 1998-05-06 2000-05-02 Lucent Technologies, Inc. Pressure controlled alignment fixture
US6369595B1 (en) 1999-01-21 2002-04-09 Micron Technology, Inc. CSP BGA test socket with insert and method
US7867763B2 (en) 2004-01-25 2011-01-11 Fluidigm Corporation Integrated chip carriers with thermocycler interfaces and methods of using the same
US7242088B2 (en) 2000-12-29 2007-07-10 Intel Corporation IC package pressure release apparatus and method
TWI221529B (en) 2001-12-28 2004-10-01 Nhk Spring Co Ltd Socket for inspection
CN100365422C (zh) 2002-03-06 2008-01-30 株式会社爱德万测试 插入体主体、插入体和电子部件处理装置
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7425740B2 (en) 2005-10-07 2008-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for a 1T-RAM bit cell and macro
US7473593B2 (en) * 2006-01-11 2009-01-06 International Business Machines Corporation Semiconductor transistors with expanded top portions of gates
JP5095964B2 (ja) 2006-07-03 2012-12-12 スリーエム イノベイティブ プロパティズ カンパニー ソケット用アタッチメント及びそれを有する半導体デバイス試験装置
JP2008070146A (ja) 2006-09-12 2008-03-27 Yokowo Co Ltd 検査用ソケット
US7544994B2 (en) * 2006-11-06 2009-06-09 International Business Machines Corporation Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure
EP2772768B1 (en) 2007-04-05 2019-06-26 AEHR Test Systems Electronics tester with a signal distribution board and a wafer chuck having different coefficients of thermal expansion
US8496113B2 (en) 2007-04-13 2013-07-30 Techwing Co., Ltd. Insert for carrier board of test handler
JP4539685B2 (ja) 2007-06-22 2010-09-08 セイコーエプソン株式会社 部品搬送装置及びｉｃハンドラ
KR101341566B1 (ko) 2007-07-10 2013-12-16 삼성전자주식회사 소켓, 검사 장치, 그리고 적층형 반도체 소자 제조 방법
US20090026199A1 (en) 2007-07-27 2009-01-29 Jeor Bret De Pressure vacuum release hermetic valve for rigid container packages
TW200941002A (en) 2008-03-28 2009-10-01 King Yuan Electronics Co Ltd A socket, test device and test method for testing electronic element packages with leads
US8048723B2 (en) 2008-12-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs having dielectric punch-through stoppers
US8776734B1 (en) 2008-05-19 2014-07-15 Innovative Environmental Solutions, Llc Remedial system: a pollution control device for utilizing and abating volatile organic compounds
TWM354211U (en) 2008-09-08 2009-04-01 Hon Hai Prec Ind Co Ltd Electrical connector
US8053299B2 (en) 2009-04-17 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabrication of a FinFET element
US8415718B2 (en) 2009-10-30 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming epi film in substrate trench
US8395195B2 (en) 2010-02-09 2013-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Bottom-notched SiGe FinFET formation using condensation
US8575653B2 (en) * 2010-09-24 2013-11-05 Intel Corporation Non-planar quantum well device having interfacial layer and method of forming same
KR101768992B1 (ko) 2010-12-30 2017-08-17 삼성전자주식회사 프로브 카드 및 이를 이용한 반도체 장치의 검사 방법
US8797056B2 (en) 2011-03-22 2014-08-05 Advantest (Singapore) Pte Ltd System and method for electronic testing of partially processed devices
US8618556B2 (en) 2011-06-30 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design and method of fabricating same
US8609518B2 (en) 2011-07-22 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Re-growing source/drain regions from un-relaxed silicon layer
US8710859B2 (en) 2011-09-23 2014-04-29 Powertech Technology Inc. Method for testing multi-chip stacked packages
JP2013079860A (ja) 2011-10-04 2013-05-02 Advantest Corp ソケット及び電子部品試験装置
US8815712B2 (en) 2011-12-28 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial re-growth of semiconductor region
JP2013145132A (ja) 2012-01-13 2013-07-25 Advantest Corp ハンドラ装置、試験方法
US8742509B2 (en) 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US8703508B2 (en) 2012-08-14 2014-04-22 Powertech Technology Inc. Method for wafer-level testing diced multi-chip stacked packages
US8633516B1 (en) 2012-09-28 2014-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain stack stressor for semiconductor device
US8497177B1 (en) 2012-10-04 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9093530B2 (en) 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US9202917B2 (en) * 2013-07-29 2015-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Buried SiGe oxide FinFET scheme for device enhancement
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US8963258B2 (en) 2013-03-13 2015-02-24 Taiwan Semiconductor Manufacturing Company FinFET with bottom SiGe layer in source/drain
US9341671B2 (en) 2013-03-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Testing holders for chip unit and die package
US8796666B1 (en) 2013-04-26 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with strain buffer layer and methods of forming the same
US9159833B2 (en) * 2013-11-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104752508A (zh) * 2013-12-27 2015-07-01 三星电子株式会社 包括具有多倾角的沟槽壁的半导体器件
US9064943B1 (en) * 2014-09-30 2015-06-23 International Business Machines Corporation Gate-all-around field effect transistor structures and methods

Also Published As

Publication number Publication date
US20170012128A1 (en) 2017-01-12
US9691903B2 (en) 2017-06-27
TW201703156A (zh) 2017-01-16
CN106340456A (zh) 2017-01-18
KR101799647B1 (ko) 2017-11-20
TWI564970B (zh) 2017-01-01
KR20170006241A (ko) 2017-01-17
US9425313B1 (en) 2016-08-23

Similar Documents

Publication Publication Date Title
US10644154B2 (en) Semiconductor device and manufacturing method thereof
US11569387B2 (en) Semiconductor device including fin structures and manufacturing method thereof
CN106340456B (zh) 半导体装置及其制造方法
US11489074B2 (en) Semiconductor device and manufacturing method thereof
US11049970B2 (en) Semiconductor device and manufacturing method thereof
CN103107196B (zh) 鳍式场效应晶体管及其制造方法
TWI552347B (zh) 使用經摻雜的凸起源極和汲極區的源極和汲極摻雜
CN108122846A (zh) 包括鳍式场效应晶体管的半导体器件及其形成方法
CN105990440B (zh) 半导体器件结构的结构和形成方法
CN106024767B (zh) 半导体器件结构的结构和形成方法
JP2021507533A (ja) 垂直型トランジスタのための自己整合された底部スペーサを形成する方法及び半導体デバイス
CN106409679A (zh) 具有掺杂的隔离绝缘层的鳍式场效应晶体管
US9530889B2 (en) Semiconductor device and manufacturing method thereof
US9865709B2 (en) Selectively deposited spacer film for metal gate sidewall protection
CN106992154A (zh) 半导体器件及其制造方法
CN109841569A (zh) 具有增强的栅极接触件和阈值电压的栅极结构及其方法
TWI453804B (zh) 形成半導體元件的金屬閘極堆疊的方法
CN113889467A (zh) 具有横向尺寸不同的子鳍延伸区的带鳍ic结构
TWI521709B (zh) 半導體結構及積體電路之製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant