CN106298550A - 用于制作带有侧壁凹陷的半导体器件的方法及相关器件 - Google Patents
用于制作带有侧壁凹陷的半导体器件的方法及相关器件 Download PDFInfo
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- CN106298550A CN106298550A CN201510992712.0A CN201510992712A CN106298550A CN 106298550 A CN106298550 A CN 106298550A CN 201510992712 A CN201510992712 A CN 201510992712A CN 106298550 A CN106298550 A CN 106298550A
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- Prior art keywords
- lead frame
- contact pin
- solder
- anchoring
- contact
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 48
- 229910000679 solder Inorganic materials 0.000 claims abstract description 42
- 238000004873 anchoring Methods 0.000 claims abstract description 36
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000002195 soluble material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000004899 motility Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229920001059 synthetic polymer Polymers 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本申请涉及用于制作带有侧壁凹陷的半导体器件的方法及相关器件。该方法可以包括提供具有凹陷的引线框、在该引线框的该凹陷内形成牺牲材料以及在该引线框上安装IC。该方法可以包括:包封该IC和该引线框、去除该引线框的多个部分以限定用于该IC的多个引线框触点以及去除该牺牲材料以针对每个引线框触点来限定焊料锚固接片,该焊料锚固接片在下部区域处向外延伸并且在该焊料锚固接片与该包封材料的相对部分之间限定了侧壁凹陷。
Description
技术领域
本披露涉及半导体加工领域,并且更具体地涉及一种用于制作半导体器件的方法。
背景技术
在具有集成电路(IC)的电子器件中,IC通常安装到电路板上。为了电耦接在电路板和IC之间的连接,通常对IC进行“封装”。IC封装通常提供用于物理地保护IC的小型封套并且提供用于耦接至电路板的接触焊盘。在一些应用中,封装的IC可以经由键合接线或焊料凸块而耦接到电路板。
一种IC封装的方案包括四方扁平无引线(QFN)封装体。QFN封装体可以提供一些优点,诸如减小引线电感、紧密芯片尺寸占用面积、薄剖面和低重量。并且,QFN封装体通常包括周边I/O焊盘以易于电路板迹线布线,并且暴露的铜裸片焊盘技术提供了增强的热性能和电性能。QFN封装体可以很好地适用于其中尺寸、重量以及热性能和电性能重要的应用。
首先参照图1,现在描述典型的QFN封装的电子器件100。电子器件100包括IC裸片焊盘104、在该IC裸片焊盘上的IC105以及在该IC裸片焊盘与该IC之间的粘合层106。电子器件100包括多个引线框触点103a-103b以及使该多个引线框触点与IC 105相耦接的多条键合接线102a-102b。电子器件100包括围绕该多条键合接线102a-102b和IC 105的包封材料101。
发明内容
通常而言,一种方法用于制作半导体器件。该方法可以包括:提供在其中具有凹陷的引线框、在该引线框的凹陷内形成牺牲材料以及在该引线框上安装IC。该方法还可以包括:包封该IC和该引线框、去除该引线框的多个部分以限定用于该IC的多个引线框触点以及去除该牺牲材料以针对每个引线框触点限定焊料锚固接片,该焊料锚固接片在其下部区域向外延伸并且在该焊料锚固接片与该包封材料的相对部分之间限定侧壁凹陷。
更具体地,去除该引线框的多个部分可以包括通过在该凹陷处划切该引线框来使该IC单片化。例如,该牺牲材料可以包括可热分解的材料、水溶性材料和光敏材料中的至少一种。该方法可以进一步包括形成多条键合接线,每条键合接线使对应的引线框触点与该IC相耦接。
在一些实施例中,该方法进一步包括在该焊料锚固接片上形成镀层(例如,锡)。每个引线框触点可以包括从其上部区域向内延伸的模具锚固接片。并且,包封可以包括形成包封材料以围绕该模具锚固接片。该引线框可以限定IC裸片焊盘,该IC裸片焊盘具有从其上部区域向外延伸的多个模具锚固接片。
另一方面涉及一种半导体器件。该半导体器件可以包括:至少一个IC;与该至少一个IC对准的IC裸片焊盘;以及与该IC裸片焊盘相邻的多个引线框触点,每个引线框触点具有在其下部区域处向外延伸的焊料锚固接片。该半导体器件还可以包括:多条键合接线,每条键合接线使对应的引线框触点与该至少一个IC相耦接。该半导体器件还可以包括:围绕该至少一个IC和该多条键合接线的包封材料,每个引线框触点在该焊料锚固接片与该包封材料之间限定侧壁凹陷。此外,该半导体器件可以进一步包括在其中具有多个触点的电路板层以及多个焊料本体,这些焊料本体围绕这些焊料锚固接片并且将该多个触点与该多个引线框触点相耦接。
附图说明
图1是根据现有技术的半导体器件的示意性横截面视图。
图2是根据本披露的半导体器件的示意性横截面视图。
图3A和图3B是来自图2的半导体器件的引线框触点的示意性透视图,分别示出了不带有和带有包封材料的情况。
图4是流程图,展示了根据本披露的一种用于制作半导体器件的方法。
图5A是在根据本披露的用于制作半导体器件的方法中的步骤的示意性俯视图。
图5B是来自图5A沿着线5B-5B的在用于制作半导体器件的方法中的步骤的示意性横截面视图。
图6至图9是根据本披露沿着线5B-5B的用于制作半导体器件的步骤的示意性横截面视图。
具体实施方式
现在将在下文中参照附图更全面描述本披露,其中附图示出了本发明的若干实施例。然而本披露可以以许多不同的形式来实施,并且不应当被解释为限于在此所陈述的实施例。相反,提供这些实施例以使得本披露将是全面和完整的,并且将向本领域技术人员完全传达本披露的范围。贯穿全文相同的附图标记是指相同的元件。
现在参照图2至图3B,描述了根据本披露的半导体器件10。半导体器件10说明性地包括IC 12、与该IC对准的IC裸片焊盘(例如,铜、铝)24、在该IC与该IC裸片焊盘之间的粘合层23以及与该IC裸片焊盘相邻的多个引线框触点(例如,铜、铝)14a-14b。IC裸片焊盘24说明性地包括从该IC裸片焊盘的上部区域向外延伸的多个模具锚固接片25a-25b。
每个引线框触点14a-14b说明性地包括在其下部区域向外延伸的焊料锚固接片15a-15b。并且,每个引线框触点14a-14b说明性地包括从该引线框触点的上部区域向内延伸的模具锚固接片16a-16b。
半导体器件10说明性地包括多条键合接线(例如,铜、铝、金、银)13a-13b以及围绕该IC和该多条键合接线的包封材料11,每条键合接线使对应的引线框触点14a-14b与IC 12相耦接。每个引线框触点14a-14b在焊料锚固接片15a-15b与包封材料11之间限定侧壁凹陷17a-17b。
半导体器件10说明性地包括电路板层19以及将IC裸片焊盘24耦接至该电路板层的附加焊料材料层22。电路板层19说明性地包括电介质材料衬底20以及由该电介质材料衬底承载的多个触点(例如,铜、铝)21a-21b。半导体器件10说明性地包括多个焊料本体(例如,锡、铅)18a-18b,这些焊料本体围绕焊料锚固接片15a-15b并且将该多个触点21a-21b与该多个引线框触点14a-14b相耦接。在一些实施例中,这些焊料锚固接片15a-15b各自包括在一个或多个表面上的镀层28(例如,锡)。镀层28增强了与该多个焊料本体18a-18b的物理附接。
在所展示的实施例中,该多个焊料本体18a-18b完全填充该多个引线框触点14a-14b的那些侧壁凹陷17a-17b。在其他实施例中,情况不是这样的,并且侧壁凹陷17a-17b的一部分将会剩余,即,在该多个焊料本体18a-18b的上表面与包封材料11之间存在间隙。有利的是,在这些其他实施例中,引线框触点14a-14b具有增加的灵活性/柔韧性,这减少了半导体器件10上的应力并且提高了板级可靠性。
现另外参照图4至图9,现在参考流程图30描述一种用于制作半导体器件10的方法(块31)。该方法说明性地包括:提供在其中具有凹陷29的引线框26、在该引线框的该凹陷内形成牺牲材料27(块33)以及在该引线框上安装IC 12(块35)。例如,牺牲材料27可以包括可热分解的材料、聚合物、水溶性材料(水溶性合成聚合物)或光敏材料。应认识到,载体带可以提供用于在此所描述的方法的基底。
该方法说明性地包括:包封IC 12和引线框26(框37)。并且,包封包括:形成包封材料11以围绕引线框26的模具锚固接片16a-16b。
该方法说明性地包括形成多条键合接线13a-13b,每条键合接线使对应的引线框触点14a-14b与IC 12相耦接。该方法说明性地包括去除引线框26的多个部分以针对IC 12限定多个引线框触点14a-14b(块39)。更具体地,去除引线框26的多个部分说明性地包括通过在凹陷29处划切该引线框来使IC 12单片化(例如,使用划切刀片)。
该方法说明性地包括:去除牺牲材料27以针对每个引线框触点14a-14b限定焊料锚固接片15a-15b(框41、43),该焊料锚固接片在其下部区域处向外延伸并且在该焊料锚固接片与包封材料11的相对部分之间限定侧壁凹陷17a-17b。
由于引线框触点14a-14b的一些表面在切割步骤之后不是可湿的,可以用后镀步骤来使在切割期间所创建的侧表面或切开的引线表面是可湿的。相应地,在一些实施例中,该方法进一步包括在焊料锚固接片15a-15b上形成镀层28(例如,锡)。
在典型的电子器件(如在图1中所描绘的电子器件)中,QFN封装体可能具有一些缺点。具体地,随着引线尺寸变小,在封装体组装期间的问题包括在使用薄型引线框带时的带处理损坏以及在键合接线的形成期间的引线框不稳定性(即,引线反弹)。问题还可能包括在封装体表面安装到电路板上的期间的不充分的焊料锚固。
有利的是,以上所讨论的用于制作半导体器件10的方法使用包括可热分解的聚合物的牺牲材料27,该可热分解的聚合物将在封装体组装期间(即,在图7中所示出的包封之前的步骤)增加引线框26的刚度。这可以减小带处理损坏并且还增加在形成键合接线13a-13b期间的稳定性。并且,一旦形成了侧壁凹陷17a-17b,可以改善焊料锚固性能。
并且,半导体器件10可以使用现有的锯齿型QFN制造工艺/设备,并且不需要获得冲压型设备,从而降低成本和制造复杂性。由于更多的引线框触点14a-14b侧壁是焊料可湿的,对电路板层19的机械附着比在典型的器件中要强。如上所述,半导体器件10可以提供改进的板级可靠性。具体地,仿真已经示出在最坏情况场景下该多个焊料本体18a-18b的规范化焊料寿命的41%的增加(优于并超过图1中所示出的典型的电子器件的性能)。
得益于在前述说明书和相关联附图中呈现的教导,本领域技术人员将想到本披露的许多修改和其他实施例。因此,应该理解的是,本发明实施例并不限于所披露的特定实施例,并且修改和实施例旨在包括于所附权利要求书的范围内。
Claims (23)
1.一种用于制作半导体器件的方法,所述方法包括:
提供在其中具有凹陷的引线框;
在所述引线框的所述凹陷内形成牺牲材料;
在所述引线框上安装集成电路(IC);
对所述IC和所述引线框进行包封;
去除所述引线框的多个部分以限定用于所述IC的多个引线框触点;以及
去除所述牺牲材料以针对每个引线框触点来限定焊料锚固接片,所述焊料锚固接片在其下部区域处向外延伸并且在所述焊料锚固接片与所述包封材料的相对部分之间限定了侧壁凹陷。
2.如权利要求1所述的方法,其中,去除所述引线框的多个部分包括通过在所述凹陷处划切所述引线框来使所述IC单片化。
3.如权利要求1所述的方法,其中,所述牺牲材料包括可热分解的材料、水溶性材料和光敏材料中的至少一种。
4.如权利要求1所述的方法,其中,所述牺牲材料包括聚合物。
5.如权利要求1所述的方法,进一步包括形成多条键合接线,每条键合接线将对应的引线框触点与所述IC相耦接。
6.如权利要求1所述的方法,进一步包括在所述焊料锚固接片上形成镀层。
7.如权利要求1所述的方法,其中,每个引线框触点包括从其上部区域向内延伸的模具锚固接片。
8.如权利要求7所述的方法,其中,包封包括形成所述包封材料来围绕所述模具锚固接片。
9.如权利要求1所述的方法,其中,所述引线框限定IC裸片焊盘,所述IC裸片焊盘具有从其上部区域向外延伸的多个模具锚固接片。
10.一种用于制作半导体器件的方法,所述方法包括:
提供在其中具有凹陷的引线框;
在所述引线框的所述凹陷内形成可热分解的牺牲材料;
在所述引线框上安装集成电路(IC);
对所述IC和所述引线框进行包封;
去除所述引线框的多个部分以限定用于所述IC的多个引线框触点,每个引线框触点包括从其上部区域向内延伸的模具锚固接片;以及
去除所述可热分解的牺牲材料以针对每个引线框触点来限定焊料锚固接片,所述焊料锚固接片在其下部区域处向外延伸并且在所述焊料锚固接片与所述包封材料的相对部分之间限定侧壁凹陷。
11.如权利要求10所述的方法,其中,去除所述引线框的多个部分包括通过在所述凹陷处划切所述引线框来使所述IC单片化。
12.如权利要求10所述的方法,其中,所述可热分解的牺牲材料包括聚合物。
13.如权利要求10所述的方法,进一步包括形成多条键合接线,每条键合接线将对应的引线框触点与所述IC相耦接。
14.如权利要求10所述的方法,进一步包括在所述焊料锚固接片上形成镀层。
15.如权利要求10所述的方法,其中,包封包括形成所述包封材料来围绕所述模具锚固接片。
16.如权利要求10所述的方法,其中,所述引线框限定了IC裸片焊盘,所述IC裸片焊盘具有从其上部区域向外延伸的多个模具锚固接片。
17.一种半导体器件,包括:
至少一个集成电路(IC);
与所述至少一个IC对准的IC裸片焊盘;
与所述IC裸片焊盘相邻的多个引线框触点,每个引线框触点具有在其下部区域处向外延伸的焊料锚固接片;
多条键合接线,每条键合接线将对应的引线框触点与所述至少一个IC相耦接;以及
围绕所述至少一个IC和所述多条键合接线的包封材料,每个引线框触点在所述焊料锚固接片与所述包封材料之间限定了侧壁凹陷。
18.如权利要求17所述的半导体器件,其中,每个引线框触点包括从其上部区域向内延伸的模具锚固接片。
19.如权利要求18所述的半导体器件,其中,所述包封材料围绕所述模具锚固接片。
20.如权利要求17所述的半导体器件,进一步包括在其中具有多个触点的电路板层以及多个焊料本体,所述焊料本体围绕所述焊料锚固接片并且将所述多个触点与所述多个引线框触点相耦接。
21.如权利要求17所述的半导体器件,其中,所述IC裸片焊盘包括从其上部区域向外延伸的多个模具锚固接片。
22.如权利要求17所述的半导体器件,其中,每个引线框触点包括在所述焊料锚固接片上的镀层。
23.如权利要求22所述的半导体器件,其中,所述镀层包括锡镀层。
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US20160379916A1 (en) | 2016-12-29 |
CN205376495U (zh) | 2016-07-06 |
CN110010489B (zh) | 2023-04-28 |
CN110010489A (zh) | 2019-07-12 |
US20180130767A1 (en) | 2018-05-10 |
CN106298550B (zh) | 2019-01-15 |
US10943885B2 (en) | 2021-03-09 |
US10008472B2 (en) | 2018-06-26 |
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