CN110034078A - 用于半导体器件的封装内嵌结构和制造方法 - Google Patents

用于半导体器件的封装内嵌结构和制造方法 Download PDF

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Publication number
CN110034078A
CN110034078A CN201811473190.3A CN201811473190A CN110034078A CN 110034078 A CN110034078 A CN 110034078A CN 201811473190 A CN201811473190 A CN 201811473190A CN 110034078 A CN110034078 A CN 110034078A
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Prior art keywords
lead frame
frame assembly
lead
semiconductor packages
semiconductor
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CN201811473190.3A
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H·T·王
S·H·杨
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L2225/06503—Stacked arrangements of devices
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Abstract

公开了一种半导体封装，其包括堆叠在第一引线框架组件上方的第二引线框架组件，每个引线框架组件包括管芯焊盘、多个引线以及附接到管芯焊盘并与引线电连接的半导体管芯。间隔体将引线框架组件彼此分开。单个模塑化合物嵌入了第一引线框架组件的部分、第二引线框架组件的部分和间隔体。两个引线框架组件的引线的一部分未被模塑化合物覆盖，以形成半导体封装的端子。两个管芯焊盘的一侧未被模塑化合物覆盖。

Description

用于半导体器件的封装内嵌结构和制造方法
技术领域
本申请涉及半导体器件封装，并且特别涉及用于封装半导体器件的堆叠组件。
背景技术
堆叠是使多个半导体管芯(芯片)或多个半导体封装堆叠在彼此上以减小总体封装占用区域和尺寸的技术。在叠层芯片堆叠技术的情况下，两个半导体管芯以堆叠布置利用通往管芯的接合线连接而彼此附接。然后对具有引线接合连接的堆叠芯片布置进行模塑以形成最终封装。然而，利用叠层芯片堆叠方法，两个管芯都被模塑化合物完全包封，这限制了最终解决方案的热性能。而且，需要专用的引线接合设计规则来形成到堆叠管芯布置的接合线连接。在叠层封装堆叠技术的情况下，两个完全完成的半导体封装堆叠在彼此上。亦即，每个半导体封装在堆叠之前已经被模塑、修整并形成。然后将完成的封装以堆叠布置彼此粘合。然而，利用叠层封装堆叠方法，两个封装都被完全模塑，并且管芯完全嵌入在相应的模塑化合物内，这再次限制了最终解决方案的热性能。
因此，需要用于封装半导体器件的改进的堆叠组件。
发明内容
根据半导体封装的实施例，半导体封装包括第一引线框架组件和堆叠在第一引线框架组件上方的第二引线框架组件。第一引线框架组件包括第一管芯焊盘、第一多个引线、以及附接到第一管芯焊盘并电连接到第一多个引线的第一半导体管芯。第二引线框架组件包括第二管芯焊盘、第二多个引线、以及附接到第二管芯焊盘并电连接到第二多个引线的第二半导体管芯。间隔体将第一和第二引线框架组件彼此分开。单个模塑化合物嵌入了第一引线框架组件的部分、第二引线框架组件的部分和间隔体。第一多个引线的一部分和第二多个引线的一部分未被模塑化合物覆盖，以形成半导体封装的端子。第一管芯焊盘的背离第一半导体管芯的一侧和第二管芯焊盘的背离第二半导体管芯的一侧未被模塑化合物覆盖。
根据制造半导体封装的方法的实施例，所述方法包括：提供多个第一引线框架组件，每个第一引线框架组件包括第一管芯焊盘、第一多个引线、以及附接到第一管芯焊盘并电连接到第一多个引线的第一半导体管芯；在所述第一引线框架组件中的每者上方堆叠第二引线框架组件，每个第二引线框架组件包括第二管芯焊盘、第二多个引线、以及附接到第二管芯焊盘并电连接到第二多个引线的第二半导体管芯；在第一引线框架组件和第二引线框架组件之间提供间隔体；将每个第一引线框架组件的部分、每个第二引线框架组件的部分和每个间隔体嵌入单个模塑化合物中，以使得第一多个引线中的每个的一部分和第二多个引线中的每个的一部分未被模塑化合物覆盖，以形成相应半导体封装的端子，并且使得每个第一管芯焊盘的背离相邻第一半导体管芯的一侧和每个第二管芯焊盘的背离相邻第二半导体管芯的一侧未被模塑化合物覆盖；以及将相应的半导体封装单一化成为个体封装。
在阅读以下具体实施方式并查看附图时，本领域的技术人员将认识到额外的特征和优点。
附图说明
附图的要素未必相对于彼此成比例。类似附图标记指示对应的类似部分。可以组合各种所示实施例的特征，除非它们彼此排斥。在附图中描绘并且在下面的描述中详述了实施例。
图1A示出了具有封装内嵌结构的模塑半导体封装的实施例的截面图。
图1B示出了模塑半导体封装的底侧处的引线框架占用区域的俯视图。
图2到图8和图13到图16示出了具有封装内嵌结构的模塑半导体封装的额外实施例的相应截面图。
图9A到图9D、图10A到图10C和图11A到图11E示出了制造模塑半导体封装的方法的实施例。
图12A和图12B示出了在制造模塑半导体封装时采用的替代方法。
具体实施方式
本文描述的实施例提供了封装内嵌结构，其利用了叠层芯片和叠层封装堆叠技术的益处。通过将两个引线框架组件堆叠在彼此上来实现封装内嵌结构，每个引线框架组件具有管芯焊盘、引线、以及附接到管芯焊盘并电连接到引线的至少一个半导体管芯。间隔体将引线框架组件彼此分开以防止在堆叠的引线框架组件之间的接合线短路。然后经由常见模塑工艺将间隔体和引线框架组件的部分嵌入到单个模塑化合物中。引线框架组件的管芯焊盘在最终封装的相对侧未被模塑化合物覆盖，以提供双侧散热。除了改善的热管理，封装内嵌结构提供了更高的部件密度，不需要为芯片到封装互连(管芯附接和引线接合)改变设计规则，降低了与3D半导体封装相关联的复杂度，将两种典型的IC封装结束工艺(如模塑、去毛边、引线镀覆等)组合成具有较少材料用量的单一工艺，利用消除了引线接合期间的引线弹跳的载体，并且在制造过程期间实现了能够重复使用的封装级模塑。
图1A示出了具有封装内嵌结构的模塑半导体封装的实施例的截面图，并且图1B示出了封装的底侧处的引线框架占用区域的俯视图。
模塑半导体封装包括第一引线框架组件100和堆叠在第一引线框架组件100上方的第二引线框架组件102。每个引线框架组件100、102包括用于附接至少一个半导体管芯108、110的管芯焊盘104、106，并且包括提供用于与相应管芯108、110的外部电连接的装置的引线112、114。每个管芯108、110可以例如通过引线接合或带式自动接合通过导线116、118连接到相应的引线112、114。半导体管芯108、110通过标准管芯附接材料被附接到相应的管芯焊盘104、106，并且引线接合连接116、118形成在管芯108、110和相应的引线112、114之间以形成引线框架组件100、102。
在封装被模塑之前，将第二引线框架组件102堆叠在第一引线框架组件100上方。而且，提供间隔体120以用于将引线框架组件100、102彼此分开。在图1A和图1B中，第二引线框架组件102的半导体管芯110设置在第一引线框架组件100的半导体管芯108之上并与其竖直对齐。根据该实施例，间隔体120将上半导体管芯110与下半导体管芯108分开。在管芯108、110被设置成一个在另一个上方但在竖直上未对齐、或者一个管芯未设置在另一个管芯之上(即，在竖直方向上不与另一个管芯重叠)的情况下，仍提供间隔体120作为结构支撑以便于管芯堆叠。通常，在模塑工艺之前提供间隔体120作为结构支撑以实现管芯堆叠，并确保堆叠的引线框架组件100、102的接合线连接116、118之间的足够的电隔离。通过这种方式，可以执行后续的模塑工艺以用于嵌入第一引线框架组件100的部分、第二引线框架组件102的部分和间隔体120。
由于上述原因，间隔体120是电绝缘的。优选但并非必要地，间隔体120是良好的热导体。间隔体材料的一些示例为具有导热且电绝缘的填料的粘合剂或聚合物珠、膜或膏。这些仅是示例，并且不应被视为限制。
在第二引线框架组件102堆叠在第一引线框架组件100上方并且提供间隔体120以将引线框架组件100、102彼此分开的情况下，该布置经受常见模塑工艺，在该工艺期间，第一引线框架组件100的部分、第二引线框架组件102的部分以及间隔体120被嵌入到单个模塑化合物122中。亦即，相同的模塑化合物122整体地嵌入了引线框架组件100、102的部分以及间隔体120。因此，两个单独模塑的封装不是被堆叠成一个在另一个上以形成得到的封装内嵌结构，并且在两个引线框架组件100、102之间不存在物理模塑化合物界面。相反，本文中描述的封装内嵌结构实施例使用单个模塑化合物122，其整体具有连续结构以嵌入间隔体120并且经由常见模塑工艺部分地嵌入引线框架组件100、102。间隔体120可以包括与模塑化合物122相同或不同的材料。
第一引线框架组件100的管芯焊盘104的背离附接到管芯焊盘104的半导体管芯108的一侧124未被模塑化合物122覆盖。类似地，第二引线框架组件102的管芯焊盘106的背离附接到管芯焊盘106的半导体管芯110的一侧126也未被模塑化合物122覆盖。利用该配置，模塑半导体封装提供双侧散热。
第一引线框架组件100的引线112的一部分未被模塑化合物122覆盖，以形成半导体封装的第一组端子128。类似地，第二引线框架组件102的引线114的一部分未被模塑化合物122覆盖，以形成半导体封装的第二组端子130。端子128、130提供了用于嵌入到公共模塑化合物122中的半导体管芯108、110的外部电接触的点。
由引线框架组件100、102的引线112、114形成的端子128、130可以具有不同的配置。在该实施例中，第一组端子128位于模塑半导体封装的轮廓内并且与模塑半导体封装的底面132齐平。第二组端子130从半导体封装的一个或多个面延伸超出模塑半导体封装的轮廓。根据特定示例，引线框架组件100/102中的一个具有方形扁平无引线(QFN)或双扁平无引线(DFN)配置，并且另一个引线框架组件102/100具有方形扁平封装(QFP)或双小型轮廓封装(DSO)配置。例如QFN和DFN的扁平无引线封装配置在没有穿通孔的情况下将底部处的IC连接到印刷电路板(PSB)或类似基板的表面。QFP和DSO配置也是表面安装技术，但端子(引线)从封装的一个或多个侧面延伸而不是从底表面延伸。
在图1A和图1B中，第一引线框架组件100具有QFN或DFN配置，并且第二引线框架组件102具有QFP或DSO配置。第一引线框架组件100的引线112在模塑半导体封装的底面132处未被模塑化合物122覆盖。第二引线框架组件102的引线114在半导体封装的一个或多个侧面134处从模塑化合物122突出并在朝向封装的底面132的方向上弯曲。
图2示出了具有QFN或DFN配置的第一引线框架组件100和具有QFP或DSO配置的第二引线框架组件102的另一实施例。图2中所示的实施例与图1A和图1B中所示的实施例类似。然而，不同的是，第二引线框架组件102的引线114在朝向半导体封装的与底面132相对的顶面136的方向上弯曲。
图3示出了具有QFN或DFN配置的第一引线框架组件100和具有QFP或DSO配置的第二引线框架组件102的另一实施例。图3中所示的实施例与图2中所示的实施例类似。然而，不同的是，第二引线框架组件102的引线114的端部向内指向封装，而不是指向外。
图4示出了具有QFN或DFN配置的第一引线框架组件100和具有QFP或DSO配置的第二引线框架组件102的另一实施例。图4中所示的实施例与图3中所示的实施例类似。然而，不同的是，第二引线框架组件102的一些引线114的端部向内指向封装，并且第二引线框架组件102的其它引线114的端部指向外。
图5示出了两个引线框架组件100、102都具有QFN或DFN配置的实施例。根据该实施例，第一引线框架组件100的引线112在模塑半导体封装的底面132处未被模塑化合物122覆盖，并且第二引线框架组件102的引线114在封装的与底面132相对的顶面136处未被同一模塑化合物覆盖。
图6示出了两个引线框架组件100、102都具有QFP或DSO配置的实施例。根据该实施例，第一引线框架组件100的引线112在模塑半导体封装的一个或多个侧面134处从模塑化合物122突出并且在朝向封装的底面132的方向上弯曲。第二引线框架组件102的引线114也在半导体封装的一个或多个侧面134处从模塑化合物突出，但在朝向半导体封装的与底面132相对的顶面136的方向上弯曲。
图7示出了两个引线框架组件100、102都具有QFP或DSO配置的另一个实施例。图7中所示的实施例与图6中所示的实施例类似。然而，不同的是，如图6所示，第一引线框架组件100的引线112的端部向内指向模塑半导体封装，而不是指向外。
图8示出了两个引线框架组件100、102都具有QFP或DSO配置的另一个实施例。图8中所示的实施例与图6中所示的实施例类似。然而，不同的是，如图6所示，第二引线框架组件102的引线114的端部向内指向模塑半导体封装，而不是指向外。还设想了额外的QFP端子(引线)配置，并且其取决于模塑半导体封装将要附接到的板/PCB的对应导体轨迹布局。
如本文中前面所描述的，通过在第一引线框架组件100上方堆叠第二引线框架组件102并且在常见模塑工艺之前提供间隔体120以用于将引线框架组件100、102彼此分开，来制造模塑半导体封装。在引线框架组件100、102被堆叠并通过间隔体120彼此分开之后，第一引线框架组件100的部分、第二引线框架组件102的部分、以及间隔体120被嵌入到单个模塑化合物122中。接下来描述的是制造模塑半导体封装的具体实施例。
图9A到图9D示出了形成图1A和图1B中所示的第一引线框架组件100的一个实施例。
在图9A中，第一引线框架条200被提供有暂时附接到第一引线框架条200的底部的载体202。载体202在后续引线接合和常见模塑工艺期间提供支撑。第一引线框架条200包括通过框架208彼此互连的多个第一管芯焊盘204和多个第一引线206。每个管芯焊盘204和周围的一组引线206形成个体引线框架210，个体引线框架210例如经由所谓的系杆或类似结构通过框架208互连。引线框架条典型地例如通过冲压或蚀刻由扁平金属片构成。金属片典型地暴露于化学蚀刻剂，化学蚀刻剂去除未被光致抗蚀剂覆盖的区域。在蚀刻工艺之后，将经蚀刻的框架单一化(分离)成为引线框架条。每个引线框架条包括多个单元引线框架，每个单元引线框架具有本文中所述的管芯焊盘和引线构造。
在图9B中，第一半导体管芯212附接到第一引线框架条200的第一管芯焊盘204中的每一个。可以使用任何标准管芯附接工艺，例如焊接、烧结、胶合等。
在图9C中，第一半导体管芯212中的每一个被电连接到围绕第一管芯焊盘204的一组第一引线206，管芯212被附接到第一管芯焊盘204。例如，第一管芯212可以通过例如引线接合、金属夹、金属带等电导体214而连接到对应组的第一引线206。
在图9D中，通过例如激光切割、射流切割、锯切等的任何标准单一化工艺将第一引线框架条200单一化成为个体第一引线框架组件216。尽管在图9D中未示出，但是可以将间隔体材料施加到每个第一半导体管芯212的暴露的主表面。
图10A到图10C示出了形成图1A和图1B中所示的第二引线框架组件102的一个实施例。
在图10A中，提供第二引线框架条300，其包括通过框架306彼此互连的多个第二管芯焊盘302和多个第二引线304。框架306的一部分不在图10A中的视野内。如上所述，每个管芯焊盘302和周围的一组引线304形成引线框架308，其例如经由系杆或类似结构通过框架306而互连。同样在图10A中，第二半导体管芯310附接到第二引线框架条300的第二管芯焊盘302中的每一个。可以使用任何标准管芯附接工艺，例如焊接、烧结、胶合等。
在图10B中，第二半导体管芯310中的每一个被电连接到围绕第二管芯焊盘302的一组第二引线304，管芯310附接到第二管芯焊盘302。例如，第二管芯310可以通过例如引线接合、金属夹、金属带等电导体312被连接到对应组的第二引线304。
在图10C中，将间隔体314施加到第二引线框架条300的每个第二半导体管芯310的暴露的主表面。如前所述，在模塑工艺之前提供间隔体314作为结构支撑以实现管芯堆叠，并确保第一引线框架组件216的接合线连接214与第二引线框架条300的接合线连接312之间的足够的电隔离。优选但并非必要地，间隔体314是良好的热导体。间隔体314的一些示例为具有导热且电绝缘的填料的粘合剂或聚合物珠、膜或膏。这些仅是示例，并且不应被视为限制。
图9A到图9D和图10A到图10C中所示的工艺可以被反转，因为图1A和图1B中所示的第二引线框架组件102可以如图9A到图9D所示的那样被处理，并且图1A和图1B中所示的第一引线框架组件100可以如图10A至图10C所示的那样被处理。利用该方法，多个第二引线框架组件将作为单个引线框架条的部分而保持彼此附接，并且对应的第一引线框架条将被单一化成为个体第一引线框架组件。通常，图1A到图8中所示的QFN/DFN/QFP/DSO配置中的任一个可以通过图9A到图9D以及图10A到图10C中所示的工艺而产生。在每种情况下，一个引线框架条保持完整，并且另一引线框架条被单一化成为个体引线框架组件，以准备好用于后续处理，该后续处理产生采用常见工艺模塑的多个封装内嵌结构。
图11A到图11E示出了通过分别处理由图9A到图9D和图10A到图10C中所示的处理所实现的第一引线框架组件216和第二引线框架条300来形成图1A和图1B中所示的模塑半导体封装的一个实施例。再次，如上所述，图11A到图11E中所示的处理可以很容易地应用于本文中描述的QFN/DFN/QFP/DSO配置中的任一个。
在图11A中，在第一引线框架组件216和第二引线框架条300之间提供间隔体314之后，第二引线框架条300与第一引线框架组件216对齐，以使得每个第二半导体管芯310设置在第一半导体管芯212中的一个之上。第二半导体管芯310可以与相应的第一半导体管芯212竖直对齐或不对齐。
在图11B中，将引线框架组件的堆叠布置放置在标准模塑工具400中并经受常见的模塑工艺，在此期间，每个第一引线框架组件216的部分、附接到完整的引线框架条300的每个第二引线框架组件的部分、以及间隔体314嵌入到单个模塑化合物402中。亦即，同一个模塑化合物402整体地嵌入了每个第一引线框架组件216的部分、附接到完整的引线框架条300的每个第二引线框架组件的部分、以及间隔体314。因此，两个单独模塑的封装不是被堆叠成一个在另一个上以形成得到的封装内嵌结构。相反，在常见模塑工艺中，整体具有连续构造的单个模塑化合物402嵌入了间隔体314并且部分地嵌入了引线框架组件。可以使用任何标准模塑化合物。
同样在图11B中，示出了上引线框架组件216被预先单一化以允许模塑化合物402在所形成的封装内嵌结构的侧面中和周围流动。而且，底部引线框架组件保持以条形式附接到彼此，以实现常见模塑工艺。亦即，一个组的引线框架组件在嵌入单个模塑化合物402期间通过框架而保持互连。
在图11C中，得到的模塑封装内嵌结构404被从模塑工具400移除并保持通过下引线框架条300的框架306连接。
在图11D中，在嵌入到单个模塑化合物402中之后，移除暂时附接到第一引线框架组件216的载体202。如上所述，载体202在先前的引线接合和常见嵌入工艺期间提供支撑。在制造新的一组半导体封装的后续实例期间，可以重新使用载体202来提供支撑。
在图11E中，通过常见模塑工艺形成的模塑封装内嵌结构404被单一化成为个体封装406。可以使用任何标准模塑封装单一化工艺，例如修整和成型、激光切割、射流切割、锯切等。通过切割穿过将下引线框架组件互连的框架306来将模塑封装内嵌结构404单一化。如果在待切割的框架306的区段上形成模塑化合物402，则模塑化合物402也在该区域中被切割穿过以将模塑封装内嵌结构404单一化。
同样在图11E中，可以在常见工艺步骤中对每个引线206、304的未被模塑化合物402覆盖的部分进行去毛边和镀覆。可以使用任何标准去毛边工艺来去除在常见模塑工艺期间出现的毛刺。可以使用任何标准镀覆工艺来例如利用Sn、Sn合金、NiPdAu、Ni合金、Au、Au合金等镀覆引线206、304的暴露部分。引线206、304上的镀覆层可以包括一个或多个金属层，其使用非氧化金属或金属合金材料。也可以在常见工艺步骤中标记个体封装406。
图12A和图12B示出了图11A和图11B所示实施例的替代方法。代替具有暂时载体的基于QFN/DFN的引线框架组件设置在堆叠布置的底部上并且基于QFP/DSO的引线框架条设置在顶部上，顺序被反转。亦即，基于QFP/DSO的引线框架条设置在堆叠布置的底部上，并且具有暂时载体的基于QFN/DFN的引线框架组件设置在堆叠布置的顶部上。如图12B所示，堆叠布置然后被插入到模塑工具中并经受常见模塑工艺，以将每个第一引线框架组件216的部分、附接到完整的引线框架条300的每个第二引线框架组件的部分、以及间隔体314嵌入到单个模塑化合物402中。然后，所得到的封装内嵌结构的模塑布置可以经受例如图11C到图11E所示的常见工艺步骤。
如前所述，由个体引线框架组件的引线形成的端子可以具有不同的配置。例如，一个组的引线框架组件可以具有QFN或DFN配置，并且另一组的引线框架组件可以具有QFP或DSO配置。在其它情况下，所有引线可以具有相同的配置，例如QFN、DFN、QFP或DSO。
同样如前所述，包括在一个组的引线框架组件中的管芯可以设置在包括在另一组的引线框架组件中的对应半导体管芯之上并与其竖直对齐。在其它情况下，管芯竖直未对齐和/或一个管芯不设置在另一管芯之上。在每种情况下，在模塑工艺之前提供间隔体作为结构支撑以实现管芯堆叠，并确保堆叠的引线框架组件的接合线连接之间的足够的电隔离。
图13示出了模塑半导体封装的另一个实施例，其中下引线框架组件100包括单个半导体管芯108a，并且上引线框架组件102包括两个半导体管芯110a、110b，它们都不与下引线框架组件100的单个半导体管芯108a竖直对齐。间隔体120提供上引线框架组件102的半导体管芯110a、110b与下引线框架组件100的单个半导体管芯108a之间的分离。虽然下引线框架组件100被示为具有QFN/DFN引线配置，并且上引线框架组件102被示为具有QFP/DSO引线配置，但引线配置可以被反转或甚至是相同的。
图14示出了上面结合图1A和图1B所述的模塑半导体封装的又一个实施例。图14中所示的实施例与图13中所示的实施例类似。然而，不同的是，上引线框架组件102包括单个半导体管芯110a，并且下引线框架组件100包括两个半导体管芯108a、108b，它们都不与上引线框架组件102的半导体管芯110a竖直对齐。间隔体120再次提供下引线框架组件100的两个半导体管芯108a、108b与上引线框架组件102的单个半导体管芯110a之间的分离。如上所述，虽然下引线框架组件100被示为具有QFN/DFN引线配置，并且上引线框架组件102被示为具有QFP/DSO引线配置，但引线配置可以被反转或甚至相同。还构想了其它管芯/间隔体配置。通常，提供间隔体120以将引线框架组件100、102彼此分离并避免堆叠的引线框架组件100、102之间的接合线短路。
图15示出了模塑半导体封装的另一个实施例。图15中所示的实施例与图13中所示的实施例类似。然而，不同的是，半导体管芯110a、110b附接到单独的管芯焊盘204a、204b。
图16示出了模塑半导体封装的另一个实施例。图15中所示的实施例与图14中所示的实施例类似。然而，不同的是，半导体管芯110a、110b附接到单独的管芯焊盘204a、204b。
诸如“在……之下”、“在……下方”、“下部”、“在……之上”、“上部”等空间相对术语用于方便描述以解释一个元件相对于第二元件的定位。这些术语旨在涵盖除了与附图所示的取向不同的取向之外的设备的不同取向。此外，诸如“第一”、“第二”等术语也用于描述各种元件、区域、部分等，并且也不旨在进行限制。在通篇描述中，类似的术语指代类似的元件。
如本文所用，术语“具有”、“包含”、“包括”等是开放式术语，其指示存在所提及的元件或特征，但不排除额外的元件或特征。冠词“一”和“所述”旨在包括复数以及单数，除非上下文另外明确指出。
考虑到上述变型和应用的范围，应当理解，本发明不受前述描述的限制，也不受附图的限制。相反，本发明仅受以下权利要求及其合法等同物的限制。

Claims (20)

1.一种半导体封装，包括：
第一引线框架组件，其包括第一管芯焊盘、第一多个引线以及附接到所述第一管芯焊盘并电连接到所述第一多个引线的第一半导体管芯；
第二引线框架组件，其堆叠于所述第一引线框架组件上方，并且包括第二管芯焊盘、第二多个引线以及附接到所述第二管芯焊盘并电连接到所述第二多个引线的第二半导体管芯；
将所述第一引线框架组件和所述第二引线框架组件彼此分开的间隔体；以及
单个模塑化合物，其嵌入了所述第一引线框架组件的部分、所述第二引线框架组件的部分和所述间隔体，
其中，所述第一多个引线的一部分和所述第二多个引线的一部分未被所述模塑化合物覆盖，以形成所述半导体封装的端子，
其中，所述第一管芯焊盘的背离所述第一半导体管芯的一侧和所述第二管芯焊盘的背离所述第二半导体管芯的一侧未被所述模塑化合物覆盖。
2.根据权利要求1所述的半导体封装，其中，所述第一多个引线在所述半导体封装的底面处未被所述模塑化合物覆盖，并且其中，所述第二多个引线在所述半导体封装的一个或多个侧面处从所述模塑化合物突出，并且在朝向所述底面的方向上弯曲。
3.根据权利要求1所述的半导体封装，其中，所述第一多个引线在所述半导体封装的底面处未被所述模塑化合物覆盖，并且其中，所述第二多个引线在所述半导体封装的一个或多个侧面处从所述模塑化合物突出，并且在朝向所述半导体封装的与所述底面相对的顶面的方向上弯曲。
4.根据权利要求1所述的半导体封装，其中，所述第一多个引线在所述半导体封装的底面处未被所述模塑化合物覆盖，并且其中，所述第二多个引线在所述半导体封装的与所述底面相对的顶面处未被所述模塑化合物覆盖。
5.根据权利要求1所述的半导体封装，其中，所述第一多个引线在所述半导体封装的一个或多个侧面处从所述模塑化合物突出，并且在朝向所述半导体封装的底面的方向上弯曲，并且其中，所述第二多个引线在所述半导体封装的所述一个或多个侧面处从所述模塑化合物突出，并且在朝向所述半导体封装的与所述底面相对的顶面的方向上弯曲。
6.根据权利要求1所述的半导体封装，其中，所述引线框架组件中的一个具有方形扁平无引线(QFN)或双扁平无引线(DFN)配置，并且其中，所述引线框架组件中的另一个具有方形扁平封装(QFP)或双小型轮廓封装(DSO)配置。
7.根据权利要求1所述的半导体封装，其中，所述第一引线框架组件和所述第二引线框架组件均具有方形扁平无引线(QFN)或双扁平无引线(DFN)配置。
8.根据权利要求1所述的半导体封装，其中，所述第一引线框架组件和所述第二引线框架组件均具有方形扁平封装(QFP)或双小型轮廓封装(DSO)配置。
9.根据权利要求1所述的半导体封装，其中，所述间隔体是粘合剂。
10.根据权利要求1所述的半导体封装，其中，所述间隔体包括具有导热且电绝缘的填料的聚合物珠、膜或膏。
11.根据权利要求1所述的半导体封装，其中，所述第二半导体管芯设置在所述第一半导体管芯之上，并且其中，所述间隔体将所述第二半导体管芯与所述第一半导体管芯分离。
12.一种制造半导体封装的方法，所述方法包括：
提供多个第一引线框架组件，所述多个第一引线框架组件中的每者包括第一管芯焊盘、第一多个引线、以及附接到所述第一管芯焊盘并电连接到所述第一多个引线的第一半导体管芯；
在所述第一引线框架组件中的每者上方堆叠多个第二引线框架组件，每个第二引线框架组件包括第二管芯焊盘、第二多个引线、以及附接到所述第二管芯焊盘并电连接到所述第二多个引线的第二半导体管芯；
在所述第一引线框架组件和所述第二引线框架组件之间提供间隔体；
将每个第一引线框架组件的部分、每个第二引线框架组件的部分和每个间隔体嵌入到单个模塑化合物中，以使得第一多个引线中的每个的一部分和第二多个引线中的每个的一部分未被所述模塑化合物覆盖，以形成相应半导体封装的端子，并且使得每个第一管芯焊盘的背离相邻的第一半导体管芯的一侧和每个第二管芯焊盘的背离相邻的第二半导体管芯的一侧未被所述模塑化合物覆盖；以及
将所述相应半导体封装单一化成为个体封装。
13.根据权利要求12所述的方法，其中，在嵌入所述模塑化合物中期间，所述第一引线框架组件或所述第二引线框架组件通过框架保持互连。
14.根据权利要求13所述的方法，还包括：
切割穿过所述框架以将所述相应半导体封装单一化成为所述个体封装。
15.根据权利要求12所述的方法，还包括：
将所述第一引线框架组件或所述第二引线框架组件暂时附接到载体，所述载体在嵌入所述模塑化合物中期间提供支撑；以及
在所述嵌入之后移除所述载体。
16.根据权利要求15所述的方法，还包括：
在制造新的一组半导体封装的后续实例期间，重新使用所述载体来提供支撑。
17.根据权利要求12所述的方法，还包括：
在常见工艺步骤中，对未被所述模塑化合物覆盖的第一多个引线中的每个的所述部分和第二多个引线中的每个的所述部分进行去毛边和镀覆。
18.根据权利要求12所述的方法，还包括：
在常见工艺步骤中标记所述个体封装。
19.根据权利要求12所述的方法，其中，在所述第一引线框架组件中的每者上方堆叠第二引线框架组件包括：
提供引线框架条，所述引线框架条包括通过框架彼此互连的所述第一管芯焊盘；
将第一半导体管芯附接到所述第一管芯焊盘中的每个第一管芯焊盘；
将所述第一半导体管芯中的每个第一半导体管芯电连接到围绕所述第一管芯焊盘的所述第一多个引线，所述第一半导体管芯被附接到所述第一管芯焊盘；以及
在所述第一引线框架组件和所述第二引线框架组件之间提供所述间隔体之后，将所述引线框架条与所述多个第二引线框架组件对齐，以使得每个第二半导体管芯设置在所述第一半导体管芯中的一个之上。
20.根据权利要求19所述的半导体封装，其中，所述第一引线框架组件具有方形扁平无引线(QFN)或双扁平无引线(DFN)配置，并且其中，所述第二引线框架组件具有方形扁平封装(QFP)或双小型轮廓封装(DSO)配置。
CN201811473190.3A 2017-12-05 2018-12-04 用于半导体器件的封装内嵌结构和制造方法 Pending CN110034078A (zh)

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