CN106252457A - Mixed type polysilicon hetero-junctions back contact battery - Google Patents
Mixed type polysilicon hetero-junctions back contact battery Download PDFInfo
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- CN106252457A CN106252457A CN201610206738.2A CN201610206738A CN106252457A CN 106252457 A CN106252457 A CN 106252457A CN 201610206738 A CN201610206738 A CN 201610206738A CN 106252457 A CN106252457 A CN 106252457A
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- Prior art keywords
- layer
- silicon
- solaode
- back side
- silicon substrate
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 128
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 128
- 239000010703 silicon Substances 0.000 claims abstract description 127
- 238000000034 method Methods 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims description 40
- 238000000576 coating method Methods 0.000 claims description 40
- 239000006117 anti-reflective coating Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- 238000001465 metallisation Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 35
- 239000002019 doping agent Substances 0.000 description 29
- 238000005516 engineering process Methods 0.000 description 19
- 210000004027 cell Anatomy 0.000 description 14
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000521 B alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 208000031481 Pathologic Constriction Diseases 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000002082 metal nanoparticle Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000004447 silicone coating Substances 0.000 description 1
- 210000001215 vagina Anatomy 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
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Abstract
The invention discloses a kind of method for manufacturing high efficiency solar cell.Described method is included on the back side of silicon substrate and arranges film dielectric layer and doped polysilicon layer.Subsequently, high quality oxide layers and broad-band gap doping semiconductor layer can be formed on the described back side of described silicon substrate and front.Then metallization process can be performed metal flange to be plated on described doped polysilicon layer through contact openings.The metal flange of described plating can form the first metal grid grid line.The second metal grid grid line can be formed by the emitter district being directly plated on by metal on the described back side of described silicon substrate, thus eliminate the needs of the contact openings for described second metal grid grid line.In these advantages, the described method for manufacturing solaode is to manufacture high efficiency solar cell to provide the thermal process of minimizing, the etching step of minimizing, the efficiency of raising and the operation of simplification.
Description
The application be based on filing date December in 2012 19 days, (international application no is Application No. 2012800636868
PCT/US2012/070709), invention and created name is the Chinese patent application of " mixed type polysilicon hetero-junctions back contact battery "
Divisional application.
Technical field
The embodiment of theme described herein usually relates to solaode manufacture.Specifically, the enforcement of described theme
Example relates to slim silicon solar cell and manufacturing technology.
Background technology
Solaode be known to the device for converting solar radiation into electric energy.They can be at semiconductor wafer
On manufacture by semiconductor processing technology.Solaode includes p-type and N-type diffusion region.The impact sun on the solar cell
Radiation produces electronics and the hole migrating to diffusion region, thus forms voltage difference between diffusion region.At back contact solar electricity
Chi Zhong, diffusion region and the metal contact piece being connected with them are respectively positioned on the back side of solaode.Contact allows external circuit
It is connected on solaode and by solar cell for supplying power.
Efficiency is the key property of solaode, because it is directly connected to the generating capacity of solaode.Therefore,
Typically require for improving manufacturing process, reducing manufacturing cost and improve the technology of efficiency of solaode.This type of technology
Including being formed polysilicon and hetero junction layer on a silicon substrate by thermal process, the present invention is by this way for improving solaode
Efficiency create condition.These or other similar embodiment forms the background technology of the present invention.
Accompanying drawing explanation
When considering in conjunction with the following drawings, can be more fully understood from by seeing detailed description of the invention and claims
Described theme, the most in all of the figs, similar reference refers to the element being similar to.
Fig. 1-12 is the cross-sectional schematic manufacturing solaode according to embodiments of the invention
Figure 13-18 is the cross-sectional schematic manufacturing solaode according to an alternative embodiment of the invention
Detailed description of the invention
Detailed description below is the most illustrative, be not intended to limit the embodiment of described theme or this type of
The application of embodiment and purposes.As used herein, word " exemplary " refers to " as an example, example or illustration ".Show herein
Any embodiment that example describes is not necessarily to be construed as than other embodiments more preferably or favorably.Additionally, be not intended
Any expressed or managing of implying by what aforementioned technical field, background technology, summary of the invention or detailed description below proposed
The constraint of opinion.
Disclose the method manufacturing solaode.The method includes: provides and has film dielectric layer overleaf and thin Jie
There is on matter layer the silicon substrate of deposited silicon layer；Deposited silicon layer is formed dopant material layer；Dopant material layer is formed oxidation
Nitride layer；Oxide skin(coating), dopant material layer and deposited silicon layer is partly removed according to interdigitated pattern；Grown oxide layer, with this
Rise high-temperature simultaneously and enter in deposited silicon layer to order about the alloy from dopant material layer；Deposited silicon layer is made to be carried out auto-dope material
The alloy of the bed of material adulterates to form crystallization doped polysilicon layer；Broad-band gap doped semiconductor and anti-reflective coating are deposited upon too
On the back side of sun energy battery；And broad-band gap doped semiconductor and anti-reflective coating are deposited upon on the front of solaode.
Disclose another method manufacturing solaode.The method includes: provide have overleaf film dielectric layer and
Film dielectric layer has the silicon substrate of deposited silicon layer；Deposited silicon layer is formed dopant material layer；Shape on dopant material layer
Become oxide skin(coating)；Oxide skin(coating), dopant material layer and deposited silicon layer is partly removed according to interdigitated pattern；The silicon that etching is exposed
Substrate is to form veining silicon area；Grown oxide layer, meanwhile rises high-temperature to order about the doping from dopant material layer
Thing enters in deposited silicon layer；Deposited silicon layer is made to be adulterated by the alloy from dopant material layer and form doped polysilicon layer；Will
First thick-layer of broad-band gap doped amorphous silicon and ARC are coated in the back side of solaode；Adulterate amorphous by broad-band gap
Second thin layer of silicon and ARC are coated in the front of solaode, and wherein thin layer is less than the 10% of thick-layer thickness
To 30%.
Disclose another method manufacturing solaode.The method includes: provide have overleaf film dielectric layer and
Film dielectric layer has the silicon substrate of doped silicon layer；Form oxide skin(coating) on the doped silicon layer；According to interdigitated pattern part
Remove oxide skin(coating) and doped silicon layer；Grow on the back side of the solar cell by heating silicon substrate in an oxidizing environment
Silicon oxide layer, wherein silicon layer is crystallized and forms doped polysilicon layer；Broad-band gap doped semiconductor is deposited on solar-electricity
On the back side in pond；And broad-band gap doped semiconductor and anti-reflective coating are deposited upon on the front of solaode.
Disclose another method manufacturing solaode.The method includes: provide have overleaf film dielectric layer and
Film dielectric layer has the silicon substrate of doped silicon layer；Form oxide skin(coating) on the doped silicon layer；According to interdigitated pattern part
Remove oxide skin(coating) and doped silicon layer；The silicon substrate that etching is exposed is to form veining silicon area；By adding in an oxidizing environment
Hot silicon substrate and grow silicon oxide layer on the back side of the solar cell, wherein silicon layer is crystallized and forms DOPOS doped polycrystalline silicon
Layer；Broad-band gap doped amorphous silicon and anti-reflective coating are deposited upon on the back side of solaode；And it is non-broad-band gap to be adulterated
Crystal silicon and anti-reflective coating are deposited upon on the front of solaode.
Disclose another embodiment of the method manufacturing solaode.The method includes: offer has thin overleaf
Dielectric layer and there is on film dielectric layer the silicon substrate of doped silicon layer；Form oxide skin(coating) on the doped silicon layer；According to interdigitated
Pattern partly removes oxide skin(coating) and doped silicon layer；The silicon substrate that etching is exposed is to form veining silicon area；By in oxidation
Heating silicon substrate in environment and grow silicon oxide layer on the back side of the solar cell, wherein silicon layer is crystallized and forms doping
Polysilicon layer；Broad-band gap doped amorphous silicon and anti-reflective coating are deposited upon solaode on the front and back simultaneously；Portion
Remove broad-band gap doped semiconductor and oxide skin(coating) to form a series of contact openings with dividing；And simultaneously at solar battery back
Formed on face and be electrically coupled to the first metallic grid of doped polysilicon layer and be electrically coupled to second metallic grid in emitter district.
It is that film dielectric layer and deposited silicon layer are set on the back side of silicon substrate for manufacturing the improvement technology of solaode.
The region of DOPOS doped polycrystalline silicon can enter in deposited silicon layer by ordering about alloy or by being formed in situ doped polysilicon area and shape
Become.Then can be at the oxide skin(coating) of formation on the front and back of solaode and broad-band gap doping semiconductor layer.One modification
Related to the surface texturizing of front and back before oxide is formed and broad-band gap doped semiconductor is formed.May then pass through
The layer on top and form contact hole to expose doped polysilicon area.Then can carry out metallizing operation so that contact is formed at doping
On polysilicon layer.Second group of contact is formed also by the emitter district being connected directly on silicon substrate by metal, described
Beam district is formed by the wide bandgap semiconductor layers between the region of the DOPOS doped polycrystalline silicon being arranged on rear surface of solar cell.
Fig. 1-18 shows and combines the various operations that manufacturing process performs.It addition, the some operations in various operations are not
Perform the most in the indicated order, and can be merged into there is the more comprehensive operation of the additional function not described in detail herein, work
In skill or manufacture.
Fig. 1-3 shows the embodiment for manufacturing solaode 100, described solaode include silicon substrate 102,
Film dielectric layer 106 and deposited silicon layer 104.In certain embodiments, can formed before film dielectric layer 106 clean, polish, plane
Change and/or thinning or otherwise process silicon substrate 102.Film dielectric layer 106 and deposited silicon layer 104 can be raw via thermal technology's sequence
Long.Dopant material layer 108, the followed by first oxide skin(coating) 110 can be deposited on deposited silicon layer 104 by Conventional deposition processes.
Dopant material layer 108 can comprise dopant material or alloy 109, but is not limited to the eurymeric dopant material layer or such as of such as boron
The minus dopant material layer of phosphorus.Although film dielectric layer 106 and deposited silicon layer 104 are described as respectively via thermal technology's sequence growth or logical
Cross Conventional deposition processes deposition, but for any other formation, deposition or the growth technique step being described herein as or enumerate, often
Individual layer or material can use any suitable technique to be formed.Such as, every place addressing formation, chemical gaseous phase all can be used to sink
Long-pending (CVD) technique, low pressure chemical vapor deposition (LPCVD), atmospheric pressure cvd (APCVD), plasma enhanced CVD (PECVD), thermally grown, sputtering
And any other required technology.Therefore, and similarly, the such as ink-jet of deposition technique, sputtering or typography can be passed through
Print or silk screen printing, substrate is formed dopant material 108.
Fig. 4 shows and forms the phase starting from Fig. 1-3 after the multi-crystal silicon area 124 exposed at execution material-removing process
With solaode 100.Some examples of material-removing process include mask and etch process, laser ablation process and other
Similar techniques.The multi-crystal silicon area 124 and the dopant material layer 108 that expose are formed as any required form, including interdigitated pattern.
In the case of using mask process, screen process press or ink-jet printer can be used to perform, with according to predetermined interdigitated figure
Case applies mask ink (mask ink).Therefore, conventional chemical wet etching technique can be used to remove mask ink, generation is exposed
Multi-crystal silicon area 124 and the interdigitated pattern of dopant material layer 108.In at least one embodiment, removable first oxide skin(coating)
The some parts or whole of 110.This can remove the same etch in region or the ablation work of deposited silicon layer 104 and dielectric layer 106
Skill realizes, as shown in Figures 4 and 5.
Seeing Fig. 5, solaode 100 can carry out the second etch process, causes the multi-crystal silicon area 124 to exposing to be lost
Carve, form the first veining silicon area 130 with the back side at solaode and form the second texture in the front of solaode
SiClx district 132, thus strengthen solar radiation collection.Texturizing surfaces can be to have regular or erose surface, its
For scatter incident light, reduce the light quantity being reflected back from solar cell surface.
See Fig. 6, can at 140 heating solar battery 100, to order about the dopant material from dopant material layer 108
109 enter in deposited silicon layer 104.Identical heating 140 also can on dopant material layer 108 and the first veining silicon area 130 shape
Become Si oxide or the second oxide skin(coating) 112.In this technical process, trioxide layer 114 can be at the second veining silicon area
Grow on 132.Oxide skin(coating) 112,114 both of which can comprise high quality oxide.High quality oxide is generally by greatly
The interface state density oxides of thermal oxide growth at a temperature of 900 degrees Celsius, it can be that passivation improvement creates conditions.
Seeing Fig. 7, therefore deposited silicon layer 104 can be adulterated by the dopant material 109 from dopant material layer 108 and be formed and mix
Miscellaneous polysilicon layer 150.In one embodiment, can realize in the following way formed doped polysilicon layer: grown oxide layer,
Meanwhile rise high-temperature to enter in deposited silicon layer 104 to order about the alloy 109 from dopant material layer 108, wherein deposit
Silicon layer 104 is adulterated by the alloy 109 from dopant material layer 108, defines crystallization doped polysilicon layer or DOPOS doped polycrystalline silicon
Layer 150.In one of some embodiments, if employing eurymeric dopant material, then doped polysilicon layer 150 can comprise just adulterating many
Crystal silicon layer.In the illustrated embodiment, silicon substrate 102 includes block N-type silicon substrate.In certain embodiments, if employing negative
Type dopant material, then doped polysilicon layer 150 can comprise negative doped polysilicon layer.In one embodiment, silicon substrate 102 should wrap
Include block P-type silicon substrate.
See Fig. 8, the first broad-band gap doping semiconductor layer 160 can be deposited on the back side of solaode 100.One
In individual embodiment, the first broad-band gap doping semiconductor layer 160 is partially electronically conductive, and its resistivity is at least 10 Ω-cm.Identical
Embodiment in, it can have at the solaode currently covered by the first veining silicon area 130 and the second oxide skin(coating) 112
Rear surface regions is served as the band gap more than 1.05 electron-volts (eV) of hetero-junctions.The example of broad-band gap doped semiconductor includes carbon
SiClx and aluminium gallium nitride alloy.It is used as presenting any other broad-band gap doped semiconductor material of nature described above and feature
Material.First broad-band gap doping semiconductor layer 160 can be made up of the first thick broad-band gap doped amorphous silicon layer.
See Fig. 9, the second broad-band gap doped semiconductor 162 can be deposited on the second stricture of vagina on solaode 100 front
On physics and chemistry silicon area 132.In one embodiment, the broad-band gap doping semiconductor layer on solaode 100 back side and front
160,162 both of which can comprise broad-band gap minus doped semiconductor.In another embodiment, with the first thick broad-band gap doping half
Conductor layer is compared, and the second broad-band gap doped semiconductor 162 can be relatively thin.Therefore, in certain embodiments, the second thin broadband gap
Doping semiconductor layer can have the 10 to 30% of the first thick broad-band gap doped semiconductor layer thickness.In yet another embodiment, divide
It is not positioned at broad-band gap doping semiconductor layer 160,162 both of which in rear surface of solar cell and front to comprise broad-band gap minus and mix
Miscellaneous quasiconductor or broad-band gap eurymeric doped semiconductor.Subsequently, by same process, ARC (ARC) 170 can be deposited on
On two broad-band gap doped semiconductors 162.In another embodiment, by same process, ARC 170 can be deposited on
On one broad-band gap doped semiconductor 160.In certain embodiments, ARC 170 can be made up of silicon nitride.
Figure 10 shows first broad-band gap doped semiconductor the 160, second oxide skin(coating) on solaode 100 back side
112 and the part that carries out of dopant material layer 108 remove, described part removes to form a series of contact openings 180.At one
In embodiment, the technology of removing can be reached with ablating technics.A kind of such ablating technics is laser ablation process.Real at another
Executing in example, the technology of removing can be silk screen printing or the inkjet printing of any conventional wet etch process, such as mask, then continuous with erosion
Carving technology.
See Figure 11, the first metallic grid or grid line 190 can be formed on the back side of solaode 100.First gold medal
Possessive case grid line 190 is electrically coupled to the DOPOS doped polycrystalline silicon 150 in contact openings 180.In one embodiment, the first metallic grid
Line 190 may pass through the first broad-band gap doped semiconductor the 160, second oxide skin(coating) 112 and contact openings of dopant material layer 108
180 and formed, to connect by the positive electrical terminal of external circuit of solar cell for supplying power.
See Figure 12, can form the second metallic grid or grid line 192 on the back side of solaode 100, described
Two metal grid grid lines 192 are electrically coupled to the second veining silicon area 132.In one embodiment, the second metal grid grid line 192 can coupling
It is bonded to serve as first broad-band gap doped semiconductor the 160, second oxide skin(coating) 112 of hetero-junctions in rear surface of solar cell region
And the first veining silicon area 130, to be connected to by the negative electrical terminal of the external circuit of solar cell for supplying power.Real at some
Execute in example, the formation of the metal grid grid line related in Figure 11 and 12 can pass through electroplating technology, silk-screen printing technique, ink-jetting process,
It is plated on the metal formed by aluminum metal nano-particle or any other metallizes or metal formation process step performs.
Figure 13-18 shows another embodiment manufacturing solaode 200.Unless indicated additionally below, otherwise use
Refer to assembly or the digital labelling of structure that the digital marking class of the assembly of Figure 13-18 is similar to be used to refer in figure 1 above-12, no
Same is that label adds 100.
See Figure 13-14, may be included in shape on silicon substrate 202 for manufacturing another embodiment of solaode 200
Become the first oxide skin(coating) 210, film dielectric layer 206, doped polysilicon layer 250.Discussion as similarly described above, can form film dielectric layer
Clean before 206, polish, planarize and/or thinning or otherwise process silicon substrate 202.First oxide skin(coating) 210, Jie
Matter layer 206 and doped polysilicon layer 250 can grow via thermal technology's sequence.In one embodiment, by heating in an oxidizing environment
Silicon substrate 202 and grow silicon oxide layer or oxide skin(coating) 210 on the back side of the solar cell, wherein doped silicon layer is crystallized
And form doped polysilicon layer 250.In another embodiment, dielectric layer 206 grows doped polysilicon layer 250 and include raw
Long positive DOPOS doped polycrystalline silicon, wherein positive DOPOS doped polycrystalline silicon can be made up of dopant material 209 such as boron alloy.In another embodiment
In, negative DOPOS doped polycrystalline silicon can be used.Although film dielectric layer 206 and doped polysilicon layer 250 are described as respectively via thermal technology's sequence
Grow or deposited by Conventional deposition processes, but any other formation, deposition or the growth technique step that are just described herein as or enumerate
For Zhou, each layer or material can use previously discussed any suitable technique to be formed.
Solaode 200 can process the most further: uses conventional mask and etch process, partly moves
Except the first oxide skin(coating) 210, doped polysilicon layer 250 and dielectric layer 206 so that the exposed area 220 of silicon substrate is with interdigitated figure
Case manifests.In the case of using conventional mask and etch process, ablating technics can be used.If employing ablating technics, the
Monoxide layer 210 can keep partially complete, as shown in figure 14 on doped polysilicon layer 250.In another embodiment, silk
Wire mark brush or inkjet technology can use in conjunction with etch process.In such an embodiment, the first oxide skin(coating) 210 can be from doping
Polysilicon layer 250 etches away.
Seeing Figure 15, the silicon substrate 220 exposed of solaode 200 and the exposed area in front can be lost simultaneously
Carve, to form the first veining silicon face 230 and the second veining silicon face 232, thus strengthen solar radiation collection.
See Figure 16, at 240, solaode 200 can be heated to the temperature more than 900 degrees Celsius, simultaneously at the sun
The second oxide skin(coating) 212 can be formed and form trioxide layer 214 on solaode 200 front on battery 200 back side.
In another embodiment, two oxide skin(coating)s 212,214 can be made up of the high quality oxide being previously discussed as.
See Figure 17, the first broad-band gap doping semiconductor layer 260 can be concurrently deposited at the back side and just of solaode
On face.First broad-band gap doping semiconductor layer 260 can be partially electronically conductive, and its resistivity is more than 10 Ω-cm.First broad-band gap is mixed
Miscellaneous semiconductor layer 260 also can have the band gap more than 1.05eV.It addition, the first wide bandgap semiconductor layers can be by the first veining
Hetero-junctions is served as in the rear surface of solar cell region that silicon area 230 and the second oxide skin(coating) 212 cover.
First broad-band gap doping semiconductor layer 260 is than the second broad-band gap doping semiconductor layer 262 thickness 10% to 30%.?
In other embodiments, this thickness variable is to less than 10% or more than 30% without departing from the techniques described herein.Broad-band gap is mixed
Miscellaneous semiconductor layer 260,262 both of which can be positive doped semiconductor, but has its of different substrate and polysilicon doping polarity
In his embodiment, it is possible to use negative doped wide-bandgap semiconductor layer.Subsequently, ARC (ARC) 270 can be deposited on second
On broad-band gap doped semiconductor 262.In one embodiment, ARC 270 can be made up of silicon nitride.In some embodiments
In, it is possible to ARC is deposited on the first broad-band gap doping semiconductor layer 260.
See Figure 18, the first broad-band gap doping semiconductor layer 260 and can be removed in doped polysilicon layer 250 upper part
Dioxide layer 212 is to form a series of contact openings, and described contact openings is similar to above in association with that described in Figure 10-12
A bit, and form technology and be similar to above in association with those described in Figure 10-12.Subsequently, can on solaode 200 back side shape
Become the first metal grid grid line 290, the DOPOS doped polycrystalline silicon that wherein said first metal grid grid line 290 is electrically coupled in contact openings
250.The second metal grid grid line 292, described second metal grid grid line 292 electric coupling can be formed on solaode 200 back side
To the first veining silicon area or N-type emitter district 230.In one embodiment, the first metal grid grid line and can be concurrently formed
Two metal grid grid lines.Then can be by assembling other assemblies of the energy resource system of solaode 200, with the first metallic grid
Line 290 and the second metal grid grid line 292 realize supplementary contact.
Although detailed description above has shown that at least one exemplary embodiment, it is to be understood that, there is also substantial amounts of
Variations.It is also understood that one or more exemplary embodiment as herein described is not intended as limiting by any way to want
Ask the scope of the theme of protection, the suitability or configuration.On the contrary, above-mentioned detailed description will provide enforcement for those skilled in the art
The convenient courses of action figure of the one or more embodiment.Should be appreciated that and can limited without departing from claims
Function to element in the case of scope (known equivalent and predictable equivalent when it includes submitting present patent application to)
It is variously changed with arrangement.
Claims (20)
1., for manufacturing the method for solaode including silicon substrate, described silicon substrate has and is configured in normal work
During work towards the sun front and with the back side of described vis-a-vis, and described method includes:
Thering is provided silicon substrate, described silicon substrate has film dielectric layer on the described back side, and has on described film dielectric layer and mix
Miscellaneous silicon layer；
Described doped silicon layer is formed oxide skin(coating)；
Described oxide skin(coating) and described doped silicon layer is partly removed according to interdigitated pattern；
The silicon substrate that etching is exposed is to form the silicon area of veining；
On the described back side of described solaode, Si oxide is grown by heating described silicon substrate in an oxidizing environment
Layer, wherein said doped silicon layer is crystallized and forms doped polysilicon layer；
Broad-band gap doped amorphous silicon and anti-reflective coating are deposited upon on described front and the described back side of described solaode；
Partly remove described ARC, described broad-band gap doped amorphous silicon and described oxide skin(coating) to form a series of connecing
Touch opening；
The described back side of described solaode is formed the first metallic grid and the second metallic grid, described first metal grid
Grid are electrically coupled to described DOPOS doped polycrystalline silicon and described second metallic grid is electrically coupled to the part of described interdigitated pattern.
Method the most according to claim 1, wherein said doped polysilicon layer includes minus doped polysilicon layer.
Method the most according to claim 1, wherein said doped polysilicon layer includes eurymeric doped polysilicon layer.
Method the most according to claim 1, is wherein deposited upon the described front of described solaode by anti-reflective coating
With on the described front including on the described back side depositing silicon nitride on described solaode and the described back side.
5., for manufacturing the method for solaode including silicon substrate, described silicon substrate has and is configured in normal work
During work towards the sun front and with the back side of described vis-a-vis, and described method includes:
Thering is provided silicon substrate, described silicon substrate has film dielectric layer on the described back side, and has on described film dielectric layer and mix
Miscellaneous silicon layer；
Described doped silicon layer is formed oxide skin(coating)；
Described oxide skin(coating) and described doped silicon layer is partly removed according to interdigitated pattern；
The silicon substrate that etching is exposed is to form veining silicon area；
On the described back side of described solaode, Si oxide is grown by heating described silicon substrate in an oxidizing environment
Layer, wherein said silicon layer is crystallized and forms doped polysilicon layer；
Wide bandgap semiconductor layers and anti-reflective coating are deposited upon on the described back side of described solaode；And
Wide bandgap semiconductor layers and anti-reflective coating are deposited upon on the described front of described solaode.
Method the most according to claim 5, wherein said doped polysilicon layer comprises phosphorus.
Method the most according to claim 5, wherein said doped polysilicon layer comprises boron.
Method the most according to claim 5, wherein deposition wide bandgap semiconductor layers includes that deposition has more than 1.05 electronics
The quasiconductor of the band gap of volt.
9., for manufacturing the method for solaode including silicon substrate, described silicon substrate has and is configured in normal work
During work towards the sun front and with the back side of described vis-a-vis, and described method includes:
Thering is provided silicon substrate, described silicon substrate has film dielectric layer on the described back side, and has on described film dielectric layer and mix
Miscellaneous silicon layer；
Described doped silicon layer is formed oxide skin(coating)；
Described oxide skin(coating) and described doped silicon layer is partly removed according to interdigitated pattern；
On the described back side of described solaode, Si oxide is grown by heating described silicon substrate in an oxidizing environment
Layer, wherein said silicon layer is crystallized and forms doped polysilicon layer；
Semiconductor layer is deposited on the described back side of described solaode；And
Semiconductor layer and anti-reflective coating are deposited upon on the described front of described solaode.
Method the most according to claim 9, wherein provides described silicon substrate to include providing and have the silica-based of N-type bulk silicon
Plate.
11. methods according to claim 9, wherein provide described silicon substrate to include providing and have the silica-based of p-type bulk silicon
Plate.
12. methods according to claim 9, wherein partly remove described oxide skin(coating) and described according to interdigitated pattern
Doped silicon layer includes using etch process to remove described oxide skin(coating) and described doped silicon layer with the district of exposing exposing silicon substrate.
13. methods according to claim 9, wherein partly remove described oxide skin(coating) and described according to interdigitated pattern
Doped silicon layer includes using ablating technics to remove described oxide skin(coating) and described doped silicon layer with the district of exposing exposing silicon substrate.
14. methods according to claim 9, wherein deposition broad-band gap doped semiconductor includes that deposition has more than 1.05 electricity
The quasiconductor of the band gap of sub-volt.
15. methods according to claim 9, are wherein deposited upon the described front of described solaode by anti-reflective coating
On include depositing silicon nitride on the described front of described solaode.
16. methods according to claim 9, wherein partly remove described oxide skin(coating) and described according to interdigitated pattern
Doped silicon layer includes that the silicon substrate exposed with after etching is to form veining silicon area.
17. methods according to claim 9, also include the institute partly removing on the described back side of described solaode
State semiconductor layer, described oxide skin(coating) and described doped polysilicon layer to form a series of contact openings.
18. methods according to claim 17, are additionally included on the described back side of described solaode and form the first gold medal
Possessive case grid, described first metallic grid is electrically coupled to open through described a series of interfaces of described semiconductor layer and described oxide layer
Doped polysilicon layer in Kou.
19. methods according to claim 18, are additionally included on the described back side of described solaode and form the second gold medal
Possessive case grid, described second metallic grid is electrically coupled to a part for described interdigitated pattern.
20. methods according to claim 19, wherein form the first metal on the described back side of described solaode
Grid and the second metal grate include concurrently forming the first metal grate and the second metal grate.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/333,908 US8679889B2 (en) | 2011-12-21 | 2011-12-21 | Hybrid polysilicon heterojunction back contact cell |
| US13/333,904 US8597970B2 (en) | 2011-12-21 | 2011-12-21 | Hybrid polysilicon heterojunction back contact cell |
| US13/333,904 | 2011-12-21 | ||
| US13/333,908 | 2011-12-21 | ||
| CN201280063686.8A CN104011881B (en) | 2011-12-21 | 2012-12-19 | Mixed type polysilicon hetero-junctions back of the body contact battery |
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| CN201280063686.8A Active CN104011881B (en) | 2011-12-21 | 2012-12-19 | Mixed type polysilicon hetero-junctions back of the body contact battery |
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| KR (3) | KR102223562B1 (en) |
| CN (2) | CN106252457B (en) |
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| US12021158B2 (en) | 2022-10-11 | 2024-06-25 | Golden Solar (Quanzhou) New Energy Technology Co., Ltd. | Mask-layer-free hybrid passivation back contact cell and fabrication method thereof |
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| TW201707224A (en) | 2017-02-16 |
| JP6701295B2 (en) | 2020-05-27 |
| AU2015210421B9 (en) | 2017-11-09 |
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| JP2019024107A (en) | 2019-02-14 |
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| JP6208682B2 (en) | 2017-10-04 |
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| CN104011881A (en) | 2014-08-27 |
| KR20190073594A (en) | 2019-06-26 |
| JP2020129689A (en) | 2020-08-27 |
| JP2015505167A (en) | 2015-02-16 |
| JP2017228796A (en) | 2017-12-28 |
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| WO2013096500A1 (en) | 2013-06-27 |
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| AU2012358982B2 (en) | 2015-05-07 |
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| AU2015210421B2 (en) | 2017-06-01 |
| KR20200039850A (en) | 2020-04-16 |
| TW201344931A (en) | 2013-11-01 |
| DE112012005381T5 (en) | 2014-09-04 |
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