FR3037721B1 - PROCESS FOR PRODUCING A PHOTOVOLTAIC CELL WITH HETEROJUNCTION AND PHOTOVOLTAIC CELL THUS OBTAINED - Google Patents

Abstract

A heterojunction photovoltaic cell comprising: - a crystalline silicon substrate (1) comprising a main surface provided with at least one textured area and a planar area, - a first layer of a first conductivity type (4) covering only the area textured, - a second layer of a second conductivity type (3) covering only the flat area, the substrate (1) forming a p / n junction with the first layer (4) or with the second layer (3).

Description

Process for producing a heterojunction photovoltaic cell and photovoltaic cell thus obtained

TECHNICAL FIELD OF THE INVENTION The invention relates to a method for producing a heterojunction photovoltaic cell. State of the art

Conventionally, a photovoltaic cell is formed by a diode, for example, a p / n type junction made of a semiconductor material such as silicon. The diode then comprises a zone doped with a p-type impurity, for example boron, and a zone doped with an n-type impurity, for example phosphorus.

Silicon heterojunction cells combine a crystalline silicon substrate, c-Si, associated with ultra-thin layers of amorphous silicon a-Si: H, deposited to form junctions with crystalline silicon.

Conventionally, in a heterojunction cell contacted on the rear face (RCC-HIT cells), the front face of this type of cell is covered by a stack of layers (full-plate deposit) so as to passivate the crystalline silicon surface and form an anti-reflective layer. The front face, receiving side of the light, is also textured to increase the optical path of the light in the device and to increase the absorption of solar radiation.

Research has been carried out to improve the collection of electron-hole pairs, the Back Surface Field configuration in English or BSF is advantageous. This field improves the electrical characteristics of the solar cell, in particular the open circuit voltage by reducing the dark current. In fact, porters who become minority after their injection into the rear zone move away from the depletion zone. The rear electric field "BSF" pushes them towards the junction.

Finally, new architectures have been proposed to release the collection surface, the front surface. The rear contact cells, in English "Rear Contact Cell" RCC, allow to have both the emitter and BSF areas located on the back side and thus avoid shading due to the metallization of the face before.

The emitter / BSF patterns of the rear face of the RCC-HIT cells have, for example, an interdigital geometry.

Two metal grids can be used to collect minority and majority carriers respectively on its back side.

The rear face of the cells is usually completely polished because a polished surface facilitates the manufacture of said patterns by conventional techniques (screen printing, laser engraving, photolithography, etc.). Nevertheless, if the definition of these motifs is not restrictive, this face be textured in the same way as the light-receiving face.

These architectures, and more particularly the realization of emitter / BSF patterns, are, however, relatively complex to implement, especially on textured substrates, and have risks of poor performance.

OBJECT OF THE INVENTION The object of the invention is to overcome the drawbacks of the prior art and to propose a process for producing a heterojunction photovoltaic cell making it possible to produce thin-film patterns in a simplified manner, and making it possible to obtain a Photovoltaic cell with better yields.

This object is achieved by a method for producing a heterojunction photovoltaic cell, characterized in that it comprises the following successive steps: a) providing a crystalline silicon substrate comprising a main face provided with at least one textured zone covered with a first layer having a first conductivity type p or n and a planar area, b) forming a second layer having a second type of conductivity n or p, opposite the first conductivity type p or n, simultaneously with the surface of the textured area covered with the first layer and on the surface of the flat area of the main face, c) etch the second layer. At the end of step b), the portion of the second layer deposited on the surface of the textured zone covered with the first layer has a thickness and less than the thickness ep of the portion of the second layer deposited at the surface of the planar zone, so that at the end of the step c) etching, only the portion of the second layer deposited on the surface of the planar region is retained.

The substrate forms a p / n junction with the layer selected from one of the first and second layers and has a conductivity type opposite to that of the substrate.

This object is also achieved by a heterojunction photovoltaic cell comprising: a crystalline silicon substrate comprising a main surface provided with at least one textured area and a planar area, a first layer of a first conductivity type covering only the textured zone, - a second layer of a second conductivity type covering only the flat area, the substrate forming a p / n junction with the first layer or with the second layer.

BRIEF DESCRIPTION OF THE DRAWINGS Other advantages and features will emerge more clearly from the following description of particular embodiments of the invention given as non-restrictive examples and represented in the accompanying drawings, in which: FIGS. 1i show, schematically, in section, various steps of a method for producing a photovoltaic cell being developed, according to one embodiment of the invention, - Figures 2a to 2d, represent, schematic, in section, various steps of a method of producing a substrate having a planar zone and a textured zone according to an embodiment of the invention; - FIGS. 3a to 3f, show schematically, in section , various steps of a method of producing a substrate having a planar zone and a textured zone according to another embodiment of the i nvention, - Figures 4a to 4d, show schematically, in section, different steps of a method of producing a photovoltaic cell being developed, according to another embodiment of the invention.

Description of a preferred embodiment of the invention

As represented in FIGS. 1a to 1c, the process for producing a heterojunction photovoltaic cell comprises the following successive steps: a) providing a crystalline silicon substrate 1 comprising a main surface provided with at least one textured zone 2a covered with a first layer 4 having a first conductivity type p or n 4 and a flat area 2b, b) forming a second layer 3 having a second type of conductivity n or p, opposite to the first type of conductivity p or n, simultaneously with the surface of the textured zone 2a covered with the first layer 4 and on the surface of the flat zone 2b of the main face, c) etching the second layer 3. At the end of step b), the part of the second layer deposited on the surface of the textured zone 2a covered with the first layer has a thickness and less than the thickness ep of the portion of the second layer deposited on the surface of the flat zone 2b, so that at the end of the etching step c), only the portion of the second layer 3 deposited on the surface of the plane zone 2b is retained.

The substrate 1 forms a junction p / n with the layer chosen from one of the first and second layers 3, 4 and which has a conductivity type opposite to that of the substrate.

To produce the heterojunction photovoltaic cells, the silicon substrate 1, supplied in step a), is crystalline, that is to say monocrystalline or polycrystalline.

The substrate comprises a first face, the main face, and a second face.

The second face is advantageously intended to form the front face of the photovoltaic cell. The front is the receiving side of the light. It can be textured to increase the absorption of light.

The main face is intended to form the rear face of the photovoltaic cell. It is provided with at least one textured zone 2a and at least one flat zone 2b.

Textured area means that the area has reliefs, the reliefs being at least 2μιτι high. The height is measured perpendicularly to the plane zone 2b of the substrate. The distance is the height between two reliefs. Preferably, the textured zone 2a is in the form of pyramids.

The pyramids have a height between 2μιτι and 20μιτι, and even more preferably between 2μιτι and 7μιτι.

Pyramids advantageously have a uniform height, that is to say that on the same textured area all the pyramids have the same height to a few micrometers. For example, for pyramids 5μιτι high, all pyramids have a height of 5 ± 2μιτι.

"Flat area" means a surface having a roughness of between 0.05 μm and 1 μm, and preferably between 0.2 μm and 0.3 μm.

The textured zone 2a is covered with a first amorphous layer of a first conductivity type 4. Preferably, the flat zone 2b is not covered by the first amorphous layer 4.

The geometry of the amorphous layer of the first conductivity type 4 follows the geometry of the textured zone 2a.

The first layer 4 and the second layer 3 are, preferably, amorphous and, even more preferentially, amorphous silicon. It is conceivable to use semiconductor materials of group III-V instead of silicon.

The first amorphous layer 4 is doped. It is of a first type of conductivity.

Preferably, the substrate is of a conductivity type opposite to the conductivity type of the first amorphous layer 4, so as to form a p / n type heterojunction with the substrate. For example, the substrate is of N-type crystalline silicon and the first amorphous layer 4 is p-doped amorphous silicon, (p) a-Si: H. In this particular embodiment, the first amorphous layer 4 plays the role of 'transmitter.

In another embodiment, the substrate is of the same type of conductivity as the first amorphous layer 4. For example, the substrate is p-type crystalline silicon and the first amorphous layer 4 is p-doped amorphous silicon, (p) a-Si: H. In this particular embodiment, the first amorphous layer 4 plays the role of BSF.

According to a preferred embodiment, to ensure a better lifetime of the carriers at the interface, ie to minimize the recombination of the carriers, the amorphous silicon layer 4 of the first conductivity type is formed of a stack of a first undoped or slightly doped layer covered with a doped layer.

The first layer, in contact with the substrate, not or little doped, passive interface. Effective passivation can be achieved by means of a first layer having a thickness of between 3 and 10 nm, and preferably between 3 nm and 4 nm. By little doped means for example a doping of the order of 1.1011cm'3. The first layer is, advantageously, of intrinsic amorphous silicon, (i) a-Si: H.

The second layer is doped, type N or P, depending on the desired doping, and provides the electric field necessary for the collection of carriers. This layer advantageously has a thickness ranging from 3 to 30 nm, and preferably from 10 to 15 nm. The resulting stack of layers will be (i) a-Si: H / (p) a-Si: H or (i) a-Si: H / (n) a-Si: H depending on the type of doping desired. The emitter and / or the BSF of the solar cell can advantageously be made using intrinsic amorphous silicon materials (i) a-Si: H, in combination with microcrystalline silicon μο-Si: H, doped. The percentage of crystallinity is advantageously between 30% and 60%. These materials are advantageously deposited by PECVD but can be deposited by other techniques such as chemical vapor deposition by hot filament (HW-CVD) for example. The thickness of the amorphous layer 4 is advantageously between 6 nm and 30 nm.

Preferably, and as represented in FIG. 1a, the amorphous silicon layer of a first conductivity type 4 is covered with a sacrificial barrier layer 5, before the deposition of the second amorphous layer of a second conductivity type 3. The amorphous silicon layer 4 is disposed between the crystalline silicon substrate 1 and the sacrificial barrier layer 5.

The sacrificial barrier layer 5 advantageously protects the first amorphous layer 4 during the etching step.

In step b), a second amorphous layer of a second conductivity type 3 is deposited on the textured portion 2a and on the flat portion 2b.

The second amorphous layer 3 deposited on the textured zone 2a has a thickness and less than the thickness ep of the second amorphous layer 3 deposited on the flat zone 2b.

Without being bound by the theory, the difference in thickness comes from the ratio between the effective or effective surfaces of a textured zone and a flat zone (also called non-textured zone) for the same given flow of species reaching the substrate 1. The ratio of thickness ep / and ranges from 1.5 to 2, and preferably, it ranges from 1.6 to 1.7. The thickness of the second amorphous layer 3 deposited on the plane zone 2b is between 5 nm and 50 nm, before the etching step. Preferably, the thickness of the second amorphous layer 3 deposited on the plane zone 2b is between 10 nm and 40 nm.

The amorphous layer 3 is advantageously deposited by plasma-assisted chemical vapor deposition (PECVD). The deposit could be made by any other suitable technique.

The deposit is advantageously made full plate.

The first type of conductivity is opposite to that of the second type of conductivity.

For example, the substrate is of N-type crystalline silicon, the first amorphous layer 4 is p-doped amorphous silicon, (i) a-Si: H / (p) a-Si: H and the second amorphous layer is silicon In this particular embodiment, the first amorphous layer 4 acts as an emitter and the second amorphous layer 3 makes it possible to form an amorphous doped n, (i) a-Si: H / (n) a-Si: H. rear electric field BSF.

The positions of the transmitter and the BSF can be reversed. The second amorphous layer 3, connected to the substrate 1, can form the junction p / n.

Like the first doped amorphous layer of the first conductivity type 4, the amorphous silicon layer of the second conductivity type 3 may be formed of a stack of a first undoped or slightly doped layer covered with a doped layer.

Advantageously, only the side faces of the amorphous layers 3, 4 are in contact.

According to another embodiment, they may not be in contact (in the case of a structure with a step between the flat area and the textured area, this difference in height being created during the formation of the substrate).

The second amorphous layer 3 is then etched (step c)).

The second amorphous layer 3 is advantageously etched in a single step. Only one etch chemistry is used to etch the thin film in one step. The etching is advantageously a wet etching. This is for example an etching by means of an alkaline or acidic solution. Preferably, the etching is isotropic.

The layer 3 is etched simultaneously on the flat area 2b and on the textured area 2a.

As at the end of step b), the portion of the second layer deposited on the surface of the textured zone 2a has a thickness and less than the thickness ep of the portion of the second layer deposited on the surface of the 2b, it is possible to adjust the etching time so as to completely etch the portion of the second amorphous layer 3 disposed at the level of the textured zone, and at the same time, so as to leave part of the layer thin disposed at the level of the flat area 2b.

Preferably, the etching rate of the second amorphous layer 3 is identical at the level of the plane zone 2b and at the level of the textured zone 2a. The thickness of the second amorphous layer 3 at the level of the plane zone 2b, obtained after the etching step, is advantageously between 3 nm and 40 nm, and even more preferably between 6 nm and 30 nm.

This range of thickness is sufficient to properly passivate the surface while avoiding resistive losses in the layers.

The second amorphous layer 3 is self-aligned with the planar area without using a step with an etching mask to be aligned.

The etching of the amorphous second amorphous silicon layer 3 (step c) -figure 1c) is advantageously a wet etching. The etching solution is chosen from HF-O3, KOH, NH4OH, TMAH, N2H4, etc.). The concentration of the etching solution is between 1 and 30%.

An isotropic plasma etching may be considered as an alternative.

The sacrificial barrier layer 5 protects the amorphous layer of the first conductivity type 4 during the etching of the second amorphous layer 3.

After the etching step, the sacrificial barrier layer 5 is advantageously removed (FIG. 1d). It can be removed by any suitable technique.

The complete etching of the sacrificial barrier layer or the stack of layers forming the sacrificial barrier layer is advantageously carried out with chemical solutions such as HF, HNO 3 -HF or BOE ("Buffered oxide etch"). The etching can also be performed by dry etching or by laser etching.

The type of etching, and in particular, the etching solution used in the case of wet etching, will be chosen so as not to damage the amorphous silicon layers (emitter and BSF).

Electrical contacts 8 may then be formed: a first electrical contact electrically connected to the first amorphous layer 4 and a second electrical contact electrically connected to the second amorphous layer 3.

The first electrical contact and the second electrical contact are electrically dissociated. The contacts have no interface with the substrate to prevent short circuits.

Electrical contact materials are electrically conductive. They are for example aluminum and / or ITO.

The electrically conductive contacts 8 can be deposited by any suitable technique, preferably by spraying, electrochemical deposition, screen printing, evaporation, inkjet.

FIGS. 1e to 1i represent different steps of a preferred embodiment for forming the electrical contacts of the photovoltaic cell.

The electrical contacts are formed according to the following successive steps: depositing an electrically conductive layer 6 in transparent conductive oxide (OTC or TCO), preferably in indium-tin oxide, on the first layer first conductivity amorphous layer 4 and on the second amorphous second conductivity layer 3 (FIG. 1e), - deposition of an insulating paste 7 on the OTC layer 6, on the first amorphous first conductivity layer 4 and on the second layer second conductivity amorphous layer 3, the conductive transparent oxide layer 6 separating the insulating paste 7 from the amorphous layers 3, 4 (FIG. 1f), etching of the OTC layer 6 not covered by the insulating paste 7, so as to separate the OTC layer in two distinct parts, the first part being electrically connected to the amorphous layer of first conductivity 4 and the second part being electrically connected the second amorphous layer of second conductivity 3 (1g); the etching is, for example, carried out with a HCl solution, - etching of the insulating paste 7 with an alkaline solution, for example with a KOH solution (FIG. 1 h), - forming electrical contacts 8 on the oxide layer transparent conductive, for example by screen printing (Figure 1i).

In the case where the paste 7 is an electrically conductive paste, the last two steps are not performed. The paste 7 then advantageously serves as a pattern for etching the OTC layer 6 and, at the same time, it forms electrical contacts.

The substrate used in step a) of the method described above can be obtained by several embodiments which will now be described.

In a first embodiment, the substrate provided in step a) is produced according to the following successive steps (FIGS. 2a to 2d): i. depositing an amorphous silicon layer of a first conductivity type 4 on a fully textured face of a substrate 1 (FIG. 2a), ii. depositing a sacrificial barrier layer 5, the barrier layer 5 partially covering the amorphous silicon layer 4 (FIG. 2b), iii. etching the portion of the amorphous silicon layer 4 not covered by the sacrificial barrier layer 5, so as to release a portion of the main face of the substrate (FIG. 2c), iv. polishing the released portion of the face of the substrate to form a flat area 2b (Figure 2d).

By fully textured is meant that at least 90% of the face of the substrate is textured, and preferably at least 95%.

To obtain a pyramidal texture on a crystalline silicon substrate 1, a planar substrate can be etched with a chemical solution of KOH, NH 4 OH, TMAH, N 2 H 4 at concentrations of between 1% and 10%.

The geometry of the deposited layers advantageously follows the geometry of the main face of the substrate, so as to maintain a planar zone and a textured zone.

When layers are deposited on the flat area 2b, the layers also have a flat surface 2b.

The layers deposited on the textured zone 2a preferably have the same geometry as the textured zone 2a. This is a compliant deposit.

The sacrificial barrier layer deposited during step ii) may be formed of a single layer or a stack of layers of different materials. Preferably, the material or materials will be selected from SiN, SiC, or Al2O3. Still more preferably, the sacrificial barrier layer 5 is an SiO 2 layer. The thickness of the barrier layer 5 is between 50nm and 1μητι, and preferably between 0.5 / vm and 1 μιτι.

The choice of the nature and the thickness of the sacrificial barrier layer 5 is made according to the structure and the stresses present.

The sacrificial barrier layer 5 may be deposited by any suitable technique chosen by those skilled in the art.

The portion of the first amorphous layer 4 not protected by the sacrificial barrier layer 5 is preferably wet etched (step iii). Preferably, it is etched with a solution of KOH, NH4OH, TMAH, or N2H4 having a concentration of 10% to 30%.

According to a preferred embodiment, the deposits of both the first amorphous layer 4 and the sacrificial barrier layer 5 could be made, both, full plate.

The method comprises the following steps (replacing steps ii and iii): ii '. depositing a sacrificial barrier layer 5 on the amorphous silicon layer 4, iii '. etching the sacrificial barrier layer 5 and the amorphous silicon layer 4, so as to release a portion of the textured face of the substrate.

Laser etching will advantageously be used to remove the barrier layer and the amorphous silicon layer 4.

The two layers will advantageously be removed during the same step.

In step iv), the substrate, not covered by the amorphous layer 4 and the sacrificial barrier layer 5, is polished with a chemical solution (KOH, NH4OH, TMAH, N2H4, etc.) with concentrations typically comprised between 10 and 30%.

This last step results in the formation of a substrate 1 having a flat zone 2b (the polished zone) and a textured zone 2a (FIG. 2d).

In Figure 2d, the base of the pyramids coincides with the surface of the flat area 2b.

However, according to some embodiments, the polishing step is further advanced and leads to the formation of a difference in height between the base of the pyramids and the surface of the planar zone. This difference in height (or walking) can be of the order of 5-20pm.

According to a second embodiment, the substrate 1 supplied in step a) is obtained according to the following successive steps (FIGS. 3a to 3f): I. depositing a first 5 'sacrificial barrier layer on a completely flat face of a substrate 1 (Figure 3a), II. removing a portion of the first sacrificial barrier layer 5 ', so as to release a portion of the face of the substrate 1 (Figure 3b), III. forming a textured zone 2a on the released portion of the substrate 1 (Figure 3c), IV. completely withdrawing the first sacrificial barrier layer 5 ', so as to release the plane zone 2b of the substrate (FIG. 3d), V. successively depositing an amorphous silicon layer 4 of a first conductivity type and a second sacrificial barrier layer 5 " on the textured zone 2a and on the flat zone 2b of the substrate 1, the sacrificial barrier layer 5 "preferably covering completely the amorphous silicon layer 4 of the first conductivity type, the amorphous layer 4 covering both the textured zone 2a and the plane zone 2b of the substrate (FIG. 3e), VI. locally etching the second sacrificial barrier layer 5 "and the amorphous silicon layer 4, so as to release the flat area 2b of the substrate (Figure 3f). The thickness of the barrier layer 5 "is between 50 nm and 1 μm, and preferably between 0.5 μm and 1 μm.

The etching solutions and the deposition techniques are the same as those described in the first embodiment of the substrate 1.

Thanks to this method, the realization of the emitter / BSF units of a back-contacted heterojunction photovoltaic cell (RCC-HIT) is simplified, even for producing patterns having an interdigitated geometry.

This method can be used to make photovoltaic cells with more complex architectures.

Advantageously, this same method can be used on a crystalline silicon substrate provided with a p / n junction and whose main face of the substrate 1 comprises a textured zone 2a disposed between two planar zones 2b, 2b '(FIG. 4a). The stack shown in Figure 4a is obtained according to steps a, b and c) shown in Figures 1a to 1d. Axis AA 'represents an axial plane of symmetry. On either side of the axis, we find the cell of Figure 1d.

The textured zone 2a is covered with a first amorphous silicon layer of a first conductivity type 4.

The planar zones 2b, 2b 'are covered with a second amorphous silicon thin layer of a second conductivity type 3.

Preferably, the amorphous layers 4, 3 are not superimposed, do not overlap each other.

A conductive transparent oxide layer 6 is formed on this stack, represented in FIG. 4a, according to the following steps: a ') providing a crystalline silicon substrate 1 comprising a main face provided with at least one textured zone 2a covered with a first layer of a first conductivity type 4 and a flat area 2b covered with a second layer of a second conductivity type 3, b ') forming a conductive transparent oxide thin layer 6 simultaneously on the textured area 2a and on the plane zone 2b of the main face, the thin layer deposited on the textured zone 2a having a thickness e less than the thickness ep- of the thin layer deposited on the flat zone 2b, c ') etching the thin oxide layer transparent conductor 6 simultaneously on the flat area 2b and the textured area 2a, so as to leave only a portion of the conductive transparent oxide thin layer 6 on the flat area 2b.

The substrate 1 forms a junction p / n with the first layer 4 or with the second layer 3. The first layer 4 and the second layer 3 are advantageously of amorphous material.

The conductive transparent oxide layer 6 is, preferably, an indium-tin oxide layer. The OTC thin film 6 has two thicknesses: a first thickness at the textured zone 2a and a second thickness at the flat areas 2b, 2b '. The first thickness is less than the second thickness.

The thin layer 6 covers the two amorphous silicon layers 4, 3.

Preferably, as represented in FIG. 4c, the method comprises an additional step, before the etching step c), in which a paste 7 is deposited on the OTC layer 6, so as to cover part of the textured zone 2a. .

The paste 7 can be deposited by screen printing.

The OTC thin film 6 is then etched (step c) so as to make part of the first and second amorphous layers 3, 4 accessible. The OTC thin film 6 may be etched by wet etching.

The wet etching is preferably carried out with a solution of HCl or HF.

Advantageously, the etching is performed so as to remove the OTC layer 6 at the level of the textured zone 2a not covered by the insulating paste, and so as to leave only the OTC layer 6 at the level of the flat area 2b.

Once the OTC layer 6 has been etched, the OTC layer is in three distinct parts: a part on each plane zone 2b, 2b 'and a part placed between the amorphous layer 4 and the paste 7, at the level of the part textured 2a (Figure 4d).

If the paste 7 is electrically insulating, the paste 7 is removed, and electrical contacts 8 are formed on the conductive transparent oxide layer 6. A first contact is formed on the first amorphous layer of the first conductivity type 4 and a second contact is formed on the second amorphous layer of the second conductivity type 3. The stack represented in FIG. 4a can be obtained as described above, that is to say according to the steps a) to c) of FIGS. 1e, but it could also be envisaged to be realized by other techniques.

The heterojunction photovoltaic cell, obtained according to one of the methods described above, comprises: a crystalline silicon substrate 1 comprising a main surface provided with at least one textured zone 2a and a flat zone 2b; a first layer amorphous of a first type of conductivity 4 covering only the textured area 2a, - a second amorphous layer of a second conductivity type 3 covering only the flat area 2b.

The substrate 1 forms a p / n junction with the first amorphous layer 4 or with the second amorphous layer 3.

According to a particular embodiment, a conductive transparent oxide layer covers the first and second amorphous layers 4, 3.

An electrical contact is disposed on the conductive transparent oxide layer 6 at the textured area 2a.

A second electrical contact is arranged on the conductive transparent oxide layer 6 at the level of the flat area 2b.

The conductive transparent oxide layer will, advantageously, subsequently split into two parts so as to isolate the two electrical contacts of the first 4 and second 3 layers.

The method makes it possible to obtain a photovoltaic cell whose main face, in this case the rear face, comprises textured zones and alternately polished zones.

The polished and textured surfaces advantageously have a difference in reflectivity. This difference in reflectivity can be used to facilitate the localized deposition of metal grids, for example by screen printing.

The method of producing a heterojunction photovoltaic cell will now be described by way of the following example given by way of nonlimiting illustration.

The method comprises the following successive steps: 1. Texturing of an N-type c-Si substrate in a KOH solution (1% concentration) to form pyramids. 2. Deposition of a stack (i) a-Si: H / (p) a-Si: H on a textured face of the substrate to form the emitter. The amorphous silicon layers are deposited by PECVD (temperature: 180-200 ° C., pressure 0.8-1.5 Torr). The thickness of the intrinsic silicon layer is between 3 and 10 nm and the thickness of the doped amorphous layer is between 3 and 30 nm. 3. Localized deposit of a sacrificial SiO2 layer by PECVD (temperature 180-200 ° C, pressure: 0.8-1.5 Torr). The layer obtained has a thickness ranging from 50 nm to 1000 nm. 4. Engraving the unprotected part of the emitter with a concentrated solution of KOH (20%) to release a part of the surface of the substrate. 5. Polishing of the surface freed from the substrate by a concentrated solution of KOH (20%) to form a flat area. 6. Deposition of the BSF stack: (i) a-Si: H / (n) a-Si: H. The stack is deposited by PECVD with the same operating conditions as for stage 2. The thickness of the doped amorphous silicon layer is between 5 nm and 50 nm, after deposition and before being etched. 7. Engraving of the BSF layer with a solution of low concentration of KOH (1%) until the BSF layer is completely etched at the level of the textured and partial zone on the plane part (reduction of the initial thickness until at the desired value, between 3 nm and 30 nm). 8. Complete etching of the SiO2 layer with a low concentration HF solution (5%). 9. Full plate deposition of a conductive ITO layer by sputtering (temperature: about 200 ° C., pressure 1.5 × 10 -3 Torr). The thickness of the deposited ITO layer is between 50 nm and 250 nm. 10. Deposition of an insulating paste at the level of the textured area and the flat area. 11. Etching of ΙΊΤΟ unprotected by the insulating paste with a solution of HCl or HF. 12. Etching the insulation paste with an alkaline solution (KOH). 13. Realization of the electrical contacts of the cell on the rear face by screen printing.

This method is simple to implement and makes it possible to easily produce thin film patterns on substrates. It is advantageously used to produce emitter / BSF units of an RCC-HIT cell.

The method of realization comprises steps using selective chemistries to etch certain localized areas of the rear face of the photovoltaic cell in order to texture or polish them.

The method can also be used to form patterns on the front face of a silicon substrate for manufacturing solar cells with different structures.

The production method has been described for a photovoltaic cell comprising a silicon heterojunction.

The process could be applied for other materials. The heterojunction could be any other suitable material such as Group III-V compound semiconductors or metal oxides. It could be, for example, a junction like CdS / CdTe or based on organic materials such as PEDOT / PSS (Poly (3,4-ethylenedioxythiophene) poly (styrenesulfonate)), or even copper di-selenide. indium or gallium arsenide.

Claims (16)

claims 1. A method for producing a heterojunction photovoltaic cell, characterized in that it comprises the following successive steps: a) providing a crystalline silicon substrate (1) comprising a main surface provided with at least one textured zone (2a) covered with a first layer (4) having a first conductivity type p or n (4) and a flat area (2b), b) forming a second layer (3) having a second type of conductivity n or p, opposite to first type of conductivity p or n, simultaneously with the surface of the textured zone (2a) covered with the first layer (4) and on the surface of the plane zone (2b) of the main face, c) etch the second layer ( 3), in that at the end of step b), the portion of the second layer deposited on the surface of the textured zone (2a) covered with the first layer has a thickness and less than the thickness ep. the part of the second layer deposited on the surface of the a planar zone (2b), so that at the end of the etching step c), only the part of the second layer (3) deposited on the surface of the plane zone (2b) is preserved, and the substrate (1) forms a p / n junction with the layer selected from one of the first and second layers (3, 4) and has a conductivity type opposite to that of the substrate. 2. Method according to claim 1, characterized in that the first layer (4) and the second layer (3) are amorphous silicon. 3. Method according to one of claims 1 and 2, characterized in that the textured zone (2a) is in the form of pyramids, the pyramids having a height of 2pm to 20 / im. 4. Method according to any one of claims 1 to 3, characterized in that the ratio of thicknesses ep / and ranges from 1.5 to 2. 5. Method according to any one of claims 1 to 4, characterized in that the thickness of the second layer (3) deposited on the plane region (2b) is between 5nm and 50nm, before the etching step. 6. Method according to any one of claims 1 to 5, characterized in that, before the deposition of the second layer of a second conductivity type (3), the first layer of a first conductivity type (4) is covered with a sacrificial barrier layer (5, 5 "), the first layer (4) being disposed between the crystalline silicon substrate (1) and the sacrificial barrier layer (5, 5"). 7. Method according to claim 6 characterized in that the substrate (1) provided in step a) is obtained according to the following steps: i '. depositing a layer of a first type of conductivity (4) on a fully textured face of a substrate (1), iî !, depositing a sacrificial barrier layer (5) on the layer (4), the sacrificial barrier layer (5) ) having a thickness between 50nm and 1pm, they 'etch the sacrificial barrier layer (5) and the layer (4), so as to release a portion of the textured face of the substrate, iv !. polishing the released portion of the substrate face to form a planar area (2b). 8. Method according to claim 6, characterized in that the substrate (1) provided in step a) is obtained according to the following steps: I. depositing a first sacrificial barrier layer (5!) On a completely planar face of a substrate (1), II. removing a portion of the first sacrificial barrier layer (5!) to release a portion of the planar face of the substrate (1), Iii. forming a textured area (2a) on the released portion of the face of the substrate (1), IV. completely removing the first sacrificial barrier layer (5 '), so as to release the plane area (2b) of the substrate, V. successively depositing a layer of a first conductivity type (4) and a second sacrible barrier layer (5 " ) on the textured zone (2a) and on the plane area (2a) of the main face of the substrate (1), the second sacrificial barrier layer (5 ") completely covering the layer (4) of the first conductivity type, the second sacrificial barrier layer (5 ") having a thickness between 50nm and Ιμπι, VI. locally etching the second sacrificial barrier layer (5 ") and the layer (4), so as to release the flat area (2b) of the main face of the substrate (1). 9. Method according to any one of claims 7 and 8, characterized in that, after step c) of etching the second layer (3), the sacrificial barrier layer (5, 5 ") is removed. 10. Method according to any one of claims 1 to 9, characterized in that the layer of a first conductivity type (4) has a thickness of between 6nm and 3Qnm. 11. Method according to any one of claims 1 to 10, characterized in that the substrate (1) made of crystalline silicon is of the first type of conductivity of the second type of conductivity. 12. Method according to one of claims 1 to 11, characterized in that the method comprises the following additional steps: depositing a conductive transparent oxide layer (6) on the first first conductivity layer (4) and on the second second conductivity layer (3); - forming electrical contacts (8) on the conductive transparent oxide layer (6). 13 = Method according to claim 12, characterized in that, before the formation of the electrical contacts (8), the method comprises the following steps: - depositing an insulating paste (7) on the first first conductivity layer (4) and on the second layer of second conductivity (3), the conductive transparent oxide layer (6) separating the insulating paste (7) from the layers (3, 4), etching the conductive transparent oxide layer (8) so as to separate the conductive transparent oxide layer (6) in two distinct parts, the first part being electrically connected to the first first conductivity layer (4) and the second part being electrically connected to the second second conductivity layer (3), - etching the insulating paste (7). 14, A method for producing a heterojunction photovoltaic cell comprising the following successive steps: a ') providing a crystalline silicon substrate (1) comprising a main face provided with at least one textured zone (2a) covered with a first layer of a first conductivity type (4) and a flat area (2b) covered with a second layer of a second conductivity type (3), the substrate (1) forming a p / n junction with the first layer (4) or with the second layer (3), b ') forming a conductive transparent oxide thin layer (6) simultaneously on the textured area (2a) and on the flat area (2b) of the main face, the thin layer deposited on the textured zone (2a) having a thickness and less than the thickness ep> of the thin layer deposited on the plane zone (2b), c ') etching the conductive transparent oxide thin film (6) simultaneously on the plane zone (2b) and on the textured zone (2a), so leaving only a portion of the conductive transparent oxide thin layer (6) on the flat area (2b). 15. The method of claim 14, characterized in that the extured zone (2a) covered with the layer of a first conductivity type (4) is laminated between two plane areas (2b, 2b '), 3S planar areas (2b , 2b ') being covered with a layer of a second type of inductivity (3). 6. Method according to one of claims 14 and 15, characterized in that the sracédé comprises an additional step, before the etching step c '), in which a dough (7) is deposited on the transparent oxide layer: waving element (6) so as to cover part of the textured area (2a). 7. Method according to claim 16, characterized in that, after the etching step c '), the electrically insulating paste (7) is removed and in that an electric contact (8) is deposited on the layer transparent oxide "nducer (6) at the textured area (2a).