EP2801116A2

EP2801116A2 - Photovoltaic cell and manufacturing process

Info

Publication number: EP2801116A2
Application number: EP13704145.5A
Authority: EP
Inventors: Thibaut Desrues; Sylvain DE VECCHI; Florent Souche
Original assignee: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Current assignee: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date: 2012-01-05
Filing date: 2013-01-03
Publication date: 2014-11-12
Also published as: WO2013102725A2; FR2985608B1; KR20140112537A; FR2985608A1; WO2013102725A3; JP2015506584A; US20140373919A1

Abstract

The invention relates to a photovoltaic cell comprising a semiconductor substrate (1) of a first conductivity type equipped with a main side, a first layer (2) made of an amorphous semiconductor of the first conductivity type making contact with the main side of the substrate (1), a first electrical contact (3) formed on the first amorphous layer (2), a second layer (4) made of an amorphous semiconductor of a second conductivity type making contact with the main side of the substrate (1), a second electrical contact (5) formed on the second amorphous layer (4), and an electrically insulating layer (6), the cell being characterised in that the electrically insulating layer (6) is formed fully on the first amorphous layer (2), and in that the first and second contacts (3, 5) extend over the electrically insulating layer (6).

Description

Photovoltaic cell and method of production

Technical field of the invention

The invention relates to a photovoltaic cell.

The invention also relates to a method for producing a photovoltaic cell.

State of the art

In the field of photovoltaic cells, the research focuses mainly on improving the conversion efficiency of the cell, for example by reducing the recombination of photogenerated charge carriers and / or by reducing the resistive losses, and on the simplification of the process realization of photovoltaic cells.

Conventionally, a photovoltaic cell is formed by a diode, for example, a p / n type junction made of a semiconductor material such as silicon. The diode then comprises a zone doped with a p-type impurity, for example boron, and a zone doped with an n-type impurity, for example phosphorus. In order to improve the conversion efficiency of the photovoltaic cells, different architectures have been proposed.

In the first place, cells with heterojunctions of silicon combine a crystalline silicon substrate, c-Si, associated with ultra-thin layers of amorphous silicon a-Si: H, deposited to form junctions with crystalline silicon. The gap energy of a-Si: H (1, 5eV <E _G <1, 9eV) is more higher than that of c-Si (1, 12eV). The first developments of heterojunction cells were performed on structures where only the emitter consisted of a film of a-Si: H, with interesting yields. Research has also been conducted to improve the collection of electron-hole pairs, the Back Surface Field configuration in English or BSF is advantageous. This field improves the electrical characteristics of the solar cell, in particular the open circuit voltage by reducing the dark current. In fact, porters who become minority after their injection into the rear zone move away from the depletion zone. The rear electric field "BSF" pushes them towards the junction.

Finally, new architectures have been proposed to release the collection surface, the front surface. The rear contact cells, in English "Rear Contact Cell" RCC, make it possible to have the emitter and BSF zones located on the rear face and thus to avoid the shadowing due to the metallization of the front face. Heterojunction cell architectures, and particularly double heterojunction cells with an a-Si: H backbone transmitter and BSF, are described in US 7, 199,395 and US 2004/0043528.

These architectures are, moreover, relatively long to implement and present risks of poor performance.

Indeed, the spaces and overlaps of the different layers of the photovoltaic cell impose tolerances in the geometry of the masks and in the alignments between the deposits to avoid short circuits. For example, it is a question of having a good alignment between the different levels of layers made on the substrate. Thus, the more the geometry of the rear face is complex and the more it requires locating steps. At each location step is added a tolerance, which increases the width of the device and can reduce its performance. There remains a need to develop a photovoltaic cell of simple geometry on the rear face to obtain high conversion efficiencies.

Object of the invention

The invention relates to a photovoltaic cell whose structure is compact while facilitating the formation of contacts to maintain good yields.

The invention also relates to a method for producing a photovoltaic cell that is robust, easy to implement and that allows a reduction in the number of technological steps. This object is approached by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS Other advantages and features will emerge more clearly from the following description of particular embodiments of the invention given by way of nonlimiting example and represented in the accompanying drawings, in which: FIG. , schematically, in section, a photovoltaic cell,

FIG. 2, 3 and 4 represent, schematically, in section, a photovoltaic cell being developed,

- Figure 5 schematically shows the photovoltaic cell seen from above. Description of a preferred embodiment of the invention

As illustrated in FIG. 1, the photovoltaic cell comprises a substrate 1 of a first conductivity type provided with a main face. The substrate 1 is crystalline, that is to say mono-crystalline or polycrystalline. The substrate 1 is formed by a semiconductor material, for example a material of the type, IV, such as Si, Ge, an alloy of these materials, a material of the type III-V or II-VI.

It comprises, on its main face, a first amorphous semiconductor layer of the first conductivity type 2 and a second amorphous semiconductor layer of a second conductivity type 4, both in contact with the main face of the substrate 1. The first and second amorphous layers are electrically connected to the substrate 1 so as to form a junction with the substrate and / or to allow the passage of the charge carriers between the amorphous layers and the substrate. The first and / or second amorphous layers can thus have an interface with the substrate. Preferably, the interfaces are steep.

This structure is called heterojunction photovoltaic cell because the two materials that constitute this junction have a different energy band gap (EQ).

The second type of conductivity is opposite to the first type of conductivity.

The heterojunction is preferably between an amorphous material and an identical mono or polycrystalline material. Advantageously, the heterojunction is of the a-Si: H / c-Si type. The substrate may optionally have a passivation layer, for example a layer of Al ₂ O ₃ , thermal SiO ₂ , or any material capable of passivating the surface of c-Si. The properties of the passivation layer are configured to maintain the junction between the substrate and the amorphous layer. The heterojunction is for example made of silicon or any other suitable material, for example a junction like CdS / CdTe or based on organic materials such as PEDOT / PSS (Poly (3,4-ethylenedioxythiophene) poly (styrenesulfonate)). It may also be indium copper di-selenide or gallium arsenide.

The first amorphous layer of the first conductivity type is preferably doped amorphous silicon. Preferably, the first amorphous layer 2 is an n-doped amorphous silicon, a-Si: H Un. Preferably, the first amorphous layer makes it possible to form a rear electric field BSF.

The second amorphous layer of the second conductivity type 4 is preferably p-doped amorphous silicon, a-Si: H i / p. The second amorphous layer forms a junction p / n with the substrate, which makes it possible to recover the current of carriers generated inside the photovoltaic cell. This second amorphous layer can also be called transmitter. The photovoltaic cell also has, on its main face, a first electrical contact 3 formed on the first layer and a second electrical contact 5 formed on the second layer. The electrical contact materials are electrically conductive, such as aluminum and / or ΙΊΤΟ. Preferably, the interfaces between the electrical contacts and the amorphous materials are abrupt or formed by means of a silicide.

The photovoltaic cell also comprises, on its main face, an electrically insulating layer 6. The material of the electrically insulating layer 6 is, for example, a silicon oxide, a silicon nitride, a silicon carbide or a type of material. -If: H stoichiometric or not. The material of the electrically insulating layer 6 may also be a stack or a mixture of these latter materials. Preferably, the layer 6 consists of a stack of a low Si layer covered with a Si-rich layer. For example, it is possible to have a first layer of silicon-poor nitride obtained by means of a stream of NH gas. ₃ / SiH ₄ with a ratio between 2 and 10 covered with a second layer of silicon-rich nitride obtained with a gas ratio close to 1, typically less than 2.

The layer 6 may be for example Al 2 O 3 or a stack of oxide or silicon nitride, with a first protective layer poor in Si covered with an absorbent layer rich in Si. This stack has the advantage of being easy to use. engrave.

The layer 6 can for example be produced by plasma-activated vapor deposition PECVD, LPCVD low-pressure chemical vapor deposition, screen-printing or ink-jet.

The electrically insulating layer 6 is integrally formed on the first amorphous layer 2. The electrically insulating layer 6 may interface with the first amorphous layer 2. It has no interface with the substrate 1. Thus, the effect of the rear electric field BSF and the output is increased. In addition, the surface of the second amorphous layer 4 is left free for the contact 5. Advantageously, a better compactness of the photovoltaic cell is obtained. The first and second contacts 3 and 5 respectively extend on the first and second amorphous layers by extending on the electrically insulating layer 6 to increase the active surface of the contacts on the main face without increasing the risk of short circuits. This architecture makes it easy to reduce resistive losses. Advantageously, the other opposite main face is free to optimize the collection surface of the light radiation. The first electrical contact 3 and the second electrical contact 5 are electrically dissociated. The contacts have no interface with the substrate to prevent short circuits and they are preferably formed on the same face of the electrically insulating layer 6.

In a preferred embodiment, part of the second amorphous layer 4 covers the electrically insulating layer 6 and this electrically insulating layer 6 covers part of the first amorphous layer 2. The electrically insulating layer 6 isolates the amorphous layers 2 and 4 different types of conductivity. The performance of the photovoltaic cell is thus improved and the lifetime of the photovoltaic cells is increased. The second amorphous layer 4, electrically connected to the substrate 1, is completely covered by the electrical contacts and more particularly by the second electrical contact 5. It has been observed that a complete or almost complete coverage of the second layer 4 by the second contact 5 makes it possible to increase the electrical performance of the photovoltaic cell, even if the additional contact surface has a negligible effect on the transport of charges. In addition, since the second amorphous layer 4 is completely covered by the electrical contact 5, the layer 4 is protected from the external environment, which makes it possible to increase its lifetime.

By fully covered surface is meant the surface of the layer 4 which has an interface with the substrate 1. This surface must be covered with more than 95% and advantageously 100%. On the other hand, the surface of the layer 4 which has an interface with the insulating layer 6 can only be partially covered by the contact 5. In one embodiment that can be combined with the above, the main surface of the substrate 1 is completely covered by the first amorphous layer 2 and the second amorphous layer 4. This makes it possible to increase the efficiency of the cell by using the entire main surface usable to recover the photogenerated stream or to form the rear surface field. According to a preferred embodiment, only the side faces of the amorphous layers 2 and 4 are in contact. In this architecture, the amorphous layers 2 and 4, connected to the substrate 1, form a junction p / n.

According to one embodiment, to prevent excessive leakage between layers 2 and 4, several solutions are possible. For the layer 4, it is possible to use a stack of a first thin or slightly doped thin layer (1 to 10 nm) coated with a doped layer. It is also possible to locally modify the layer 2 near the layer 4 by doping (p or hydrogen) to make it locally insulating. It is also possible to modify layer 4 locally.

By fully covered surface is meant a surface covered to more than 95% and preferably 100%.

In a particular embodiment, which can be combined with the preceding embodiments, the structure comprises, in a direction perpendicular to the main face, a stack successively comprising the substrate 1, the first amorphous layer 2, the electrically insulating layer 6, the second layer amorphous 4, the electrical contact 5. The contact 5 and the first layer 2 are separated, perpendicularly to the substrate, by the electrically insulating layer 6 and the second layer 4. The shift between the contact 5 and the first layer 2 is defined by the thicknesses of the second layer 4 and the electrically insulating layer 6, and not by means of one or more photolithography steps, which allows a compact architecture.

In addition, this allows a better overlap of the different layers while ensuring maximum coverage of the contacts 3 and 5 on the layers amorphous 2 and 4. This reduces or even eliminates the risk of direct contact between the first amorphous layer 2 and the electrical contact of the second amorphous layer 5.

The electrical contacts 3 and 5 extend above the electrically insulating layer 6 and are electrically dissociated. In a particular embodiment that can be combined with the previous modes, there exists between the two contacts 3 and 5 an electrically insulating groove. The insulating groove is defined between the contacts 3 and 5 and it preferably extends inside the second layer 4 to reduce the risk of leakage when the latter has a portion which is in electrical contact with the first contact 3. even more preferentially, this groove makes it possible to avoid any accumulation of conductive dust during the production process or during the lifetime of the photovoltaic cell, which would make the contact of the first amorphous layer 3 with the second contact in electrical contact. 5.

In a particular embodiment, the photovoltaic cell is formed in the following manner. As illustrated in FIG. 2, it is necessary to provide a substrate 1 comprising a semiconductor material layer of a first conductivity type. The substrate 1 is partially covered by a first pattern comprising a first amorphous layer 2 of the first conductivity type and an electrically insulating layer 6. The electrically insulating layer 6 is separated from the substrate 1 by the first amorphous layer 2. The substrate 1 and the first pattern are covered by a second amorphous layer 4 of a second conductivity type.

To obtain this type of substrate, it is preferable to cover the substrate 1 with an amorphous layer 2 of the first type of conductivity. The layer 2 of the first conductivity type is deposited by any suitable technique, for example an n-doped α-Si: H layer. The first layer 2 may be deposited by plasma-activated vapor deposition PECVD, LPCVD low-pressure chemical vapor deposition or at atmospheric pressure APCVD, for example. The layer of the first conductivity type 2 has, preferably, a thickness of between 5 nm and 50 nm after deposition. This thickness range advantageously makes it possible to properly passivate the surface while avoiding resistive losses in the layers.

This first amorphous layer 2 is covered by an electrically insulating layer 6. Preferably, the first amorphous layer 2 and the electrically insulating layer 6 have the same design and are perfectly aligned, that is to say that the lateral faces 2 and 6 are in continuity with one another. The material of the electrically insulating layer 6 is preferably obtained by means of plasma-enhanced chemical vapor deposition. It is also possible to use plasma assisted atomic layer deposition techniques (ALD, PEALD). It is also possible to deposit materials like AI ₂ O ₃ , the choice is made according to the structure and the constraints present.

The electrically insulating layer 6 preferably has a thickness of between 10 nm and 2000 nm. This thickness range advantageously makes it possible to obtain a good compromise between the thickness, the deposition time and the insulating properties of the layer.

The electrically insulating layer 6 and the first amorphous layer 2 are then etched by means of the same etching mask so as to self-align the pattern formed in the electrically insulating layer 6 and the pattern formed in the first layer 2. The substrate is then partially covered by the first pattern. Part of the surface of the first layer 2 and / or the electrically insulating layer 6 may be etched, preferably by laser irradiation and / or by wet etching, for example.

The amorphous layer 4 of the second conductivity type is then deposited by any suitable technique, for example a p-doped a-Si: H layer deposited by plasma-activated vapor deposition PECVD, low-level chemical vapor deposition. pressure LPCVD or at atmospheric pressure APCVD for example. The amorphous layer of the second conductivity type 4 has, preferably, a thickness of between 5 nm and 50 nm after deposition. This thickness range makes it possible to passively pass the surface while avoiding resistive losses in the layers.

The second layer 4 is deposited in a non-selective manner and it covers the substrate and the first pattern.

The layers 2 and 4 may advantageously consist of a stack of two layers. The first layer, in contact with the substrate, is not or little doped and passive interface. Effective passivation can be achieved by means of a first layer having a thickness of between 1 and 10 nm. The second layer is doped and provides the electric field necessary for the collection of carriers.

The second amorphous layer 4 and the first pattern are then partially etched to release a portion of the first amorphous layer 2, the substrate 1 being left covered by the second amorphous layer 4, as illustrated in FIG. 3. The etching of the second layer amorphous 4 and the electrically insulating layer 6 is made above the first amorphous layer 2, at the left side as shown in Figure 3. The etching stops on the amorphous layer 2 and defines a pad of electrically insulating material extending vertically between the two amorphous layers. Part of the surface of the second amorphous layer 4 and the electrically insulating layer 6 may be etched preferentially by laser irradiation and / or by wet etching, for example. After, as illustrated in FIG. 4, a contact of the first amorphous layer 3 and a contact of the second amorphous layer 5 are formed by means of an electrically conductive material, the two contacts partially covering the electrically insulating layer 6 and being dissociated electrically.

In a particular embodiment, the contacts are formed by deposition of the electrically conductive material on the first amorphous layer 2 and the second amorphous layer 4.

The electrically conductive contacts 3 and / or 5 are deposited by any suitable technique, preferably by spraying, electrochemical deposition, screen printing, evaporation, inkjet. The thickness of the electrical contacts is for example between 1 pm and 50 pm after deposition so as not to cause partial or total depletions of the doped areas or to cause problems of series resistance.

The electrically conductive material 6 is etched to form the two contacts 3 and 5. The second amorphous layer 4 can then be etched above the electrically insulating layer 6 in the extension of the hole formed in the electrically conductive material to release a portion of the electrically insulating layer 6, to electrically dissociate the two contacts 3 and 5 and optionally two parts of the second layer 4. Advantageously, the layer 4 is etched so as to reduce the electrical losses between the contacts 3 and 5. However, given its low conductivity, it can be engraved partially or not engraved.

According to a preferred embodiment and as represented in FIG. 5, according to a view from above, the contacts 3 and 5 have a shape of slot nested one inside the other, the contacts being separated by the layer 6.

The etching of the electrically insulating material 6 is carried out above the second layer 4. During etching, the second layer 4 can be eliminated so as to prevent the contact 3 from being associated with material forming the second layer 4. configuration depends on the extent of the area to be etched and its position above the electrically insulating layer 6.

Preferably, the electrically insulating layer 6 comprises: a first absorbent layer (rich in silicon for example) and a second protective layer (low in silicon for example), the protective layer being in contact with the amorphous layer of first conductivity 2. The laser irradiation then opens the absorbent layer, rich in Si, but does not deteriorate the layer 2 thanks to the protective layer. The latter is then easily etched by the wet route.

The absorbent layer can be easily structured by laser irradiation. Preferably, the absorbent layer will be etched by laser irradiation and the protective layer by chemical etching.

Preferably, the laser etching removes a portion of the absorbent layer, separating the absorbent layer in its middle into two uncontacted portions and leaving free a portion of the protective layer. The protective layer thus serves as a barrier layer for laser irradiation. Thus, a trench is formed in a simple manner in the electrically insulating layer 6.

In the case where the etching of the electrically insulating layer 6 goes to the first amorphous layer 2, the electrically insulating layer being totally etched in its thickness, there are two elementary patterns of the electrically insulating layer 6, one of which is used by the substrate stack 1 / first amorphous layer 21 electrically insulating layer 6 / second amorphous layer 4 / electrical contact 5.

Preferably, the electrically insulating layer 6 is not completely etched so as to leave a space between the contacts 3 and 5 and protect the layer 2.

The etching of the second amorphous layer 4, the electrically conductive material and / or possibly part of the electrically insulating layer 6 can be carried out in a single step, preferably by laser irradiation.

As the etching is performed above the electrically insulating layer 6, it is sufficient to align the laser above this layer. One of the side faces of the second amorphous layer 4 and the contact 5 are thus self-aligned to have a complete or almost complete coverage of the second layer 4 by the contact 5. The contacts 3 and 5 are separated by the same distance above the electrically insulating layer 6. There is therefore no short circuit between the contacts 3 and 5.

The photovoltaic cell thus has low tolerance values for technological steps requiring alignments and can achieve high efficiency while limiting the risk of short circuits.

In order that the photovoltaic cell can be implemented by means of a robust manufacturing method, easy to implement and which ensures rates compatible with an industrial implementation, it is advantageous to carry out the laser irradiation etching. The laser irradiation will preferably be carried out with a wavelength of less than 600 nm, a fluence of between 0.01 J / cm 2 and 10 J / cm 2, a frequency of between 10 kHz and 10,000 kHz and a pitch of between 1 μm and 100 μm. Preferably, the laser irradiation is used to etch at once a part of the electrically insulating layer 6, a part of the second amorphous layer 4 and the electrical contacts 3 and 5. In another embodiment, at least a part of engravings can also be made by wet etching. The duration is 2 minutes and the etching solution is 2% HF.

The electrically insulating layer provides the mask function, which simplifies this process by reducing the number of steps necessary for the realization of the photovoltaic cell and by using easily industrializable techniques, such as laser irradiation or chemical etching, unlike more conventional techniques and more difficult to industrialize, such as photolithography, metal masks or screen printing for example.

Layers 2 and 4 have been presented as amorphous layers to form a double heterojunction cell, but another crystal structure may be employed for one and / or the other. Those skilled in the art will keep in mind that additional steps of localization of the different layers described above are possible, for example to modify the extent of the second layer 4 on the electrically insulating layer 6, or to form a spacer on the edges of the pattern in materials 2 and 6.

According to a particular embodiment, the layers 2 and 4 can be inverted, for example, if the area of the layer 2 covered by the layer 6 is very narrow, less than 10μιη.

Claims

claims

Photovoltaic cell comprising:

a semiconductor substrate of a first conductivity type (1) provided with a main face,

a first amorphous semiconductor material layer (2) of the first conductivity type in contact with the main face of the substrate (1),

a first electrical contact (3) formed on the first amorphous layer (2),

a second layer of amorphous semiconductor material (4) of a second conductivity type in contact with the main face of the substrate (1).

a second electrical contact (5) formed on the second amorphous layer (4) and

an electrically insulating layer (6),

characterized in that the electrically insulating layer (6) is integrally formed on the first amorphous layer (2) and the first and second contacts (3,5) extend over the electrically insulating layer (6).

2. Photovoltaic cell according to claim 1, characterized in that the second amorphous layer (4) is completely covered by the electrical contact (5) and covers the insulating layer (6).

3. Photovoltaic cell according to any one of claims 1 to 2, characterized in that the second amorphous layer (4), electrically connected to the substrate (1), is completely covered by the second electrical contact (5).

4. Photovoltaic cell according to any one of claims 1 to 3, characterized in that the main surface of the substrate (1) is entirely. covered by the first amorphous layer (2) and the second amorphous layer (4).

5. Photovoltaic cell according to any one of claims 1 to 4, characterized in that the electrically insulating layer (6) comprises a first absorbent layer and a second protective layer.

6. Photovoltaic cell according to claim 5, characterized in that the absorbent layer of the electrically insulating layer (6) is separated in its middle in two parts not contacted, leaving free a portion of the protective layer.

7. Photovoltaic cell according to any one of claims 1 to 6, characterized in that it comprises at least one stack successively comprising the substrate (1), the first amorphous layer (2), the electrically insulating layer (6), the second amorphous layer (4), one of the electrical contacts (3,5) in a direction perpendicular to the main face.

8. A method of producing a photovoltaic cell, characterized in that it comprises the following steps:

- Providing a substrate (1) having a semiconductor material layer of a first conductivity type, the substrate (1) being partially covered by a first pattern comprising a first amorphous layer (2) of the first conductivity type and an electrically layer insulating (6), the electrically insulating layer (6) being separated from the substrate (1) by the first amorphous layer (2), the substrate (1) and the first pattern being covered by a second amorphous layer (4) of a second conductivity type,

- Partially etching the second amorphous layer (4) and the first pattern to release a portion of the first amorphous layer, a portion of the substrate (1) being left covered by the second amorphous layer (4),

Forming a first contact (3) of the first amorphous layer (2) and a second contact (5) of the second amorphous layer (4) by means of an electrically conductive material, the two contacts (3,5) partially covering the electrically insulating layer (6) and being electrically dissociated.

Method according to claim 8, characterized in that the first and second contacts (3,5) are formed by:

- Deposition of the electrically conductive material on the first and second amorphous layers (2,4),

- Etching the electrically conductive material and the second amorphous layer (4) on the electrically insulating layer (6) to release a portion of the electrically insulating layer (6) and electrically dissociate the two contacts (3,5).

Method according to claim 9, characterized in that, the electrically insulating layer (6) having a protective layer and an absorbing layer, the etching is carried out by laser irradiation and removes only part of the absorbent layer, separating into two parts not contacted the absorbent layer and leaving free a portion of the protective layer.