TW201537757A - Solar cell and method for manufacturing such a solar cell - Google Patents

Abstract

A solar cell includes a semiconductor substrate, that has a front side surface for receiving radiation and a back-side surface provided with a first junction structure in a first area portion of the substrate and with a second junction structure in a second area portion of the substrate. The second area portion borders on the first area portion. The first junction structure includes a first conductivity type semiconductor layer covering the first area portion. The second junction structure includes a second conductivity type semiconductor layer covering the second area portion. The second conductivity type semiconductor layer of the second junction structure partially overlaps the first conductivity type semiconductor layer of the first junction structure, with the overlapping portion of the second conductivity type semiconductor layer being above a portion of the first conductivity type semiconductor layer while separated by a first dielectric layer therebetween. The portion of the first conductivity type semiconductor layer under the overlapping portion of the second conductivity type semiconductor layer is in direct contact with the semiconductor surface of the substrate.

Description

Solar cell and method of manufacturing solar cell

The invention relates to a solar cell. Further, the present invention relates to a method of manufacturing the solar cell.

Solar cells with back-side contacts are known in the art. In such solar cells, the contact layer has been placed substantially completely on the back side of the solar cell substrate. In this manner, the front side region of the solar cell that can collect the radiant energy can be maximized.

On the back side, the contact structure is used to collect photogenerated charge carriers from the back of the cell.

Such contact structures may include interdigitated p-type and n-type heterostructure junctions (heterojunctions).

For example, solar cells of this type are known to be disclosed in US 2008/0061293 having a heterojunction and an inter-finger structure. Such a semiconductor device includes a first type on at least one surface of a crystalline semiconductor substrate At least one first amorphous semiconductor region doped by the electrical conductor. The semiconductor substrate includes at least one second amorphous semiconductor region doped with the second type conductor on the same at least one surface, and the second type conductor is opposite to the conductivity type of the first type conductor. The first amorphous semiconductor region and the second amorphous semiconductor region form an interdigitated structure, and the first amorphous semiconductor region is insulated from the second amorphous semiconductor region by at least one dielectric region in contact with the semiconductor substrate.

A disadvantage of such a semiconductor device is that the dielectric region cannot collect light to generate carriers. In addition, the dielectric region needs to be well passivated. Furthermore, the fabrication of such patterned dielectric regions requires an additional process step that increases the cost of the solar cell.

In addition, in the case where the semiconductor layer includes amorphous germanium, since most of the passivation dielectric is deposited at a relatively high substrate temperature, the relatively high substrate temperature is deteriorated by the amorphous germanium layer. The passivation layer is such that deposition of the passivation dielectric layer is typically limited prior to deposition of the semiconductor layer. This deposition sequence means that the dielectric needs to be removed over the surface portion of the semiconductor layer to be deposited, which increases the additional risk of surface damage or contamination and thus degrades the quality of the solar cell.

WO 2012/014960 A1 discloses a process for fabricating a back contact solar cell in which a second semiconductor layer is formed to cover the first major surface. A portion of the second semiconductor layer on the insulating layer is partially removed by etching using a first etchant having an etch rate for the second semiconductor layer greater than the insulating layer. The second semiconductor layer is etched using a second etchant having an etch rate higher than that of the second semiconductor layer for the insulating layer to remove a portion of the insulating layer, thereby exposing the first semiconductor region. Furthermore, WO 2012/014960 discloses "using a semiconductor located below the insulating layer The layer serves as an n-type amorphous semiconductor layer. Next, the p-side electrode is formed substantially entirely on the p-type amorphous semiconductor layer. For this reason, it is easy to collect holes with a small number of carriers to the p-side electrode. "."

It is an object of the present invention to provide a solar cell and a method of manufacturing the same that overcomes the shortcomings of the prior art.

The foregoing object is achieved by a solar cell including a semiconductor substrate. The semiconductor substrate has a front side surface for receiving radiation and a back side surface configured with a first junction structure and a second junction structure, the first junction structure being located in the first region portion of the substrate, and the second junction structure Located in the second region portion of the substrate. The second area portion borders the first area portion. The first junction structure includes a first conductive type semiconductor layer covering the first region portion. The second junction structure includes a second conductive type semiconductor layer covering the second region portion. The second conductive type semiconductor layer of the second junction structure partially overlaps the first conductive type semiconductor layer of the first junction structure. The overlapping portion of the second conductive type semiconductor layer is over the portion of the first conductive type semiconductor layer while being separated by the first dielectric layer therebetween. A portion of the first conductive type semiconductor layer under the overlapping portion of the second conductive type semiconductor layer directly contacts the semiconductor surface of the substrate, wherein the second conductive type semiconductor layer in the second region portion is adjacent to the first conductive type in the first region portion a semiconductor layer, and the second conductive type semiconductor layer in the second region portion is adjacent to an overlapping portion of the first conductive type semiconductor layer and the second conductive type semiconductor layer.

Direct contact herein means that the surface of the portion of the first conductive type semiconductor layer is located on the surface of the substrate of the semiconductor without having an electrically insulating layer therebetween.

Bordering or immediate bordering herein means that the second region portion is adjacent or closest to or abuts the first region portion and does not have an intermediate dielectric material between the portions of the region.

Advantageously, the present invention provides the following aspects and advantages in that the first and second junction structures are directly adjacent without a gap therebetween, thereby maximizing the area for collecting light generating charge carriers. Furthermore, by placing only the first and second conductive semiconductor layers on the semiconductor of the substrate without including the first dielectric layer on the substrate between the first and second junction regions, a better A passivation layer that reduces the recombination effect and improves the efficiency of the solar cell. In addition, in the case where the semiconductor layer includes amorphous germanium, since most of the deposition of passivation dielectrics is performed at a relatively high substrate temperature, the relatively high substrate temperature is deteriorated by amorphous. The passivation layer produced by the germanium layer, so the deposition of the passivation dielectric layer is typically limited prior to deposition of the semiconductor layer. This deposition sequence means that the dielectric needs to be removed on the surface portion where the semiconductor layer is to be deposited, which increases the additional risk of surface damage or contamination and thus degrades the quality of the solar cell. The present invention eliminates the need for surface passivating dielectrics and therefore greater flexibility in the choice of deposition temperature of the material and dielectric layer.

The present invention allows for very beneficial manufacturing latitude in defining the first and second region portions. While solar cells can be fabricated using any suitable high pattern definition accuracy of the present invention, the present invention also allows for fabrication such as pattern accuracy of less than 10 microns. Poor or worse solar cells. In contrast, for conventional solar cell fabrication, such low accuracy tends to cause battery efficiency losses such as by causing shunts, or increasing series resistance, or residual unpassivated substrate regions.

In addition to using a semiconducting layer to substantially completely cover the surface, the present invention allows the dielectric layer to be used for pattern definition (e.g., as a mask or termination layer during etching) and for isolation. This dual function reduces costs and saves process steps.

In the aspect of the invention, the first junction structure includes a first tunnel barrier layer, and the first tunnel barrier layer is disposed on the first conductive semiconductor layer and And between the substrates; and/or wherein the second junction structure comprises a second tunneling barrier layer, the second tunneling barrier layer being disposed between the second conductive semiconductor layer and the substrate.

In the aspect of the present invention, in the aspect of the solar cell, at least one of the first junction structure and the second junction structure includes an epitaxial Si layer, and the first conductive semiconductor layer is epitaxial The tantalum layer and/or the second conductive type semiconductor layer is an epitaxial layer.

In the aspect of the invention, the interface of the solar cell, wherein the interface between the first conductive semiconductor layer and the surface of the substrate overlaps is a void of the dielectric layer.

In the aspect of the invention relating to the solar cell described above, wherein the first conductivity type is a p-type, the first conductivity type semiconductor layer comprises a p-type doped amorphous hydrogen hydride (p+ a-Si:H), and A dielectric layer includes yttrium hydrogen hydride (SiNx:H).

In the aspect of the present invention relating to the above solar cell, the first connection The face structure includes an additional first conductive layer or layer stack on top of the first conductive semiconductor layer.

In the aspect of the invention, the additional first conductive layer is a metal layer, or the layer stack comprises a conductive oxide layer and an amorphous semiconductor layer, the amorphous semiconductor layer is disposed on the conductive oxide layer and the first conductive layer On top of the stack of semiconductor layers.

In a preferred aspect of the invention, the second junction structure comprises an additional second conductive layer or layer stack on top of the second conductivity type semiconductor layer.

In the aspect of the invention, the second conductive layer is a metal layer, or the layer stack includes a conductive oxide layer and an amorphous semiconductor layer, and the amorphous semiconductor layer is disposed on the conductive oxide layer and the second conductive layer. On top of the stack of semiconductor layers.

In the aspect of the invention, the material of the first conductive type semiconductor layer includes an intrinsic amorphous germanium layer or a tunneling barrier layer, and a doped layer. The doped layer is selected from the group consisting of a first type doped amorphous germanium, a first type doped germanium-carbon mixture, a first type doped germanium-tellurium alloy, a first type doped epitaxial growth crystal germanium, and a first One of a group of doped polysilicon groups.

In the aspect of the invention, the second conductive type semiconductor layer is selected from the group consisting of a second type doped amorphous germanium, a second type doped germanium-carbon mixture, and a second type. One of a group of doped ytterbium-rhenium alloys, second type doped epitaxially grown crystalline germanium, second type doped poly germanium, and another semiconductor.

In the aspect of the invention, the first dielectric layer is selected from the group consisting of tantalum nitride, hafnium oxide, hafnium oxynitride, dielectric organic compound, dielectric metal oxide or One of a group of dielectric metal nitrides.

In the aspect of the invention, the first junction structure includes a first tunneling barrier layer, and the first tunneling barrier layer is disposed between the first conductive semiconductor layer and the substrate; / or wherein the second junction structure comprises a second tunneling barrier layer, the second tunneling barrier layer being disposed between the second conductive semiconductor layer and the substrate.

Further, the present invention relates to a method of manufacturing a solar cell from a semiconductor substrate having a front side surface for receiving radiation, and a back side surface configured with a first junction structure and a second junction structure, the first connection The face structure is located in the first region portion of the substrate, the second junction structure is located in the second region portion of the substrate, and the second region portion is adjacent to the first region portion. The method includes: depositing a first conductive type semiconductor layer on a back side surface of a substrate above at least a first region portion; selectively depositing a conductive layer; depositing a first dielectric layer at least over the first conductive type semiconductor layer; Forming the first dielectric layer to define the first region portion and exposing the second region portion by covering the first conductive type semiconductor layer in the first region portion; using the patterned first dielectric layer as a mask pair first The conductive semiconductor layer is patterned to generate a first junction structure in the first region portion and expose a surface of the germanium substrate in the second region portion; depositing a portion on the back side surface and the exposed second region portion A second conductive semiconductor layer, the second conductive semiconductor layer being over at least a portion of the first dielectric layer adjacent to the second region portion. In this manner, the second conductive type semiconductor layer of the second junction structure and the first conductive type semiconductor layer portion of the first junction structure Overlying the ground, the overlapping portion of the second conductive semiconductor layer is over the portion of the first conductive semiconductor layer while being separated by the first dielectric layer therebetween, and the overlapping portion of the second conductive semiconductor layer A portion of the lower first conductivity type semiconductor layer directly contacts the semiconductor surface of the substrate.

In the case where the selectively deposited conductive layer is a conductive oxide, the intrinsic amorphous germanium layer may be used in place of the following dielectric layer.

The first conductivity type may be equal to or opposite to the conductivity type of the semiconductor substrate.

The method of the present invention allows a self-aligned formation of the edge of the first conductive type film layer and the edge of the first dielectric layer to maximize coverage of the active layer (first or second conductive type semiconductor layer) The substrate area simultaneously improves the isolation between the two semiconductor layers.

Further, the above method facilitates the use of the first dielectric layer for separating the first and second conductive type semiconductor layers, and for covering the first conductive type semiconductor layer during deposition of the second conductive type semiconductor layer. This covering can prevent thermal degradation of the passivation layer generated by the first conductive type semiconductor layer during deposition of the second conductive type semiconductor layer. It is known that this degradation occurs in the p-doped a-Si:H layer during the deposition of the n-doped a-Si:H layer.

In one aspect, the method further provides the step of depositing a mask layer over the second conductive semiconductor layer, the mask layer covering at least a portion of the second region portion and the (adjacent) first region portion, and then the mask layer Patterning is performed; and the patterned mask layer is used to locally remove the second conductive type semiconductor layer.

Alternatively, the second conductive can be etched by a direct method The type of semiconductor layer, the direct method is, for example, printing an etchant in a desired pattern.

Alternatively, the second conductive type semiconductor layer may be used as a mask to remove the first dielectric layer. This will make these layers self-aligned. Advantageously, the above method allows the self-aligned form of the edges of the first conductive type film layer and the second conductive type film layer and the edges of the first dielectric layer to maximize the exposure of the first and second conductive type semiconductor layers. The area is used to coat the metal layer while ensuring insulation between the two layers.

In one aspect of the method, the method further includes: depositing a mask layer over the second conductive semiconductor layer, the mask layer covering at least the second region portion and the portion of the first region portion; patterning the mask layer; Patterning the second conductive semiconductor layer using the patterned mask layer as a mask to create a patterned second junction structure in the second region portion, the second junction structure patterning such that the second conductive semiconductor layer Adjacent and partially overlapping the first conductive semiconductor layer, the overlapping portion of the second conductive semiconductor layer is on top of the first conductive semiconductor layer and separated by the first dielectric layer.

As one aspect of the method, a first junction structure configured with a first tunneling barrier layer is disposed, the first tunneling barrier layer being disposed between the first conductive semiconductor layer and the substrate; and/or wherein The second junction structure is provided with a second tunneling barrier layer, and the second tunneling barrier layer is disposed between the second conductive semiconductor layer and the substrate.

In the aspect of the method, at least one of the first junction structure and the second junction structure comprises an epitaxial layer, the first conductive semiconductor layer is an epitaxial layer and a substrate, and/or the second conductive The type semiconductor layer is an epitaxial layer.

In an aspect of the method as described above, the first conductivity type is p-type, the first guide The electro-type semiconductor layer includes p-type doped amorphous lanthanum hydride (p+ a-Si:H), and the first dielectric layer includes lanthanum hydride (SiNx:H), and the SiNx:H layer covers the p+ a -Si: H layer.

The preferred embodiment is further defined by the accompanying items.

1, 2, 3‧‧‧ solar cells

5‧‧‧Substrate

10‧‧‧First Conductive Semiconductor Layer

10a, 10b‧‧‧ tunneling barrier

11‧‧‧ patterned first conductive semiconductor layer

15‧‧‧ Conductive layer

20‧‧‧First dielectric layer

21‧‧‧ patterned first dielectric layer

22, 37‧‧‧ dielectric layer

25‧‧‧Second conductive semiconductor layer

26‧‧‧ patterned second conductive semiconductor layer

27‧‧‧resist pattern

30, 50‧‧ ‧ cover layer

31‧‧‧ patterned mask

34, 35‧‧‧ metal layer

36‧‧‧ gap

40‧‧‧Second conductive layer

45‧‧‧ patterned second conductive layer

55‧‧‧Protected dielectric body

A‧‧‧First Area Section

B‧‧‧Part II section

C‧‧‧Part III

D‧‧‧ overlap

E, F‧‧‧ border

S‧‧‧ interval

The invention will be explained in more detail with reference to the drawings which illustrate some exemplary embodiments. These drawings are for illustrative purposes only and are not limiting of the inventive concepts defined by the scope of the claims. In the drawings: Figures 1a to 1c show cross-sectional views of a solar cell after the first manufacturing step.

2 is a cross-sectional view showing the solar cell after the subsequent process step.

3 is a cross-sectional view showing a solar cell semiconductor substrate after the initial patterning step.

4 is a cross-sectional view showing a solar cell semiconductor substrate after the patterning step of the first semiconductor layer is completed.

5a and 5b are cross-sectional views showing the solar cell after the subsequent process step.

Figure 6 is a cross-sectional view of the solar cell after deposition of the mask layer.

Figure 7 is a cross-sectional view of the solar cell after the subsequent patterning step.

FIG. 8 is a cross-sectional view showing the solar cell after the etching step.

9a to 9c are cross-sectional views showing the solar cell after the subsequent process step.

10a to 10e are cross-sectional views showing a solar cell after the metallization step.

11a to 11c are cross-sectional views of a solar cell according to another embodiment.

Figure 12 is a cross-sectional view showing a solar cell according to another embodiment after the continuation step.

Figure 13 is a cross-sectional view showing the solar cell after removing the second mask layer.

Figure 14 is a cross-sectional view showing the solar cell after the subsequent manufacturing steps.

In the following figures, the same component symbols in the various figures refer to similar or identical components.

Solar cells include a semiconductor substrate, which is typically a germanium wafer. Such a wafer may be polycrystalline or single crystal.

At least the front side of the wafer can be textured, and the wafer can be configured with a front side passivation by, for example, a front diffusion layer and a front passivation coating. An anti-reflective coating may also be disposed on the front side of the wafer. The front side texture and coating can also be provided during subsequent processing. The front side may also be provided with a sacrificial layer that provides protection for some of the processes described below.

Figure 1a is a cross-sectional view of the semiconductor substrate 5 after the first process step in the fabrication process. In this step, the first conductive type semiconductor layer 10 is deposited over at least a first portion of the surface of the substrate 5. The first conductive type semiconductor layer will form a first junction with the surface of the semiconductor substrate.

The material of the first conductive type semiconductor layer may be selected from the group consisting of a first type doped amorphous hydrogen-rich germanium (a-Si:H), a first type doped microcrystalline germanium, and a first type doped amorphous germanium-carbon mixture. , the first type doped yttrium-tellurium alloy, the first type doped epitaxial growth crystallization, the first type Doped in groups of polysilicon or other semiconductors. Further, the first conductive type semiconductor layer may include a stack of intrinsic semiconductor layers and first type doped semiconductor layers (materials selected from the above), which are, for example, heterojunctions having intrinsic thin layers known in the prior art. Face (HIT structure).

The first conductive type film layer may further include a surface layer of the substrate, which is generated by diffusion or implantation into the substrate, and the doping of the substrate may be partial or subsequent may be the first region portion A (please refer to FIG. 3 Etch-back on the outside.

The portion of the first region that is covered is at least equal to the region where the first junction is to be created.

Optionally, in an embodiment, the first junction and/or the second junction may comprise a metal-insulator-semiconductor (MIS) junction.

1b is a cross-sectional view of the semiconductor substrate after the first fabrication step. In this case, the first conductive semiconductor layer is covered by the conductive layer 15, and the conductive layer 15 serves as a collector layer and/or a parallel conductor. Improve current extraction and/or current flow. The conductive layer can be, for example, a metal layer or a (transparent) conductive oxide layer or a combination thereof.

Hereinafter, the present invention will be described with reference to an embodiment in which the first conductive type semiconductor layer does not have a conductive layer. It should be understood that a stack of the first conductive type semiconductor layer 10 having the conductive layer 15 may be used in place of the first conductive type semiconductor layer in another embodiment.

It is also noted that, as illustrated in FIG. 1c, in an embodiment, a thin tunneling barrier layer 10a, a thin tunneling barrier, may be disposed between the surface of the semiconductor substrate 5 and the first conductive semiconductor layer 10 Layer 10a to semiconductor substrate 5 and first conductive semiconductor layer A charge carrier between 10 provides a tunneling contact.

2 is a cross-sectional view showing the solar cell 1 after the continuation step. In this subsequent step, a first dielectric layer 20 is deposited on top of the first conductive semiconductor layer to cover the first conductive semiconductor layer at least in the first region portion A (please refer to FIG. 3).

It should be noted that in the case of selectively depositing a conductive layer as a conductive oxide, an intrinsic amorphous germanium layer may be deposited instead of the first dielectric layer.

The material of the first dielectric layer may include a material selected from the group consisting of tantalum nitride, hafnium oxide, hafnium oxynitride, dielectric organic compounds (such as "resist" or resin), dielectric metal oxide or dielectric metal. Nitride, and other materials in the group of suitable dielectrics.

In the case where the stacked end of FIG. 1a, FIG. 1b or FIG. 1c has a conductive oxide as the top layer, it may be beneficial to select a useful etchant to replace the dielectric layer with the intrinsic amorphous germanium layer.

3 is a cross-sectional view of the semiconductor substrate after the patterning step of the first dielectric layer. Patterning removes the first dielectric layer from the second region portion B of the semiconductor substrate from which the second junction is to be created. In the first region portion A where the first junction is to be created, the patterned first dielectric layer 21 remains. As in the aspect of the invention, the first region portion A is adjacent (adjacent) to the second region portion B of the semiconductor substrate.

By the patterning step, the interdigitated structure can be defined where the first type of junction and the second type of junction are staggered.

The patterning step includes an etching step (which may be a selective etching step) to The first dielectric layer is removed and the first conductive semiconductor layer is exposed in a region where the first dielectric layer is removed.

The patterned first dielectric layer 21 functions as a mask for producing the patterned first conductive type semiconductor layer 11. The exposed first conductive type semiconductor layer is removed from the second region portion B of the semiconductor substrate using an etching step which may be a selective etching step.

FIG. 4 schematically illustrates the patterning of the first conductive type semiconductor layer. Since the pattern of the first dielectric layer is transferred into the pattern of the first conductive type film layer, the pattern edges of the two film layers are substantially self-aligned. Such self-alignment has the advantage of reducing the number of process steps, reducing the required alignment tolerance, and reducing cost.

Figure 5a shows a cross-sectional view of the solar cell after the subsequent steps. On the patterned surface, at least adjacent to the second region portion B of the semiconductor substrate, and at least adjacent to the stack of the patterned first dielectric layer 21 and the patterned first conductive semiconductor layer 11 adjacent to the second region portion B A second conductive type semiconductor layer 25 is deposited over a portion.

In this structure, the patterned first dielectric layer 21 provides insulation between the second conductive type semiconductor layer 25 overlying the patterned first conductive type semiconductor layer 11 and the patterned first conductive type semiconductor layer 11.

The overlap of the first and second conductivity type semiconductors is illustrated as having a slope. It should be noted that the actual tilt angle may depend on the actual process steps and conditions. Further, the ramp may be substantially perpendicular to the surface of the substrate or stepped.

Further, the second conductive type semiconductor layer 25 is bordered on the patterned first conductive type semiconductor layer 11.

Because the first conductive type semiconductor layer 11 is patterned (below the film layer 21) The film layer 11 is etched. During the etching process, some undercut may occur, so the word "adjacent" is intended to define that the lateral distance between the two patterned semiconductor layers 11 and 25 is at most the first conductive type semiconductor layer 11 Several times the thickness.

For example, if the thickness of the patterned first conductive type semiconductor layer 11 is 20 nm, the adjacent film layer means that the distance from the patterned first conductive type semiconductor layer 11 is 100 nm or less.

Similar to the patterned first conductive type semiconductor layer 11, the film layer 25 may be selectively covered by a conductive layer such as a transparent conductive oxide (TCO) and/or a metal.

The material of the second conductive semiconductor layer may be selected from the group consisting of a second type doped amorphous germanium, a second type doped germanium-carbon mixture, a second type doped germanium-tellurium alloy, and a second type doped epitaxial growth. In the group of crystalline germanium, second doped polysilicon, or other semiconductors. Further, similarly to the first conductive type semiconductor layer, the second conductive type semiconductor layer may include a stack of an intrinsic semiconductor layer and a second type doped semiconductor layer having a material selected from the above. Further, similarly to the first conductive type semiconductor, a thin tunneling barrier layer (not shown) may be disposed between the surface of the semiconductor substrate 5 and the second conductive type semiconductor layer.

Further, the second conductive type film layer may also be composed of a layer stack forming a MIS junction.

The second conductivity type is opposite to the first conductivity type. The first conductive type semiconductor layer may constitute an emitter, and the second conductive type film layer may constitute a BSF; or the first conductive type film layer may constitute a BSF, and the second conductive type film layer may constitute an emitter.

In an embodiment, the first conductivity type is a p-type and the first conductivity type semiconductor The layer is p+ a-Si:H and the first dielectric layer is SiNx:H. Preferably, the present invention provides a structure in which the p-type a-Si:H layer is covered by the first dielectric. During subsequent deposition of the a-Si layer, the exposed p-type a-Si:H layer is substantially degraded by thermal exposure when exposed. The coverage of SiNx:H can protect the p-type layer from the above deterioration, and thus the present invention uses a p-type emitter as the first conductive type semiconductor layer. Since the p-type layer is generally the emitter that typically occupies the largest area on the back surface, it is preferred to start with a p-type layer based on battery efficiency factors.

Further, since the process of opening the first conductive type film layer may cause surface damage, and the surface damage will reduce the passivation property of the film layer deposited on the open area, the above manner is preferable.

FIG. 5b is a cross-sectional view showing a solar cell according to an embodiment after the subsequent steps described in FIG. 5a. In this embodiment, the tunneling barriers 10a and 10b are present on the surface of the semiconductor substrate 5 and patterned. Between one of the conductive semiconductor layers 11 or the tunneling barriers 10a and 10b is present between the surface of the semiconductor substrate 5 and the patterned second conductive semiconductor layer 25, or the tunneling barriers 10a and 10b are present on the semiconductor substrate. The surface of 5 is between the patterned first conductive semiconductor layer 11 and the second conductive semiconductor layer 25.

The tunneling barriers 10a and 10b under the first conductive semiconductor layer and the second conductive semiconductor layer may each be formed in separate processes. The tunneling barriers 10a and 10b may be grown by a surface reaction, or the tunneling barriers 10a and 10b may be deposited by physical or chemical deposition.

Figure 6 is a cross section of a solar cell after performing another step as in the present invention. In this further step, the mask layer 30 is deposited over at least a portion of the first region portion A and the second region portion B.

The mask layer may be selected from the group consisting of tantalum nitride (SiNx), cerium oxide (SiO ₂ ), cerium oxynitride (SiO _x N _y ), dielectric organic compound ("resistance" or resin), dielectric metal. Oxide or dielectric metal nitride, and other suitable dielectric materials. The mask layer can also be a metal (e.g., contacting) layer.

Alternatively, the mask layer may be an intrinsic amorphous layer depending on the etching properties of the top layer deposited in the process steps described above.

The patterning step illustrated in Figure 7 is then performed. In the patterning step, the mask layer 30 is patterned by removing the mask layer from the patterned third dielectric layer 21 and the patterned third region portion C of the patterned first conductive semiconductor layer 11 The mask 31 is patterned.

Alternatively, the mask layer 30 may be deposited in a suitable pattern (pattern of the film layer 31), for example, by deposition via a proximity mask, or by deposition by printing techniques.

The generated third region portion C is smaller than the first region portion A, thus exposing portions of the patterned second dielectric layer 21 and the second conductive type semiconductor layer over the stack of the patterned first conductive semiconductor layer 11. At the same time, the dielectric layer 31 covers other portions of the second conductive type semiconductor layer 25 that overlap with the stacked layers of the patterned first dielectric layer 21 and the patterned first conductive type semiconductor layer 11.

Figure 8 is a cross-sectional view of the solar cell after the subsequent etching step, in which the patterned mask 31 is used to blast the third region portion C. The exposed second conductive type semiconductor layer 25 is removed, thereby producing the patterned second conductive type semiconductor layer 26. During this removal, the first dielectric layer 21 protects the first conductive type film layer 11, and the first dielectric layer 21 also serves as this second removed etch-stop.

In addition to the foregoing manner of depositing and patterning the film layers 30 and 31 and etching the film layer 25, another alternative is to remove the second conductive type semiconductor layer 25 on the third region portion C by a direct etching process. The direct etching process is, for example, printing or (ink) jet etchant, or plasma etching through a proximity mask.

So far, the solar cell structure includes: a first region portion A, wherein the first junction is disposed between the patterned first conductive semiconductor layer 11 and the substrate 5; and the second region portion B, wherein the second junction is disposed in the pattern The second conductive semiconductor layer 26 is interposed between the substrate 5. Since the first region portion A and the second region portion B are on the surface of the semiconductor substrate, the first region portion A and the second region portion B are adjacent to each other, and the first junction surface and the second junction surface are also adjacent to each other. In this manner, the first junction and the second junction can be arranged in the closest manner. The adjacent configuration of this junction provides substantially complete coverage of the actively used substrate area for collecting charge carriers.

9a-9c are cross-sectional views of a solar cell after subsequent steps as in various embodiments.

In this step, the patterned mask 31 or the patterned second conductive semiconductor layer 26 functions as a mask for etching and removing the patterned first dielectric layer 21 in the third region portion C. For example, local shifting by a direct etch process (as described above) In the case of the film layer 25, the mask 31 may not be present.

The film layer 21 (in the third region portion C or a smaller portion thereof) may be partially removed by a direct patterning step such as printing an etchant (Fig. 9b).

While locally removing the film layers 21 and 31 by a wet chemical etching step, the region D and the regions A and B can be protected by, for example, a dielectric etching mask such as the deposited photoresist pattern 27. Some of the adjacent areas. As shown in Fig. 9c, the film layer 21 has a portion extending into the region A (this portion has a length), and the film layer 31 exists on the region D and has a portion extending into the region B (this portion has a length) Therefore, the structure obtained through the above process is different from that shown in Fig. 9a.

The configuration of Figure 9c can be used to improve long term stability and improve electrical isolation in the final solar cell (structure as shown in Figure 10e).

If the patterned mask 31 is present, the patterned mask 31 can be removed in the same etching step of removing the film layer 21 (the etching selectivity and thickness of the first and second dielectric layers are compatible) In the case of the method, or in another selective etching step, the patterned mask 31 is removed.

After performing the etching step and the removing step on the patterned mask 31, the solar cell structure includes: a first region portion A, wherein the first junction is disposed between the patterned first conductive semiconductor layer 11 and the substrate 5; The second region portion B, wherein the second junction is disposed between the patterned second conductive semiconductor layer 26 and the substrate 5. Further, the solar cell structure includes an overlapping portion in which the patterned second conductive type semiconductor layer 26 overlaps the patterned first conductive type semiconductor layer. In the overlap region D, the second conductive type semiconductor layer 26 is separated and isolated by patterning the first dielectric layer 21. in In this example, the width of the region D shown in Figures 9a, 9b, and 9c is between about 1 micrometer and about 1000 micrometers. In other examples, the width of region D is between about 10 microns and about 500 microns. In yet another embodiment, the width of the region D is between about 50 microns and about 250 microns.

Both the patterned first conductive semiconductor layer 11 in the first region portion A and the patterned second conductive semiconductor layer 26 in the second region portion B are in direct contact with the substrate surface above the corresponding full region portion (or In the case where a tunneling barrier layer is present on the surface of the substrate, the two are in direct contact with the tunneling barrier layer covering the surface of the substrate, and the first junction and the second junction are respectively formed.

Therefore, the first conductive type semiconductor layer 11 is substantially in full contact with the substrate.

Figures 10 through 14 illustrate some of the processes that can be used for metallization. Metallization may be comprised of the conductive layers previously described, and/or other conductive layers that may be subsequently (additional) applied.

In FIGS. 10 to 14, elements having the same reference numerals as those in the aforementioned figures refer to corresponding elements.

10a to 10e are cross-sectional views showing the solar cell 1 after the metallization step. As shown in FIG. 10a, metal layers (metal conductive layers) 34, 35 are deposited on top of the patterned first conductive semiconductor layer 11 and the patterned second conductive semiconductor layer 26. Figures 10b to 10e illustrate the selective adjustment of this step.

The metal layers 34 and 35 are patterned by at least the gaps 36 in the metal layer to form a first portion (at the symbol 34) of the metal layer over the first junction structure of the substrate 5 and the film layer 11 and the substrate 5 and Metal above the second junction structure of film layer 26 Electrical insulation is created between the second portion of the layer (at symbol 35). The gap 36 is located at least over the overlapping portion of the second conductive semiconductor layer 26 to achieve maximum metal coverage and minimum impedance loss on the film layer 11 and the film layer 26, but the gap 36 may further extend to the portion A or B or both. Above.

For example, if the dielectric layer 21 is not completely pinhole, the gap 36 is extended from the overlapping portion to the first portion A or the second portion B or both of the portions A and B, and such The way to reduce the possibility of shunting.

FIG. 10e illustrates an embodiment in which all regions of the patterned first conductive semiconductor layer 11 and the patterned second conductive semiconductor layer 26 are not directly exposed to atmospheric conditions. The same dielectric layer 37 as the dielectric layer 27 depicted in FIG. 9c covers the area of the film layer 26 adjacent to the overlapping regions of the first semiconductor layer 11 and the second semiconductor layer 26. This configuration enhances the durability of solar cell performance. The metal layers 34 and 35 may be deposited as a blanket and subsequently patterned by etching, or may be deposited directly in a pattern.

The metal layer may also be composed of a first blanket deposited layer (eg, a conductive oxide and/or a seed metal layer); followed by a patterned deposition of the second metal layer (eg, screen printing or spraying) The ink pattern of the ink or the photoresist pattern is connected (electro) plating; then the second metal pattern is used as a mask to etch back the first layer.

In one embodiment, the first blanket layer having a dielectric layer (for example, tantalum nitride) may be applied, and then the dielectric layer may be patterned and electroplated and oxidized in a place without a dielectric. a material such that the first blanket deposited film layer is provided with a metal pattern case.

11a to 11c illustrate cross-sectional views of a solar cell 2 as in other corresponding embodiments. The single-layer first conductive type semiconductor layer is replaced with a first stacked layer, and the first stacked layer forms a first junction structure on the substrate and includes a first conductive type semiconductor layer 11 and a conductive layer 15 on the top thereof. The stack configuration is similar to that shown in Figure 1b.

The patterned second conductive type semiconductor layer 26 is covered by the second conductive layer 40 and forms a second stacked layer. Preferably, the second conductive layer is patterned in a manner corresponding to the second conductive type semiconductor layer 26, for example, by referring to the above-described process of FIG. In the embodiment illustrated in Figure 11a, the gap 36 above the overlapping portion may be omitted.

The first stacked layer is adjacent to the second stacked layer. The second stacked layer overlaps the first stacked layer in the overlap region D. In the overlap region D, the first stacked layer is separated from the overlapped second stacked layer by 21 in a manner similar to that illustrated in FIGS. 5 to 8.

In the case where the conductive layer 15 in the first junction structure is a conductive oxide, the dielectric layer 21 may be substituted for the intrinsic amorphous semiconductor layer.

11b and 11c illustrate an embodiment in which the gap 36 in the second conductive layer 40 extends above the overlap portion D or a portion of the second region portion B.

If necessary, a gap 36 may be formed in the second conductive layer 40 around the overlapping portion of the second conductive type semiconductor layer 26 to improve isolation from the conductive layer 15 in the first junction structure.

It should be understood that the overlapping portions D of various oblique forms are obtained as described above, and thus the first and second conductive type semiconductor layers have different slopes of overlap as shown in FIGS. 11a and 11b and 11c.

Figure 12 is a cross-sectional view showing a solar cell according to another embodiment after the manufacturing step.

In this embodiment, the first junction structure in the first region portion A includes a stack of the first conductive type semiconductor layer 11 and the conductive layer 15 at the top thereof. The stack of the first conductive type semiconductor layer 11 and the conductive layer 15 is patterned, and the stack of the first conductive type semiconductor layer 11 and the conductive layer 15 is covered by the patterned dielectric layer 22.

The second conductive type semiconductor layer 25 covers the patterned stack of the first conductive type semiconductor layer 11, the conductive layer 15, and the dielectric layer 22. In the second junction structure in the second region portion B, a stack of the patterned second conductive layer 45 and the second mask layer 50 is disposed, and the second mask layer 50 is on the top of the second conductive layer 45. .

In order to obtain the structure illustrated in FIG. 12, at least the second conductive layer 45 and the second mask layer 50 are deposited over at least the second region portion B. The second mask layer 50 is then patterned. The patterned second mask layer 50 is then used to define the location of the patterned second conductive layer 45 in the second region portion B. An interval S is selectively generated between the end E of the patterned second conductive layer 45 and the boundary F of the first region portion A and the second region portion B to improve insulation.

FIG. 13 is a cross-sectional view of the solar cell of FIG. 12 after the subsequent step, in which the second mask layer 50 is selectively removed, as illustrated in an embodiment. It should be understood that the removal of the second mask layer 50 may be selective due to the contact with the second conductive layer 45 (eg, by mechanical force) through the second mask layer 50.

Figure 14 is a cross-sectional view of the solar cell 3 of Figure 13 after subsequent manufacturing steps. In this subsequent step, a dielectric is deposited over the structure as depicted in FIG. A layer (such as a photoresist layer). Then, if the dielectric layer is not patterned, the dielectric layer is patterned to form a protective dielectric body 55 (eg, a photoresist layer) covering the overlapping portion of the second conductive semiconductor layer and the first region A boundary region (E to F) between the portion A and the second region portion B.

The patterned protective dielectric body is used as an etching/removing second conductivity type semiconductor in such a manner that the overlapping portion of the second conductive type semiconductor layer overlaps the stack of the patterned conductive layer 15 and the patterned first conductive type semiconductor layer 11 A portion of the layer 25 and the dielectric layer 22 are masked, wherein the conductive layer 15 and the second conductive layer 45 are used as an etch stop layer. The first dielectric layer 21 serves as a separation layer.

The protective dielectric body 55 can be used in a subsequent plating step, such as a plating step, such that the metal contacts on the first region portion A are separated from the metal contacts on the second region portion B. Since the protective dielectric body 55 can protect the film layer 26 which is very thin and susceptible to atmospheric conditions penetrating the solar module, the protective dielectric body 55 can also provide durability for solar cell performance.

It will be understood by those of ordinary skill in the art that the protective dielectric body can be utilized in other embodiments, such as the embodiment illustrated in Figure 10e.

It is to be understood by those of ordinary skill in the art that the present invention may be practiced and practiced without departing from the true spirit of the invention, and the scope of the invention is only limited by the scope of the appended claims. . The above examples are intended to illustrate and not to limit the invention.

1‧‧‧Solar battery

11‧‧‧ patterned first conductive semiconductor layer

21‧‧‧ patterned first dielectric layer

26‧‧‧ patterned second conductive semiconductor layer

A‧‧‧First Area Section

B‧‧‧Part II section

C‧‧‧Part III

D‧‧‧ overlap

Claims (18)

A solar cell comprising: a semiconductor substrate having a front side surface for receiving radiation, and a back side surface configured with a first junction in a first region portion of the semiconductor substrate a structure and a second junction structure in the second region portion of the semiconductor substrate; the second region portion is adjacent to the first region portion; the first junction structure includes a portion covering the first region portion a first conductive type semiconductor layer; the second junction structure includes a second conductive type semiconductor layer covering the second region portion; the second conductive type semiconductor layer of the second junction structure and the first The first conductive type semiconductor layer of a junction structure partially overlaps, and an overlapping portion of the second conductive type semiconductor layer is located above a portion of the first conductive type semiconductor layer, and at the same time by the second a first dielectric layer between the overlapping portion of the conductive semiconductor layer and the portion of the first conductive type semiconductor layer, the overlapping portion of the second conductive type semiconductor layer The portions of the first conductive type semiconductor layer are separated, and the portion of the first conductive type semiconductor layer under the overlapping portion of the second conductive type semiconductor layer directly contacts a semiconductor surface of the semiconductor substrate Wherein the second conductive type semiconductor layer in the second region portion is adjacent to The first conductive semiconductor layer in the first region portion, the second conductive semiconductor layer in the second region portion is adjacent to the first conductive semiconductor layer and the second conductive semiconductor The overlapping part of the layer. The solar cell of claim 1, wherein the first junction structure comprises a first tunneling barrier layer, and the first tunneling barrier layer is disposed on the first conductive semiconductor layer and Between the semiconductor substrates; and/or wherein the second junction structure includes a second tunneling barrier layer, the second tunneling barrier layer is disposed on the second conductive semiconductor layer and the semiconductor Between the substrates. The solar cell of claim 1, wherein at least one of the first junction structure and the second junction structure comprises an epitaxial layer, and the first conductive semiconductor layer is a Lei The germanium layer and/or the second conductive semiconductor layer is an epitaxial layer. The solar cell according to claim 1, wherein an interface of the overlapping portion of the first conductive semiconductor layer and the surface of the semiconductor substrate is a void of the dielectric layer. The solar cell according to any one of claims 1 to 4, wherein the first conductivity type is p-type, and the first conductivity type semiconductor layer comprises p-type doped amorphous hydrogen hydride (p+ a-Si:H), the first dielectric layer includes yttrium hydrogen hydride (SiNx:H). The solar cell of any one of clauses 1 to 5, wherein the first junction structure comprises an additional first conductive layer or layer on top of the first conductive semiconductor layer Stacking. The solar cell of claim 6, wherein the additional first conductive layer is a metal layer, or the layer stack comprises a conductive oxide layer and an amorphous semiconductor layer, the amorphous semiconductor layer being disposed in the a conductive oxide layer and a top of the first conductive semiconductor layer. The solar cell of any one of clauses 1 to 7, wherein the second junction structure comprises an additional second conductive layer or layer stack on top of the second conductive semiconductor layer. The solar cell of claim 8, wherein the additional second conductive layer is a metal layer, or the layer stack comprises a conductive oxide layer and an amorphous semiconductor layer, the amorphous semiconductor layer being disposed in the a conductive oxide layer and a top of the second conductive semiconductor layer. The solar cell according to any one of claims 1 to 9, wherein the material of the first conductive type semiconductor layer comprises an intrinsic amorphous germanium layer or a tunneling barrier layer, and a doped layer; The impurity layer is selected from the group consisting of a first type doped amorphous germanium, a first type doped germanium-carbon mixture, a first type doped germanium-tellurium alloy, a first type doped epitaxial growth crystalline germanium, and a first type In the group doped with polysilicon. The solar cell according to any one of claims 1 to 10, wherein the material of the second conductive type semiconductor layer is selected from the group consisting of a second type doped amorphous germanium, a second type doped germanium-carbon mixture. Second type doped ytterbium-rhenium alloy, second type doped epitaxial In the group of grown crystalline germanium, second-type doped polysilicon, and other semiconductors. The solar cell according to any one of claims 1 to 11, wherein the material of the first dielectric layer is selected from the group consisting of tantalum nitride, hafnium oxide, hafnium oxynitride, dielectric organic compound, dielectric. In the group of metal oxides and dielectric metal nitrides. The solar cell according to any one of claims 1 to 12, wherein the first junction structure comprises a first tunneling barrier layer, and the first tunneling barrier layer is disposed on the first conductive layer Between the semiconductor layer and the semiconductor substrate; and/or wherein the second junction structure includes a second tunneling barrier layer, and the second tunneling barrier layer is disposed on the second conductive semiconductor layer Between the semiconductor substrate and the semiconductor substrate. A method of manufacturing a solar cell from a semiconductor substrate, the semiconductor substrate having a front side surface for receiving radiation, and the back side surface being disposed in a first region portion of the semiconductor substrate a first junction structure, and a second junction structure in the second region portion of the semiconductor substrate, the second region portion is adjacent to the first region portion, and the method for manufacturing a solar cell from a semiconductor substrate comprises: Depositing a first conductive type semiconductor layer on at least the back side surface of the semiconductor substrate above the first region portion; selectively depositing a conductive layer; depositing a first dielectric layer at least over the first conductive type semiconductor layer An electrical layer; the first dielectric layer is patterned to define the first region portion by covering the first conductive type semiconductor in the first region portion, and to expose the The second area portion; Patterning the first conductive semiconductor layer using the patterned first dielectric layer as a mask to create the first junction structure in the first region portion, and exposing the a surface of the germanium substrate in the second region portion; depositing a second conductive type semiconductor layer on the back side surface and the exposed second region portion, the second conductive type semiconductor layer being adjacent to the Above at least a portion of the first dielectric layer of the second region portion, in this manner, the second conductive type semiconductor layer of the second junction structure and the first portion of the first junction structure a conductive semiconductor layer partially overlapping, an overlapping portion of the second conductive semiconductor layer being over a portion of the first conductive semiconductor layer while being overlapped by the overlapping portion of the second conductive semiconductor layer The first dielectric layer between the portions of the first conductive type semiconductor layer separates the overlapping portion of the second conductive type semiconductor layer from the portion of the first conductive type semiconductor layer And the second The electrical-type semiconductor layer below the portion of the overlapping portion of the first conductive type semiconductor layer directly contacts the semiconductor surface of the semiconductor substrate. The method for manufacturing a solar cell from a semiconductor substrate according to claim 14, further comprising: depositing a mask layer over the second conductive type semiconductor layer, the mask layer covering at least the second region portion And a portion of the first region portion; patterning the mask layer; using the patterned mask layer as a mask for the second conductivity type semiconductor The bulk layer is patterned to create the second junction structure in the second region portion, the second junction structure having a pattern such that the second conductive semiconductor layer is adjacent and partially overlapping The first conductive semiconductor layer; the overlapping portion of the second conductive semiconductor layer is on top of the first conductive semiconductor layer, and the first dielectric layer The overlapping portion of the two-conductivity-type semiconductor layer and the top portion of the first-conductivity-type semiconductor layer are separated. The method of manufacturing a solar cell from a semiconductor substrate according to claim 14, wherein the first junction structure is provided with a first tunneling barrier layer, and the first tunneling barrier layer is disposed in the Between the first conductive semiconductor layer and the semiconductor substrate; and/or wherein the second junction structure is configured with a second tunneling barrier layer, and the second tunneling barrier layer is disposed at the second Between the conductive semiconductor layer and the semiconductor substrate. The method of manufacturing a solar cell from a semiconductor substrate according to claim 14, wherein at least one of the first junction structure and the second junction structure comprises an epitaxial layer, the first The conductive semiconductor layer is an epitaxial layer and the semiconductor substrate; and/or the second conductive semiconductor layer is an epitaxial layer. The method of manufacturing a solar cell from a semiconductor substrate according to claim 14, wherein the first conductivity type is p-type, and the first conductivity type semiconductor layer comprises p-type doped amorphous hydrogen hydride (p+) a-Si:H), and the first dielectric layer includes yttrium hydrogen hydride (SiNx:H), and the SiNx:H layer covers the p+ a-Si:H layer.