KR102223562B1 - Hybrid polysilicon heterojunction back contact cell - Google Patents

Abstract

A method of manufacturing a high-efficiency solar cell is disclosed. The method includes providing a thin dielectric layer and a doped polysilicon layer on the back side of the silicon substrate. Subsequently, both a high quality oxide layer and a wide bandgap doped semiconductor layer can be formed on the back and front surfaces of the silicon substrate. Subsequently, a metallization process of plating metal fingers on the doped polysilicon layer through the contact openings may be performed. The plated metal fingers may form a first metal grid line. The second metal grid line may be formed by directly plating a metal on the emitter region on the rear surface of the silicon substrate, thereby eliminating the need for contact openings for the second metal grid line. Among other advantages, this manufacturing method provides a reduced thermal process, a reduced etch step, increased efficiency, and a simplified procedure for the manufacture of high-efficiency solar cells.

Description

Hybrid polysilicon heterojunction back contact cell {HYBRID POLYSILICON HETEROJUNCTION BACK CONTACT CELL}

Embodiments of the subject matter described herein generally relate to solar cell manufacturing. More specifically, embodiments of the subject matter relate to thin silicon solar cells and manufacturing techniques.

Solar cells are known devices for converting solar radiation into electrical energy. Solar cells can be fabricated on semiconductor wafers using semiconductor processing techniques. The solar cell includes P-type and N-type diffusion regions. Solar radiation striking the solar cell creates electrons and holes that move into the diffusion regions, thereby creating a voltage difference between the diffusion regions. In a backside contact solar cell, both the diffusion regions and metal contact fingers bonded to them are on the backside of the solar cell. The contact fingers allow external electrical circuits to be coupled to the solar cell and powered by the solar cell.

Since efficiency is directly related to the power generation capability of a solar cell, it is an important characteristic of a solar cell. Therefore, techniques for improving the manufacturing process of the solar cell, reducing manufacturing cost, and increasing efficiency are generally desirable. Such techniques include forming a polysilicon and heterojunction layer on a silicon substrate via thermal processes, wherein the present invention contemplates an increase in solar cell efficiency. These or other similar embodiments form the background of the present invention.

When like reference numerals are considered in connection with the accompanying drawings indicating like elements throughout the drawings, a more complete understanding of the subject matter may be obtained by referring to the detailed description and claims.
<Figures 1 to 12>
1 to 12 are cross-sectional views of a solar cell manufactured according to an embodiment of the present invention.
<Figs. 13 to 18>
13 to 18 are cross-sectional views of a solar cell manufactured according to another embodiment of the present invention.

The following detailed description is merely exemplary in nature and is not intended to limit the subject matter or embodiments of the application and the use of such embodiments. As used herein, the word “exemplary” means to serve as an example, instance, or example. Any embodiment described herein as illustrative is preferred or advantageous over other embodiments. In addition, there is no intention to be limited by any expressed or implied theory presented in the foregoing technical field, background, brief summary, or the following detailed description.

A method of manufacturing a solar cell is disclosed. The method includes providing a silicon substrate having a thin dielectric layer on the back side and a deposited silicon layer over the thin dielectric layer; Forming a layer of a doping material over the deposited silicon layer; Forming an oxide layer over the layer of doped material; Partially removing the oxide layer, the layer of doped material, and the deposited silicon layer in an interdigitated pattern; Growing the oxide layer while raising the temperature to drive the dopant from the layer of doping material into the deposited silicon layer; Doping the deposited silicon layer with a dopant from the layer of doped material to form a crystallized doped polysilicon layer; Depositing a wide band gap doped semiconductor and antireflective coating on the back side of the solar cell; And depositing a wide bandgap doped semiconductor and antireflective coating on the front side of the solar cell.

Another method of manufacturing a solar cell is disclosed. The method includes providing a silicon substrate having a thin dielectric layer on the back side and a deposited silicon layer over the thin dielectric layer; Forming a layer of a doping material over the deposited silicon layer; Forming an oxide layer over the layer of doped material; Partially removing the oxide layer, the layer of doped material, and the deposited silicon layer in an intersecting pattern; Etching the exposed silicon substrate to form a textured silicon region; Growing the oxide layer while raising the temperature to drive the dopant from the layer of doping material into the deposited silicon layer; Doping the deposited silicon layer with a dopant from the layer of doped material to form a doped polysilicon layer; Covering an anti-reflective coating and a first thick layer of doped amorphous silicon of the wide bandgap on the rear surface of the solar cell; Covering a second thin layer of doped amorphous silicon with an antireflection coating and a wide bandgap on the front side of the solar cell, the thin layer being 10% to less than 30% of the thickness of the thick layer.

Another method of manufacturing a solar cell is disclosed. The method includes providing a silicon substrate having a thin dielectric layer on the back side and a doped silicon layer over the thin dielectric layer; Forming an oxide layer over the doped silicon layer; Partially removing the oxide layer and the doped silicon layer in an intersecting pattern; Growing a silicon oxide layer on the back surface of the solar cell by heating the silicon substrate in an oxygenated environment, the silicon layer crystallizing to form a doped polysilicon layer; Depositing a wide bandgap doped semiconductor on the back side of the solar cell; And depositing a wide bandgap doped semiconductor and antireflective coating on the front side of the solar cell.

Another method of manufacturing a solar cell is disclosed. The method includes providing a silicon substrate having a thin dielectric layer on the back side and a doped silicon layer over the thin dielectric layer; Forming an oxide layer over the doped silicon layer; Partially removing the oxide layer and the doped silicon layer in an intersecting pattern; Etching the exposed silicon substrate to form a textured silicon region; Growing a silicon oxide layer on the back surface of the solar cell by heating the silicon substrate in an oxygen-containing environment, the silicon layer crystallizing to form a doped polysilicon layer; Depositing a wide bandgap doped amorphous silicon and an antireflective coating on the back side of the solar cell, and depositing a wide bandgap doped amorphous silicon and an antireflection coating on the front side of the solar cell.

Another embodiment of a method of manufacturing a solar cell is disclosed. The method includes providing a silicon substrate having a thin dielectric layer on the back side and a doped silicon layer over the thin dielectric layer; Forming an oxide layer over the doped silicon layer; Partially removing the oxide layer and the doped silicon layer in an intersecting pattern; Etching the exposed silicon substrate to form a textured silicon region; Growing a silicon oxide layer on the back surface of the solar cell by heating the silicon substrate in an oxygen-containing environment, the silicon layer crystallizing to form a doped polysilicon layer; Simultaneously depositing a wide bandgap doped amorphous silicon and an antireflective coating on the front and back surfaces of the solar cell; Forming a series of contact openings by partially removing the doped semiconductor and oxide layer of the wide bandgap over the front and rear surfaces of the solar cell; And simultaneously forming a first metal lattice electrically coupled to the doped polysilicon and a second metal lattice electrically coupled to the emitter region on a rear surface of the solar cell.

An improved technique for manufacturing solar cells is to provide a thin dielectric layer and a deposited silicon layer on the back side of a silicon substrate. Regions of doped polysilicon may be formed by dopant driving into deposited silicon layers or by in-situ formation of doped polysilicon regions. Subsequently, an oxide layer and a layer of a wide bandgap doped semiconductor may be formed on the front and rear surfaces of the solar cell. One variation involves texturing the front and back surfaces prior to the formation of the oxide and the formation of the wide bandgap doped semiconductor. Subsequently, contact holes may be formed through the upper layers to expose the doped polysilicon region. Subsequently, a metallization process may be performed to form contacts on the doped polysilicon layer. In addition, the second group of contacts can be formed by directly connecting metal to emitter regions on the silicon substrate formed by the wide bandgap semiconductor layer positioned between regions of doped polysilicon on the rear surface of the solar cell. .

Various operations performed in connection with the manufacturing processes are shown in FIGS. 1 to 18. Further, some of the various tasks need not be performed in the order illustrated, and may be incorporated into a more comprehensive procedure, process, or manufacturing with additional functions not described in detail herein.

1-3 show one embodiment for fabricating a solar cell 100 comprising a silicon substrate 102, a thin dielectric layer 106 and a deposited silicon layer 104. In some embodiments, the silicon substrate 102 may be cleaned, polished, planarized and/or thinned or otherwise processed prior to formation of the thin dielectric layer 106. The thin dielectric layer 106 and the deposited silicon layer 104 can be grown through a thermal process. A layer of doped material 108 followed by a first oxide layer 110 may be deposited over the deposited silicon layer 104 through a conventional deposition process. The layer of doping material 108 may include a doping material or dopant 109, but with a layer of a negative-type doping material such as phosphorus or a layer of a positive-type doping material such as boron. Not limited. While the thin dielectric layer 106 and the deposited silicon layer 104 are each described as being grown by a thermal process or deposited through a conventional deposition process, any other formation, deposition described or recited herein , Or as in the case of a growth process step, each layer or material may be formed using any suitable process. For example, where formation is described, a chemical vapor deposition (CVD) process, low pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), plasma-enhanced CVD (PECVD), thermal growth, sputtering, as well as any other desired techniques are employed. Can be used. Accordingly and similarly, the doping material 108 may be formed on the substrate by a deposition technique such as inkjet printing or screen printing, sputtering, or a printing process.

4 shows the same solar cell 100 from FIGS. 1-3 after performing a material removal process to form exposed polysilicon regions 124. Some examples of material removal processes include mask and etching processes, laser ablation processes, and other similar techniques. The exposed polysilicon regions 124 and the layer of doped material 108 can be formed into any desired shape, including an intersecting pattern. When a masking process is used, this can be done using a screen printer or an inkjet printer to apply the mask ink in a predetermined crossover pattern. Thus, conventional chemical wet etching techniques can be used to remove the mask ink resulting in a cross-sectional pattern of exposed polysilicon regions 124 and layer 108 of doping material. In at least one embodiment, some or all of the first oxide layer 110 may be removed. This can be done in the same etching or fusing process in which regions of the deposited silicon layer 104 and dielectric layer 106 are removed, as shown in FIGS. 4 and 5.

5, the solar cell 100, in order to increase solar radiation collection, by etching the exposed polysilicon regions 124, the first textured silicon region 130 and the solar cell on the rear surface of the solar cell. May undergo a second etching process resulting in a second textured silicon region 132 on the front side of the. The textured surface may be one that has a regular or irregularly shaped surface for scattering incoming light to reduce the amount of light reflected back from the surface of the solar cell.

Referring to FIG. 6, solar cell 100 may be heated 140 to drive doped material 109 from layer 108 of doped material into deposited silicon layer 104. Also, the same heating 140 may form a silicon oxide or a second oxide layer 112 over the layer 108 of doping material and the first textured silicon region 130. During this process, a third oxide layer may be grown 114 over the second textured silicon region 132. Both of the oxide layers 112 and 114 may comprise a high quality oxide. High quality oxides are low interface state density oxides that are typically grown by thermal oxidation at temperatures above 900 degrees Celsius that can provide improved passivation.

Thus, referring to FIG. 7, the deposited silicon layer 104 can be doped with a doped material 109 from the layer 108 of a dopant material to form a doped polysilicon layer 150. In one embodiment, forming the doped polysilicon layer is performed by growing the oxide layer while increasing the temperature to drive the dopant 109 from the layer 108 of the doped material to the deposited silicon layer 104. Wherein doping the deposited silicon layer 104 with a dopant 109 from the layer 108 of doped material forms a doped polysilicon layer or doped polysilicon layer 150 that has been crystallized. In one of some embodiments, the doped polysilicon layer 150 may include a layer of positively doped polysilicon if a p-type doped material is used. In the illustrated embodiment, the silicon substrate 102 comprises a bulk N-type silicon substrate. In some embodiments, doped polysilicon layer 150 may include a layer of negatively doped polysilicon if an n-type doped material is used. In one embodiment, the silicon substrate 102 should comprise a bulk P-type silicon substrate.

Referring to FIG. 8, a doped semiconductor layer 160 of a first wide bandgap may be deposited on the rear surface of the solar cell 100. In one embodiment, the first wide bandgap doped semiconductor layer 160 is partially conductive with a resistivity of at least 10 ohm-cm. In the same embodiment, 1.05 electron-volts (eV) which now act as a heterojunction in the regions of the backside of the solar cell covered by the first textured silicon region 130 and by the second oxide layer 112. ) May have a band gap greater than. Examples of wide bandgap doped semiconductors include silicon carbide and aluminum gallium nitride. Any other wide bandgap doped semiconductor material exhibiting the properties and characteristics described above may also be used. The first wide bandgap doped semiconductor layer 160 may be formed of a thick first wide bandgap doped amorphous silicon layer.

Referring to FIG. 9, the second wide bandgap doped semiconductor 162 may be deposited over the second textured silicon region 132 on the front side of the solar cell 100. In one embodiment, both of the wide bandgap doped semiconductor layers 160 and 162 on the rear and front surfaces of the solar cell 100 may include a wide bandgap n-type doped semiconductor. In another embodiment, the doped semiconductor 162 of the second wide bandgap may be relatively thinner than the doped semiconductor layer of the thick first wide bandgap. Thus, in some embodiments, the thin second wide bandgap doped semiconductor layer may consist of 10 to 30% of the thickness of the thick first wide bandgap doped semiconductor layer. In another embodiment, both of the wide bandgap doped semiconductor layers 160 and 162 on the back and front surfaces of the solar cell, respectively, contain a wide bandgap n-type doped semiconductor or a wide bandgap p-type doped semiconductor. Can include. Subsequently, an anti-reflective coating (ARC) 170 may be deposited over the second wide bandgap doped semiconductor 162 in the same process. In another embodiment, the anti-reflective coating 170 may be deposited over the first wide bandgap doped semiconductor 160 in the same process. In some embodiments, the ARC 170 may be made of silicon nitride.

10 shows a first wide bandgap doped semiconductor 160, a second oxide layer 112 and a layer of doped material on the back side of the solar cell 100 to form a series of contact openings 180 ( 108). In one embodiment, the removal technique can be achieved using a flux process. One such ablating process is a laser ablating process. In another embodiment, the removal technique may be any conventional etching processes, such as screen printing or inkjet printing of the mask followed by an etching process.

Referring to FIG. 11, a first metal grid or grid line 190 may be formed on the rear surface of the solar cell 100. The first metal grid line 190 may be electrically coupled to the doped polysilicon 150 in the contact openings 180. In one embodiment, the first metal grid line 190 is a doped semiconductor 160 of a first wide bandgap, a second oxide layer ( 112 ), and a layer of doping material 108 through the contact openings 180.

Referring to FIG. 12, a second metal grid or grid line 192 may be formed on the rear surface of the solar cell 100, and the second metal grid line 192 is a second textured silicon region 132. Is electrically coupled to In one embodiment, the second metal grid line 192 is a doped semiconductor 160 of a first wide bandgap, a second oxide layer ( 112), and a first textured silicon region 130 that acts as a heterojunction in regions of the rear surface of the solar cell. In some embodiments, the formation of the metal grid lines referenced in FIGS. 11 and 12 is an electroplating process, a screen printing process, an inkjet process, plating on a metal formed from aluminum metal nanoparticles, or any other metallization or metal. It can be carried out through a forming process step.

13 to 18 illustrate another embodiment of manufacturing the solar cell 200. Unless otherwise specified below, numerical indicators used to refer to elements in FIGS. 13 to 18 refer to the elements or features of FIGS. 1 to 12 described above, except that the index is increased by 100. It is similar to what was used to do.

13 and 14, another embodiment for manufacturing the solar cell 200 is a first oxide layer 210, a thin dielectric layer 206, a doped polysilicon layer 250 over a silicon substrate 202. ) May include forming. The silicon substrate 202 may be cleaned, polished, planarized, and/or thinned or otherwise processed prior to formation of the thin dielectric layer 206, as discussed similarly above. The first oxide layer 210, the dielectric layer 206, and the doped polysilicon layer 250 may be grown through a thermal process. In one embodiment, a silicon oxide layer or oxide layer 210 is grown on the rear surface of the solar cell by heating the silicon substrate 202 in an oxygen-containing environment, wherein the doped silicon layer is crystallized and the doped polysilicon layer 250 ) To form. In another embodiment, growing the doped polysilicon layer 250 over the dielectric layer 206 includes growing the doped polysilicon in an amount that may be composed of a doped material 209 such as a boron dopant. do. In another embodiment, negatively doped polysilicon may be used. Although the thin dielectric layer 206 and the doped polysilicon layer 250 are each described as being grown by a thermal process or deposited through a conventional deposition process, any other formations described or recited herein, As in the case of the deposition or growth process step, each layer or material can be formed using any suitable process as discussed above.

The solar cell 200 includes a first oxide layer 210 and a doped polysilicon layer 250 in order to expose the exposed area of the silicon substrate 220 in an intersecting pattern using conventional masking and etching processes. And by partially removing the dielectric layer 206. In the case of using conventional masking and etching processes, a flux process may be used. When a flux process is used, the first oxide layer 210 may remain partially intact over the doped polysilicon layer 250, as illustrated in FIG. 14. In other embodiments, screen printing or inkjet printing techniques combined with an etching process may be used. In such an embodiment, the first oxide layer 210 may be etched away from the doped polysilicon layer 250.

Referring to FIG. 15, the exposed silicon substrate 220 and the exposed area on the front surface of the solar cell 200 are etched at the same time, so that the first textured silicon surface 230 and the second are used to increase solar radiation collection. A textured silicon surface 232 may be formed.

Referring to FIG. 16, the solar cell 200 has a temperature of more than 900 degrees Celsius while forming the second oxide layer 212 on the rear surface of the solar cell 200 and the third oxide layer 214 on the front surface. It can be heated to 240. In another embodiment, both oxide layers 212 and 214 may be composed of a high quality oxide as discussed above.

Referring to FIG. 17, the doped semiconductor layer 260 of the first wide bandgap may be simultaneously deposited on the rear and front surfaces of the solar cell. The doped semiconductor layer 260 of the first wide bandgap may be partially conductive with a resistivity of more than 10 ohm-cm. The first wide bandgap doped semiconductor layer 260 may also have a bandgap greater than 1.05 eV. Additionally, the semiconductor layer of the first wide bandgap may act as a heterojunction in regions of the rear surface of the solar cell to cover the first textured silicon region 230 and the second oxide layer 212.

The doped semiconductor layer 260 of the first wide bandgap may be 10% to 30% thicker than the doped semiconductor layer 262 of the second wide bandgap. In other embodiments, the thickness may vary by less than 10% or more than 30%, without departing from the techniques described herein. Both of the wide bandgap doped semiconductor layers 260 and 262 may be positively doped semiconductors, but in other embodiments with different substrates and polysilicon doped poles, the negatively doped wide bandgap A semiconductor layer can be used. Subsequently, an anti-reflective coating (ARC) 270 may be deposited over the doped semiconductor 262 of the second wide bandgap. In one embodiment, the anti-reflective coating 270 may be made of silicon nitride. In some embodiments, the ARC may also be deposited over the doped semiconductor layer 260 of the first wide bandgap.

Referring to FIG. 18, the doped semiconductor layer 260 and the second oxide layer 212 of the first wide bandgap are similar to those described above with reference to FIGS. It may be partially removed over the doped polysilicon layer 250 to form a series of contact openings. Subsequently, the first metal grid line 290 may be formed on the rear surface of the solar cell 200, and the first metal grid line 290 is electrically connected to the doped polysilicon 250 in the contact openings. Can be combined with The second metal grid line 292 may be formed on the rear surface of the solar cell 200, and the second metal grid line 292 is in the first textured silicon region or the N-type emitter region 230. Electrically coupled. In one embodiment, both the first and second metal grid lines may be formed at the same time. Subsequently, additional contact may be made to the first and second metal grid lines 290 and 292 by other components of the energy system including the solar cell 200.

While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are a very large number of variations. Further, it is to be understood that the exemplary embodiments or embodiments described herein are not intended to limit in any way the scope, applicability, or configuration of the claimed subject matter. Rather, the foregoing detailed description will provide those skilled in the art with convenient guidance for implementing the described embodiment or embodiments. It should be understood that various changes may be made to the function and arrangement of elements without departing from the scope defined by the claims, including known equivalents and predictable equivalents at the time of filing of this patent application.

Claims (12)

Silicon substrate;
An oxide layer disposed on the rear surface of the silicon substrate;
A first emitter region disposed on a rear surface of the silicon substrate and including a layer of a semiconductor doped with a wide bandgap of a first conductivity type disposed on the oxide layer;
A dielectric layer disposed on the rear surface of the silicon substrate;
A second emitter region disposed on a rear surface of the silicon substrate and including a doped polysilicon layer of a second conductivity type disposed on the dielectric layer; And
A solar cell comprising first and second contacts disposed on and electrically connected to each of the first and second emitter regions. The solar cell of claim 1, wherein the layer of the wide bandgap doped semiconductor further extends over a portion of the second emitter region. The method of claim 2, further comprising a material layer disposed between the doped polysilicon layer and a portion of the wide bandgap doped semiconductor extending over a portion of the second emitter region, wherein the material layer is a second conductive layer. A solar cell comprising a dopant of the type. The solar cell according to claim 3, wherein the second conductivity type dopant is a phosphorous dopant. The solar cell of claim 3, wherein the second conductivity type dopant is a boron dopant. The solar cell of claim 1, wherein the silicon substrate is N-type bulk silicon. The solar cell of claim 1, further comprising an antireflection coating on the wide bandgap doped semiconductor in the first emitter region. 8. The solar cell of claim 7, wherein the antireflective coating comprises silicon nitride. The solar cell of claim 1, further comprising a second layer of a wide bandgap doped semiconductor disposed on a front surface of the silicon substrate. 10. The solar cell of claim 9, wherein the second layer of the wide bandgap doped semiconductor comprises silicon carbide or aluminum gallium nitride. 10. The solar cell of claim 9, further comprising an antireflection layer disposed on the second layer of the wide bandgap doped semiconductor. The solar cell of claim 1, wherein the wide bandgap doped semiconductor comprises silicon carbide or aluminum gallium nitride.

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