WO2015122242A1 - Back-junction photoelectric conversion element and solar photovoltaic power generation system - Google Patents

Back-junction photoelectric conversion element and solar photovoltaic power generation system Download PDF

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Publication number
WO2015122242A1
WO2015122242A1 PCT/JP2015/051340 JP2015051340W WO2015122242A1 WO 2015122242 A1 WO2015122242 A1 WO 2015122242A1 JP 2015051340 W JP2015051340 W JP 2015051340W WO 2015122242 A1 WO2015122242 A1 WO 2015122242A1
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semiconductor layer
silicon substrate
photoelectric conversion
conversion element
amorphous semiconductor
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PCT/JP2015/051340
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French (fr)
Japanese (ja)
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和也 辻埜
神川　剛
真臣 原田
直城 小出
親扶 岡本
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シャープ株式会社
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
    • H02S10/00—PV power plants; Combinations of PV energy systems with other systems for the generation of electric power
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a back junction type photoelectric conversion element and a photovoltaic power generation system.
  • photoelectric conversion elements have attracted attention.
  • As the photoelectric conversion element there is a back contact type photoelectric conversion element.
  • the back junction type photoelectric conversion element is disclosed in, for example, JP-T-2012-519375. In this publication, irregularities are formed on the entire front and back surfaces.
  • the short-circuit current can be increased.
  • the open circuit voltage decreases. As a result, conversion efficiency may be reduced.
  • An object of the present invention is to provide a back junction type photoelectric conversion element capable of suppressing a decrease in open-circuit voltage and increasing conversion efficiency even when unevenness is formed on the back surface. .
  • a back junction photoelectric conversion element includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode.
  • the first semiconductor layer has a first conductivity type and is formed on the back side of the silicon substrate.
  • the second semiconductor layer has a second conductivity type opposite to the first conductivity type, and is formed on the back side of the silicon substrate.
  • the first electrode is formed in contact with the first semiconductor layer.
  • the second electrode is formed in contact with the second semiconductor layer. Irregularities are formed on the back surface of the silicon substrate and in the region where the first semiconductor layer is formed.
  • the average surface roughness Ra is 0.75 nm or less.
  • the back junction type photoelectric conversion element according to the embodiment of the present invention, it is possible to increase the conversion efficiency by suppressing the reduction of the open circuit voltage.
  • FIG. 2 is a cross-sectional view for explaining a method of manufacturing the back junction photoelectric conversion element shown in FIG. 1, in which an intrinsic amorphous semiconductor layer and an n-type amorphous semiconductor layer are formed on the entire light receiving surface of a silicon substrate.
  • FIG. 5 is a cross-sectional view showing a state in which an intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer are formed on a part of the back surface of the silicon substrate. It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 1, Comprising: The intrinsic
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of a back junction photoelectric conversion element according to Comparative Example 2.
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of a back junction photoelectric conversion element according to Comparative Example 3.
  • FIG. It is sectional drawing which shows an example of schematic structure of the back junction type photoelectric conversion element by the 2nd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG.
  • FIG. 8 Comprising: A texture structure is formed in the whole light-receiving surface of a silicon substrate, and unevenness
  • FIG. 9 is a cross-sectional view for explaining a manufacturing method of the back junction type photoelectric conversion element shown in FIG. 8 and showing a state in which an n-type diffusion region and a p-type diffusion region are formed on the back surface side of the silicon substrate. It is. It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG.
  • a back junction photoelectric conversion element includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode.
  • the first semiconductor layer has a first conductivity type and is formed on the back side of the silicon substrate.
  • the second semiconductor layer has a second conductivity type opposite to the first conductivity type, and is formed on the back side of the silicon substrate.
  • the first electrode is formed in contact with the first semiconductor layer.
  • the second electrode is formed in contact with the second semiconductor layer. Irregularities are formed on the back surface of the silicon substrate and in the region where the first semiconductor layer is formed.
  • the average surface roughness Ra is 0.75 nm or less.
  • the short circuit current can be increased by forming irregularities on the back surface of the silicon substrate. This is because light absorption increases when light on the long wavelength side is reflected and returned into the silicon substrate.
  • the back junction type photoelectric conversion element irregularities are formed in a region of the back surface of the silicon substrate where the first semiconductor layer in contact with the first electrode is formed. Therefore, the short circuit current can be increased.
  • the average surface roughness Ra is 0.75 nm or less in the region where the second semiconductor layer in contact with the second electrode is formed on the back surface of the silicon substrate.
  • the oxygen concentration at the interface between the silicon substrate and the second semiconductor layer is 1.2 ⁇ 10 20 cm ⁇ 3 or less. Therefore, surface recombination in the region can be reduced. As a result, it is possible to suppress a decrease in the open circuit voltage.
  • the average surface roughness Ra of the region where the second semiconductor layer in contact with the second electrode is formed on the back surface of the silicon substrate is 0.40 nm or less.
  • the oxygen concentration at the interface between the silicon substrate and the second semiconductor layer is 8 ⁇ 10 19 cm ⁇ 3 or less. As a result, surface recombination in the region can be further reduced.
  • the first semiconductor layer may be the first diffusion region
  • the second semiconductor layer may be the second diffusion region.
  • the first diffusion region is a region formed in the silicon substrate and in which the first conductivity type impurity is diffused.
  • the second diffusion region is a region formed in the silicon substrate and diffused with the second conductivity type impurity. Even with such a back junction type photoelectric conversion element, the conversion efficiency can be improved.
  • the back junction photoelectric conversion element may further include an intrinsic amorphous semiconductor layer.
  • the intrinsic amorphous semiconductor layer is formed in contact with the back surface of the silicon substrate and is made of an intrinsic amorphous semiconductor.
  • the first semiconductor layer is a first amorphous semiconductor layer
  • the second semiconductor layer is a second amorphous semiconductor layer.
  • the first amorphous semiconductor layer is formed in contact with the intrinsic amorphous semiconductor layer and is made of an amorphous semiconductor containing an impurity of the first conductivity type.
  • the second amorphous semiconductor layer is formed in contact with the intrinsic amorphous semiconductor layer and is made of an amorphous semiconductor containing a second conductivity type impurity. Even with such a back junction type photoelectric conversion element, the conversion efficiency can be improved.
  • the photoelectric conversion element 10 includes a silicon substrate 12, intrinsic amorphous semiconductor layers 14 and 16 as intrinsic amorphous semiconductor layers, an n-type amorphous semiconductor layer 18 as a first semiconductor layer, and a second semiconductor layer.
  • a p-type amorphous semiconductor layer 20 an electrode 22 as a first electrode, an electrode 24 as a second electrode, an intrinsic amorphous semiconductor layer 26, an n-type amorphous semiconductor layer 28, a reflection A prevention film 30.
  • the silicon substrate 12 is an n-type single crystal silicon substrate.
  • the thickness of the silicon substrate 12 is, for example, 100 to 300 ⁇ m.
  • the specific resistance of the silicon substrate 12 is, for example, 1.0 to 10.0 ⁇ ⁇ cm.
  • a texture structure 32 is formed on the light receiving surface of the silicon substrate 12. Thereby, the light incident on the silicon substrate 12 can be confined and the light use efficiency can be improved.
  • the plane orientation of the silicon substrate 12 is preferably (100). Thereby, formation of the texture structure 32 becomes easy.
  • the light receiving surface of the silicon substrate 12 is covered with an intrinsic amorphous semiconductor layer 26.
  • the intrinsic amorphous semiconductor layer 26 is made of, for example, i-type amorphous silicon (a-Si).
  • the thickness of the intrinsic amorphous semiconductor layer 26 is, for example, 2 to 25 nm.
  • the intrinsic amorphous semiconductor layer 26 is covered with an n-type amorphous semiconductor layer 28.
  • the n-type amorphous semiconductor layer 28 is made of, for example, amorphous silicon containing an n-type impurity (for example, phosphorus).
  • the thickness of the n-type amorphous semiconductor layer 28 is, for example, 2 to 50 nm.
  • the n-type amorphous semiconductor layer 28 is covered with an antireflection film 30.
  • the antireflection film 30 is made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. In consideration of passivation of the surface of the n-type amorphous semiconductor layer 28, the antireflection film 30 is preferably made of silicon nitride or silicon oxynitride. The thickness of the antireflection film 30 is, for example, 80 to 300 nm.
  • the back surface of the silicon substrate 12 is covered with intrinsic amorphous semiconductor layers 14 and 16.
  • the intrinsic amorphous semiconductor layers 14 and 16 are made of, for example, i-type amorphous silicon (a-Si).
  • the intrinsic amorphous semiconductor layer 14 is formed on a part of the back surface of the silicon substrate 12.
  • the intrinsic amorphous semiconductor layer 16 is formed adjacent to the region where the intrinsic amorphous semiconductor layer 14 is formed on the back surface of the silicon substrate 12. That is, the intrinsic amorphous semiconductor layers 14 and 16 are formed on the entire back surface of the silicon substrate 12.
  • the intrinsic amorphous semiconductor layers 14 and 16 have a thickness of 2 to 10 nm, for example.
  • the n-type amorphous semiconductor layer 18 is made of amorphous silicon containing an n-type impurity (for example, phosphorus).
  • the thickness of the n-type amorphous semiconductor layer 18 is, for example, 2 to 50 nm.
  • the p-type amorphous semiconductor layer 20 is made of amorphous silicon containing a p-type impurity (for example, boron).
  • the thickness of the p-type amorphous semiconductor layer 20 is, for example, 2 to 50 nm.
  • the electrode 22 is formed in contact with the n-type amorphous semiconductor layer 18. Thereby, the electrode 22 is electrically connected to the n-type amorphous semiconductor layer 18.
  • the electrode 22 includes a transparent conductive layer 22A and a metal layer 22B.
  • the transparent conductive layer 22A is formed in contact with the n-type amorphous semiconductor layer 18.
  • the transparent conductive layer 22A is made of indium tin oxide (ITO), for example.
  • the metal layer 22B is formed in contact with the transparent conductive layer 22A.
  • the metal layer 22B is made of, for example, silver.
  • the electrode 24 is formed in contact with the p-type amorphous semiconductor layer 20. Thereby, the electrode 24 is electrically connected to the p-type amorphous semiconductor layer 20.
  • the electrode 24 includes a transparent conductive layer 24A and a metal layer 24B.
  • the transparent conductive layer 24 ⁇ / b> A is formed in contact with the p-type amorphous semiconductor layer 20.
  • the transparent conductive layer 24A is made of indium tin oxide (ITO), for example.
  • the metal layer 24B is formed in contact with the transparent conductive layer 24A.
  • the metal layer 24B is made of silver, for example.
  • irregularities 34 are formed in a region overlapping the n-type amorphous semiconductor layer 18 on the back surface of the silicon substrate 12. Therefore, on the surface of the intrinsic amorphous semiconductor layer 14, irregularities 34 ⁇ / b> A corresponding to the irregularities 34 formed on the back surface of the silicon substrate 12 are formed. Further, on the surface of the n-type amorphous semiconductor layer 18, irregularities 34 ⁇ / b> B corresponding to the irregularities 34 formed on the back surface of the silicon substrate 12 are formed.
  • the unevenness 34 has, for example, a texture structure.
  • the unevenness 34 may have regularity or may be random.
  • the height difference of the unevenness 34 may be the same as or different from the height difference of the texture structure 32.
  • the ratio of the formation region of the unevenness 34 to the entire back surface of the silicon substrate 12 is preferably 20 to 80%. In this case, the short circuit current can be increased.
  • the height difference of the irregularities 34 is preferably 1 to 10 ⁇ m. In this case, the short circuit current can be increased.
  • the average surface roughness Ra of the region where the irregularities 34 are not formed on the back surface of the silicon substrate 12 is 0.75 nm or less, and preferably 0.40 nm or less.
  • the average surface roughness Ra is an index for quantifying the surface unevenness (height difference) measured by an atomic force microscope (AFM), and is defined by the following equation.
  • Z (i) is a height difference (surface height) at a certain measurement point
  • Ze is an average value of the height difference (surface height).
  • Ra is defined as described above. However, even if “the average surface roughness Ra of the region where the unevenness 34 is not formed is 0.75 nm or less” is described, the unevenness In all the regions where 34 is not formed, Ra is not completely 0.75 nm or less. For example, there may be a case where a part of the abnormality is formed. However, the abnormal part is very small in area. Therefore, the effects described in the embodiments of the present invention are not affected. Even if the average surface roughness Ra of the region where the unevenness 34 is not formed is described as 0.75 nm or less, the average surface roughness is 90% or more of the total area of the region where the unevenness 34 is not formed. If is within the stated range, there will be no problem.
  • a silicon substrate 12 having a texture structure 32 on the entire light-receiving surface and having irregularities 34 on a part of the back surface is prepared. Specifically, it is as follows.
  • the average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate to be obtained later varies depending on the mixing ratio of the hydrofluoric acid solution and the processing time.
  • hydrofluoric acid for example, hydrofluoric acid (HF) is 8.3% by weight, nitric acid (HNO 3 ) is 50.0%, and water (H 2 O) is 41.7% by weight. .
  • the etching time is, for example, 1 minute.
  • a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon oxide film is patterned by photolithography.
  • the silicon oxide film remains only on a part of the back surface of the silicon substrate.
  • the silicon substrate is wet etched.
  • the texture structure 32 is formed on the entire light receiving surface, and the unevenness 34 is formed on a part of the back surface.
  • the solution used for the wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water.
  • KOH potassium hydroxide
  • IPA isopropyl alcohol
  • the proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight.
  • the proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight.
  • the temperature of the solution is, for example, 80 to 90 ° C.
  • the etching time is, for example, 10 to 60 minutes.
  • the texture 32 on the light receiving surface and the unevenness on the back surface are formed at the same time.
  • they can be formed separately as follows.
  • a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon substrate is wet etched.
  • the texture structure 32 is formed in the whole light-receiving surface.
  • the solution used for wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water.
  • KOH potassium hydroxide
  • IPA isopropyl alcohol
  • the proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight.
  • the proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight.
  • the temperature of the solution is, for example, 80 to 90 ° C.
  • the etching time is, for example, 10 to 60 minutes.
  • a silicon oxide film is formed on the light receiving surface of the silicon substrate on which the texture structure 32 is formed by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon oxide film on the back surface is patterned by photolithography.
  • the silicon oxide film remains only on a part of the light receiving surface and the back surface of the silicon substrate.
  • the silicon substrate is wet etched.
  • corrugation 34 is formed in a part of back surface.
  • the solution used for wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water.
  • the proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight.
  • the proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight.
  • the temperature of the solution is, for example, 80 to 90 ° C.
  • the etching time is, for example, 10 to 60 minutes.
  • the conditions of the composition, concentration, temperature, and time of the solution at this time may be the same as those in the above-described wet etching of the light receiving surface, but may be different. If they are different, irregularities different from the texture of the light receiving surface can be formed.
  • the texture structure 32 formed on the entire light receiving surface and the unevenness 34 formed on a part of the back surface it remains on a part of the back surface of the silicon substrate 12 or a part of the light receiving surface and the back surface.
  • the silicon oxide film is removed by wet etching using 5.2 wt% hydrofluoric acid. Thereby, the target silicon substrate 12 is obtained.
  • the average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate is 0.26 nm.
  • an intrinsic amorphous semiconductor layer 26 and an n-type amorphous semiconductor layer 28 are formed on the light receiving surface of the silicon substrate 12, and intrinsic non-existence is formed on a part of the back surface of the silicon substrate 12.
  • a crystalline semiconductor layer 16 and a p-type amorphous semiconductor layer 20 are formed. Specifically, it is as follows.
  • the intrinsic amorphous semiconductor layer 26 and the n-type amorphous semiconductor layer 28 are formed on the light receiving surface of the silicon substrate 12.
  • the intrinsic amorphous semiconductor layer 26 and the n-type amorphous semiconductor layer 28 can be formed by, for example, a plasma CVD method.
  • an intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer are formed on the back surface of the silicon substrate 12.
  • the intrinsic amorphous semiconductor layer and the p-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method.
  • the intrinsic amorphous semiconductor layer and the p-type amorphous semiconductor layer are patterned by photolithography. As a result, the region where the irregularities 34 are formed is exposed on the back surface of the silicon substrate 12, and the other region is covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20.
  • the intrinsic amorphous semiconductor layer 14 and the region not covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20 on the back surface of the silicon substrate 12 are formed.
  • An n-type amorphous semiconductor layer 18 is formed. Specifically, it is as follows.
  • an intrinsic amorphous semiconductor layer and an n-type amorphous semiconductor layer that cover the back surface of the silicon substrate 12 and the p-type amorphous semiconductor layer 20 are formed.
  • the intrinsic amorphous semiconductor layer and the n-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method.
  • the intrinsic amorphous semiconductor layer and the n-type amorphous semiconductor layer are patterned by photolithography.
  • the intrinsic amorphous semiconductor layer 14 and the n-type amorphous semiconductor layer are formed on the back surface of the silicon substrate 12 in a region not covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20. 18 is formed.
  • an antireflection film 30 is formed on the n-type amorphous semiconductor layer 28.
  • the antireflection film 30 can be formed by, for example, a plasma CVD method.
  • electrodes 22 and 24 are formed as shown in FIG. 2E. Specifically, it is as follows.
  • a transparent conductive layer covering the n-type amorphous semiconductor layer 18 and the p-type amorphous semiconductor layer 20 is formed.
  • the transparent conductive layer can be formed by sputtering, for example.
  • the metal layer can be formed by sputtering or vapor deposition, for example.
  • the transparent conductive layer and the metal layer are patterned by photolithography. Thereby, the electrodes 22 and 24 are formed, and the target photoelectric conversion element 10 is obtained.
  • FIG. 3 shows a photoelectric conversion element 10A according to an application example of the first embodiment.
  • unevenness 34 is formed in a region of the back surface of the silicon substrate 12 where the p-type amorphous semiconductor layer 20 overlaps when viewed from the thickness direction of the silicon substrate 12.
  • the average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate 12 is 0.75 nm or less. Also in the photoelectric conversion element 10A, as in the first embodiment, it is possible to improve conversion efficiency while suppressing a decrease in open-circuit voltage.
  • the photoelectric conversion characteristics of the photoelectric conversion element 10 according to the first embodiment and the photoelectric conversion element 10A according to the application example of the first embodiment were evaluated using a solar simulator.
  • a photoelectric conversion element (Example 1) having an average surface roughness Ra of 0.26 nm and a photoelectric conversion element (average surface roughness Ra of 0.40 nm) ( Example 2), a photoelectric conversion element (Example 3) having an average surface roughness Ra of 0.53 nm, a photoelectric conversion element (Example 4) having an average surface roughness Ra of 0.75 nm, and an average surface A photoelectric conversion element (Comparative Example 1) having a roughness Ra of 1.02 nm was prepared.
  • a photoelectric conversion element (Example 5) having an average surface roughness Ra of 0.26 nm was prepared.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid was 8.3% by weight for hydrofluoric acid (HF), 50.0% for nitric acid (HNO 3 ), and 41.7% by weight for water (H 2 O).
  • the etching time was 1 minute.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid is 3.9% by weight for hydrofluoric acid (HF) and 55% for nitric acid (HNO 3 ). . 3% and water (H 2 O) was 40.8% by weight.
  • the etching time was 2 minutes.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid was 2.0% by weight for hydrofluoric acid (HF), 57.6% for nitric acid (HNO 3 ), and 40.4% by weight for water (H 2 O).
  • the etching time was 3 minutes.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid was 0.4% by weight for hydrofluoric acid (HF), 59.5% for nitric acid (HNO 3 ), and 40.1% by weight for water (H 2 O).
  • the etching time was 5 minutes.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid was 0.3% by weight for hydrofluoric acid (HF), 43.8% for nitric acid (HNO 3 ), and 55.9% by weight for water (H 2 O).
  • the etching time was 30 minutes.
  • the concentration profile of oxygen atoms in the vicinity of the interface between the intrinsic amorphous semiconductor layer and the silicon substrate was measured using SIMS (Secondary Ion Mass Spectrometer). .
  • FIG. 4 shows oxygen atom concentration profiles of Example 2 and Example 4 measured by SIMS.
  • the concentration of oxygen atoms had a peak at the interface between the intrinsic amorphous semiconductor layer and the silicon substrate.
  • the oxygen concentration also had a peak at the interface in the other examples and comparative examples.
  • the relationship between the value of the oxygen concentration at the peak and the average surface roughness Ra of the substrate is shown in FIG. As shown in FIG. 5, the oxygen concentration was low when Ra was small. When Ra was 0.75 nm or less, the oxygen concentration was 1.2 ⁇ 10 20 cm ⁇ 3 or less, and particularly when Ra was 0.40 nm or less, the oxygen concentration was lowered to 8 ⁇ 10 19 cm ⁇ 3 or less.
  • the photoelectric conversion characteristics of the photoelectric conversion elements shown in FIGS. 6 and 7 were evaluated.
  • the unevenness 34 is not formed on the back surface of the silicon substrate 12 as compared with the photoelectric conversion element 10.
  • the average surface roughness Ra of the back surface was 0.26 nm.
  • the photoelectric conversion element 70 shown in FIG. 7, as compared with the photoelectric conversion element 10, the unevenness 34 was formed on the entire back surface.
  • the cell area was 2 cm ⁇ 2 cm. Irradiation light was light equivalent to AM1.5.
  • Table 1 shows the evaluation results. In Table 1, the case of Comparative Example 2 is standardized.
  • Example 4 As can be seen from Table 1, in Examples 1 to 5, compared to Comparative Example 1, since the decrease in open-circuit voltage was suppressed, the conversion efficiency was improved. In Example 4, the conversion efficiency was improved as compared with Comparative Example 1. In Example 3, since the average surface roughness Ra was smaller than that in Example 4, the conversion efficiency was further improved. In Example 2, since the average surface roughness Ra was smaller than that in Example 3, the conversion efficiency was further improved. In Example 1, since the average surface roughness Ra was smaller than that in Example 2, the conversion efficiency was further improved.
  • the photoelectric conversion element 50 includes a silicon substrate 52, an antireflection film 54, a passivation film 56, a passivation film 58, an electrode 60, and an electrode 62.
  • the silicon substrate 52 is an n-type single crystal silicon substrate.
  • the thickness and specific resistance of the silicon substrate 52 are the same as those of the silicon substrate 12.
  • a texture structure 68 is formed on the light receiving surface of the silicon substrate 52.
  • the silicon substrate 52 includes an n-type diffusion region 64 as a first semiconductor layer and a p-type diffusion region 66 as a second semiconductor layer.
  • the impurity concentration of the n-type diffusion region 64 is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the depth dimension (vertical dimension in FIG. 8) of the n-type diffusion region 64 is, for example, 0.3 to 1.0 ⁇ m.
  • the impurity concentration of the p-type diffusion region 66 is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the depth dimension (vertical dimension in FIG. 8) of the p-type diffusion region 66 is, for example, 0.3 to 1.0 ⁇ m.
  • the light receiving surface of the silicon substrate 52 is covered with an antireflection film 54.
  • the antireflection film 54 is, for example, a silicon nitride film.
  • the thickness of the silicon nitride film is, for example, 80 to 300 nm.
  • the passivation film 56 is formed in contact with the p-type diffusion region 66.
  • the region where the p-type diffusion region 56 is formed on the back surface of the silicon substrate 52 is covered with the passivation 56.
  • the passivation film 56 is, for example, a silicon nitride film or a silicon oxynitride film.
  • the thickness of the passivation film 56 is, for example, 5 to 100 nm.
  • the passivation film 58 is formed in contact with the n-type diffusion region 64.
  • the region excluding the region where the p-type diffusion region 56 is formed on the back surface of the silicon substrate 52 is covered with the passivation 58.
  • the passivation film 58 is, for example, a silicon nitride film or a silicon oxynitride film.
  • the thickness of the passivation film 58 is, for example, 10 to 200 nm.
  • the electrode 60 is formed in contact with the n-type diffusion region 64. As a result, the electrode 60 is electrically connected to the n-type diffusion region 64.
  • the electrode 60 is made of, for example, silver.
  • the electrode 62 is formed in contact with the p-type diffusion region 66. Thereby, the electrode 62 is electrically connected to the p-type diffusion region 66.
  • the electrode 62 is made of silver, for example.
  • unevenness 70 is formed in a region other than the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate 52.
  • the unevenness 70 has, for example, a texture structure.
  • the unevenness 70 may have regularity or may be random.
  • the height difference of the unevenness 70 may be the same as or different from the height difference of the texture structure 68.
  • the ratio of the formation region of the unevenness 70 to the entire back surface of the silicon substrate 52 is preferably 20 to 80%. In this case, the short circuit current can be increased.
  • the height difference of the unevenness 70 is preferably 1 to 10 ⁇ m. In this case, the short circuit current can be increased.
  • the average surface roughness Ra of the region where the p-type diffusion region 66 is formed is 0.75 nm or less, and preferably 0.40 nm or less.
  • a silicon substrate 52 having a texture structure 68 on the entire light receiving surface and having irregularities 70 on a part of the back surface is prepared. Specifically, it is as follows.
  • a silicon substrate having a predetermined thickness is prepared by the method described in the first embodiment.
  • a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon oxide film is patterned by photolithography.
  • the silicon oxide film remains only on a part of the back surface of the silicon substrate.
  • the region where the silicon oxide film remains is a region where the p-type diffusion region 66 is formed later.
  • the silicon substrate is wet etched. Thereby, the texture structure 68 is formed on the entire light receiving surface, and the unevenness 70 is formed on a part of the back surface.
  • the texture 32 on the light receiving surface and the unevenness on the back surface are formed at the same time.
  • they can be formed separately as follows.
  • a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon substrate is wet etched. Thereby, the texture structure 32 is formed in the whole light-receiving surface.
  • a silicon oxide film is formed on the light receiving surface of the silicon substrate on which the texture structure 32 is formed by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon oxide film on the back surface is patterned by photolithography. As a result, the silicon oxide film remains only on a part of the light receiving surface and the back surface of the silicon substrate. At this time, the region where the silicon oxide film remains on the back surface is a region where the p-type diffusion region 66 is formed later. In this state, the silicon substrate is wet etched. Thereby, the unevenness
  • the conditions of the composition, concentration, temperature, and time of the solution at this time may be the same as those in the above-described wet etching of the light receiving surface, but may be different. If they are different, irregularities different from the texture of the light receiving surface can be formed.
  • an n-type diffusion region 64 and a p-type diffusion region 66 are formed on the back side of the silicon substrate 52. Specifically, it is as follows.
  • a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52.
  • an etching paste is printed on the silicon oxide film formed on the back surface of the silicon substrate 52.
  • Examples of a method for printing the etching paste include a screen printing method.
  • the silicon substrate 52 on which the etching paste is printed is heated. As a result, only the portion where the etching paste is printed is removed from the silicon oxide film formed on the back surface of the silicon substrate 52. Thereafter, the silicon substrate 52 is immersed in water and subjected to ultrasonic cleaning or the like. Thereby, the etching paste is removed.
  • boron as a p-type impurity is vapor-phase diffused.
  • a p-type diffusion region 66 is formed in a portion of the silicon substrate 52 that is not covered with the silicon oxide film.
  • the silicon oxide film formed on the light receiving surface and the back surface of the silicon substrate 52 and the BSG (Boron Silicate Glass) film formed by vapor-diffusing boron are removed using an aqueous hydrogen fluoride solution or the like.
  • the hydrogen fluoride aqueous solution at this time for example, a 5.2 wt% hydrofluoric acid aqueous solution can be used.
  • a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52.
  • the silicon oxide film formed on the back surface of the silicon substrate 52 is etched.
  • an etching method for example, there is a method using an etching paste.
  • phosphorus as an n-type impurity is vapor-phase diffused.
  • an n-type diffusion region 64 is formed in a portion of the silicon substrate 52 that is not covered with the silicon oxide film.
  • the silicon oxide film formed on the light receiving surface and the back surface of the silicon substrate 52, the PSG (Phosphorus Silicate Glass) film formed by vapor phase diffusion of phosphorus, and the like are removed using a hydrogen fluoride aqueous solution or the like.
  • a hydrogen fluoride aqueous solution for example, a 5.2 wt% hydrofluoric acid aqueous solution can be used.
  • the average surface roughness Ra of the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate is 0.75 nm or less.
  • the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate 52 is covered with the passivation film 56, and the other region is covered with the passivation film 58. Specifically, it is as follows.
  • a thermal oxidation process is performed on the silicon substrate 52.
  • a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52.
  • the silicon oxide film formed on the back surface of the silicon substrate 52 is etched.
  • an etching method for example, there is a method using an etching paste.
  • a passivation film 58 that covers the back surface of the silicon substrate 52 and the passivation film 56 is formed.
  • the passivation film 58 can be formed by, for example, a plasma CVD method.
  • the silicon oxide film formed on the light receiving surface of the silicon substrate 52 is removed using a hydrogen fluoride aqueous solution or the like. 9C, the light receiving surface of the silicon substrate 52 is exposed, and the back surface of the silicon substrate 52 is covered with the passivation films 56 and 58.
  • an antireflection film 54 is formed on the light receiving surface of the silicon substrate 52.
  • the antireflection film 54 can be formed by, for example, a plasma CVD method or the like.
  • electrodes 60 and 62 are formed. Specifically, it is as follows.
  • a part of the passivation films 56 and 58 is removed by etching to form a contact hole.
  • the etching method include a method using an etching paste.
  • the average surface roughness Ra of the region where the n-type diffusion region 64 is formed in the back surface of the silicon substrate 52 is 0.75 nm, and the region where the n-type diffusion region 64 is formed in the back surface of the silicon substrate 52
  • the unevenness 70 may be formed in a region other than the above.
  • the photoelectric conversion element according to the embodiment of the present invention has high conversion efficiency. Therefore, the photoelectric conversion module and the photovoltaic power generation system including the photoelectric conversion element according to the embodiment of the present invention can also have high conversion efficiency.
  • FIG. 10 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module according to the present embodiment.
  • the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1013 and 1014.
  • a plurality of photoelectric conversion elements 1001 are arranged in an array and connected in series.
  • FIG. 10 an arrangement in which the photoelectric conversion elements 1001 are connected in series is illustrated, but the arrangement and connection method are not limited thereto, and the photoelectric conversion elements 1001 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement.
  • the photoelectric conversion element according to the embodiment of the present invention is used for each of the plurality of photoelectric conversion elements 1001, the photoelectric conversion element according to the embodiment of the present invention is used. Note that the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 can be any integer of 2 or more.
  • the cover 1002 is composed of a weatherproof cover and covers the plurality of photoelectric conversion elements 1001.
  • the output terminal 1013 is connected to a photoelectric conversion element 1001 arranged at one end of a plurality of photoelectric conversion elements 1001 connected in series.
  • the output terminal 1014 is connected to the photoelectric conversion element 1001 arranged at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
  • FIG. 11 is a schematic diagram illustrating an example of the configuration of the photovoltaic power generation system according to the present embodiment.
  • solar power generation system 2000 includes a photoelectric conversion module array 2001, a connection box 2002, a power conditioner 2003, a distribution board 2004, and a power meter 2005.
  • the photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000.
  • the solar power generation system 2000 can be added with a function generally called “Home Energy Management System (HEMS)”. As a result, it is possible to contribute to power saving for each individual house while monitoring the power usage status of each room.
  • HEMS Home Energy Management System
  • connection box 2002 is connected to the photoelectric conversion module array 2001.
  • the power conditioner 2003 is connected to the connection box 2002.
  • the distribution board 2004 is connected to the power conditioner 2003 and the electrical equipment 2011.
  • the power meter 2005 is connected to the distribution board 2004 and the grid connection.
  • the photoelectric conversion module array 2001 generates sunlight by converting sunlight into electricity, and supplies the DC power to the connection box 2002.
  • connection box 2002 receives DC power generated by the photoelectric conversion module array 2001 and supplies DC power to the power conditioner 2003.
  • the power conditioner 2003 converts the DC power received from the connection box 2002 into AC power and supplies it to the distribution board 2004.
  • a part of the DC power received from the connection box 2002 may be supplied to the distribution board 2004 as it is without being converted into AC power.
  • Distribution board 2004 supplies at least one of AC power received from power conditioner 2003 and commercial power received via power meter 2005 to electrical equipment 2011.
  • the distribution board 2004 supplies the AC power received from the power conditioner 2003 to the electrical equipment 2011 when the AC power received from the power conditioner 2003 is larger than the power consumption of the electrical equipment 2011.
  • the distribution board 2004 supplies the surplus AC power to the grid connection via the power meter 2005.
  • the distribution board 2004 uses the AC power received from the grid connection and the AC power received from the power conditioner 2003 to the electrical equipment. To 2011.
  • the power meter 2005 measures the power in the direction from the grid connection to the distribution board 2004 and measures the power in the direction from the distribution board 2004 to the grid connection.
  • FIG. 12 is a schematic diagram showing an example of the configuration of the photoelectric conversion module array 2001 shown in FIG. Referring to FIG. 12, photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 and output terminals 2013 and 2014.
  • the plurality of photoelectric conversion modules 1000 are arranged in an array and connected in series.
  • FIG. 12 illustrates an arrangement in which the photoelectric conversion modules 1000 are connected in series, the arrangement and connection method are not limited to this, and the photoelectric conversion modules 1000 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement.
  • the number of photoelectric conversion modules 1000 included in the photoelectric conversion module array 2001 can be any integer of 2 or more.
  • the output terminal 2013 is connected to the photoelectric conversion module 1000 located at one end of the plurality of photoelectric conversion modules 1000 connected in series.
  • the output terminal 2014 is connected to the photoelectric conversion module 1000 located at the other end of the plurality of photoelectric conversion modules 1000 connected in series.
  • the solar power generation system of the present embodiment is not limited to the above description as long as it includes the photoelectric conversion element according to the embodiment of the present invention, and can take any configuration.
  • FIG. 13 is a schematic diagram illustrating another example of the configuration of the photovoltaic power generation system.
  • the photovoltaic power generation system shown in FIG. 13 is a larger scale photovoltaic power generation system than the photovoltaic power generation system shown in FIG.
  • the photovoltaic power generation system shown in FIG. 13 also includes the photoelectric conversion element according to the embodiment of the present invention.
  • solar power generation system 4000 includes a plurality of subsystems 4001, a plurality of power conditioners 4003, and a transformer 4004.
  • the plurality of power conditioners 4003 are each connected to the subsystem 4001.
  • the number of the power conditioners 4003 and the subsystems 4001 connected thereto can be any integer of 2 or more.
  • the transformer 4004 is connected to a plurality of power conditioners 4003 and grid interconnection.
  • Each of the plurality of subsystems 4001 includes a plurality of module systems 3000.
  • the number of module systems 3000 in the subsystem 4001 can be any integer greater than or equal to two.
  • Each of the plurality of module systems 3000 includes a plurality of photoelectric conversion module arrays 2001, a plurality of connection boxes 3002, and a current collection box 3004.
  • the number of the junction box 3002 in the module system 3000 and the photoelectric conversion module array 2001 connected to the junction box 3002 can be any integer of 2 or more.
  • the current collection box 3004 is connected to a plurality of connection boxes 3002.
  • the power conditioner 4003 is connected to a plurality of current collection boxes 3004 in the subsystem 4001.
  • the plurality of photoelectric conversion module arrays 2001 of the module system 3000 convert sunlight into electricity to generate DC power, and supply the DC power to the current collection box 3004 via the connection box 3002.
  • a plurality of current collection boxes 3004 in the subsystem 4001 supplies DC power to the power conditioner 4003.
  • the plurality of power conditioners 4003 convert DC power into AC power and supply the AC power to the transformer 4004.
  • the transformer 4004 converts the voltage level of AC power received from the plurality of power conditioners 4003 and supplies it to the grid interconnection.
  • the photovoltaic power generation system 4000 only needs to include the photoelectric conversion element according to the embodiment of the present invention, and all the photoelectric conversion elements included in the photovoltaic power generation system 4000 are the photoelectric conversion elements according to the embodiment of the present invention. Not necessarily. For example, all of the photoelectric conversion elements included in one subsystem 4001 are the photoelectric conversion elements according to the embodiment of the present invention, and part or all of the photoelectric conversion elements included in another subsystem 4001 are the implementation of the present invention. In some cases, the photoelectric conversion element may not be a photoelectric conversion element.

Abstract

Provided is a back-junction photoelectric conversion element which is capable of increasing the conversion efficiency by suppressing decrease of the open circuit voltage even in cases where the back surface thereof is provided with recesses and projections. This photoelectric conversion element (10) is provided with a silicon substrate (12), a first semiconductor layer (18), a second semiconductor layer (20), a first electrode (22) and a second electrode (24). The first semiconductor layer (18) has a first conductivity type, and is formed on the back surface side of the silicon substrate (12). The second semiconductor layer (20) has a second conductivity type that is opposite to the first conductivity type, and is formed on the back surface side of the silicon substrate (12). The first electrode (22) is formed in contact with the first semiconductor layer (18). The second electrode (24) is formed in contact with the second semiconductor layer (20). A region of the back surface of the silicon substrate (12), where the first semiconductor layer (18) is formed, is provided with recesses and projections. Another region of the back surface of the silicon substrate (12), where the second semiconductor layer (20) is formed, has an average surface roughness (Ra) of 0.75 nm or less.

Description

裏面接合型の光電変換素子および太陽光発電システムBack junction type photoelectric conversion element and photovoltaic power generation system
　本発明は、裏面接合型の光電変換素子および太陽光発電システムに関する。 The present invention relates to a back junction type photoelectric conversion element and a photovoltaic power generation system.
　近年、光電変換素子が注目されている。光電変換素子には、裏面接合型の光電変換素子がある。 In recent years, photoelectric conversion elements have attracted attention. As the photoelectric conversion element, there is a back contact type photoelectric conversion element.
　裏面接合型の光電変換素子は、例えば、特表２０１２－５１９３７５号公報に開示されている。この公報では、表面及び裏面の全体に凹凸が形成されている。 The back junction type photoelectric conversion element is disclosed in, for example, JP-T-2012-519375. In this publication, irregularities are formed on the entire front and back surfaces.
　裏面接合型の光電変換素子では、裏面に凹凸を形成すると、短絡電流を増加させることができる。しかしながら、裏面に凹凸を形成すると、開放電圧が低下する。その結果、変換効率が低下するおそれがある。 In the back junction type photoelectric conversion element, when unevenness is formed on the back surface, the short-circuit current can be increased. However, when unevenness is formed on the back surface, the open circuit voltage decreases. As a result, conversion efficiency may be reduced.
　本発明の目的は、裏面に凹凸を形成する場合であっても、開放電圧が低下するのを抑えて、変換効率を増加させることができる、裏面接合型の光電変換素子を提供することにある。 An object of the present invention is to provide a back junction type photoelectric conversion element capable of suppressing a decrease in open-circuit voltage and increasing conversion efficiency even when unevenness is formed on the back surface. .
　本発明の実施の形態による裏面接合型の光電変換素子は、シリコン基板と、第１半導体層と、第２半導体層と、第１電極と、第２電極とを備える。第１半導体層は、第１導電型を有し、シリコン基板の裏面側に形成される。第２半導体層は、第１導電型とは反対の第２導電型を有し、シリコン基板の裏面側に形成される。第１電極は、第１半導体層に接して形成される。第２電極は、第２半導体層に接して形成される。シリコン基板の裏面であって、且つ、第１半導体層が形成された領域には、凹凸が形成される。シリコン基板の裏面であって、且つ、第２半導体層が形成された領域では、平均面粗さＲａが０．７５ｎｍ以下である。 A back junction photoelectric conversion element according to an embodiment of the present invention includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer has a first conductivity type and is formed on the back side of the silicon substrate. The second semiconductor layer has a second conductivity type opposite to the first conductivity type, and is formed on the back side of the silicon substrate. The first electrode is formed in contact with the first semiconductor layer. The second electrode is formed in contact with the second semiconductor layer. Irregularities are formed on the back surface of the silicon substrate and in the region where the first semiconductor layer is formed. On the back surface of the silicon substrate and in the region where the second semiconductor layer is formed, the average surface roughness Ra is 0.75 nm or less.
　本発明の実施の形態による裏面接合型の光電変換素子においては、開放電圧が低下するのを抑えて、変換効率を増加させることができる。 In the back junction type photoelectric conversion element according to the embodiment of the present invention, it is possible to increase the conversion efficiency by suppressing the reduction of the open circuit voltage.
本発明の第１の実施の形態による裏面接合型の光電変換素子の概略構成の一例を示す断面図である。It is sectional drawing which shows an example of schematic structure of the back junction type photoelectric conversion element by the 1st Embodiment of this invention. 図１に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の受光面の全体にテクスチャ構造が形成され、且つ、シリコン基板の裏面の一部に凹凸が形成された状態を示す断面図である。It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 1, Comprising: A texture structure is formed in the whole light-receiving surface of a silicon substrate, and unevenness | corrugation is formed in a part of back surface of a silicon substrate. It is sectional drawing which shows the state in which was formed. 図１に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の受光面の全体に真性非晶質半導体層及びｎ型非晶質半導体層が形成され、且つ、シリコン基板の裏面の一部に真性非晶質半導体層及びｐ型非晶質半導体層が形成された状態を示す断面図である。FIG. 2 is a cross-sectional view for explaining a method of manufacturing the back junction photoelectric conversion element shown in FIG. 1, in which an intrinsic amorphous semiconductor layer and an n-type amorphous semiconductor layer are formed on the entire light receiving surface of a silicon substrate. FIG. 5 is a cross-sectional view showing a state in which an intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer are formed on a part of the back surface of the silicon substrate. 図１に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の裏面のうち、真性非晶質半導体層及びｐ型非晶質半導体層が形成された領域を除いた領域に対して、真性非晶質半導体層及びｎ型非晶質半導体層が形成された状態を示す断面図である。It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 1, Comprising: The intrinsic | native amorphous semiconductor layer and the p-type amorphous semiconductor layer were formed among the back surfaces of a silicon substrate. It is sectional drawing which shows the state in which the intrinsic | native amorphous semiconductor layer and the n-type amorphous semiconductor layer were formed with respect to the area | region except the area | region. 図１に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の受光面側に反射防止膜が形成された状態を示す断面図である。It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 1, Comprising: It is sectional drawing which shows the state in which the antireflection film was formed in the light-receiving surface side of a silicon substrate. 図１に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の裏面側に電極が形成された状態を示す断面図である。It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 1, Comprising: It is sectional drawing which shows the state in which the electrode was formed in the back surface side of the silicon substrate. 本発明の第１の実施の形態の応用例に係る裏面接合型の光電変換素子の概略構成の一例を示す断面図である。It is sectional drawing which shows an example of schematic structure of the back junction type photoelectric conversion element which concerns on the application example of the 1st Embodiment of this invention. 本発明の第１の実施の形態におけるシリコン基板と真性非晶質半導体層との界面付近の酸素濃度のプロファイルを示すグラフである。It is a graph which shows the profile of the oxygen concentration of the interface vicinity of the silicon substrate and intrinsic amorphous semiconductor layer in the 1st Embodiment of this invention. 本発明の第１の実施の形態におけるシリコン基板と真性非晶質半導体層との界面における酸素濃度のピーク値と平均面粗さＲａとの関係を示すグラフである。It is a graph which shows the relationship between the peak value of oxygen concentration in the interface of the silicon substrate and intrinsic amorphous semiconductor layer in 1st Embodiment of this invention, and average surface roughness Ra. 比較例２に係る裏面接合型の光電変換素子の概略構成を示す断面図である。10 is a cross-sectional view illustrating a schematic configuration of a back junction photoelectric conversion element according to Comparative Example 2. FIG. 比較例３に係る裏面接合型の光電変換素子の概略構成を示す断面図である。10 is a cross-sectional view illustrating a schematic configuration of a back junction photoelectric conversion element according to Comparative Example 3. FIG. 本発明の第２の実施の形態による裏面接合型の光電変換素子の概略構成の一例を示す断面図である。It is sectional drawing which shows an example of schematic structure of the back junction type photoelectric conversion element by the 2nd Embodiment of this invention. 図８に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の受光面の全体にテクスチャ構造が形成され、且つ、シリコン基板の裏面の一部に凹凸が形成された状態を示す断面図である。It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 8, Comprising: A texture structure is formed in the whole light-receiving surface of a silicon substrate, and unevenness | corrugation is formed in a part of back surface of a silicon substrate. It is sectional drawing which shows the state in which was formed. 図８に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の裏面側にｎ型拡散領域とｐ型拡散領域とが形成された状態を示す断面図である。FIG. 9 is a cross-sectional view for explaining a manufacturing method of the back junction type photoelectric conversion element shown in FIG. 8 and showing a state in which an n-type diffusion region and a p-type diffusion region are formed on the back surface side of the silicon substrate. It is. 図８に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の裏面側に第１パッシベーション層及び第２パッシベーション層が形成された状態を示す断面図である。It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 8, Comprising: It is sectional drawing which shows the state in which the 1st passivation layer and the 2nd passivation layer were formed in the back surface side of the silicon substrate. is there. 図８に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の受光面側に反射防止膜が形成された状態を示す断面図である。It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 8, Comprising: It is sectional drawing which shows the state in which the antireflection film was formed in the light-receiving surface side of a silicon substrate. 図８に示す裏面接合型の光電変換素子の製造方法を説明するための断面図であって、シリコン基板の裏面側に電極が形成された状態を示す断面図である。It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 8, Comprising: It is sectional drawing which shows the state in which the electrode was formed in the back surface side of the silicon substrate. 本発明の実施の形態による裏面接合型の光電変換素子を備える光電変換モジュールの構成の一例を示す概略図である。It is the schematic which shows an example of a structure of a photoelectric conversion module provided with the back junction type photoelectric conversion element by embodiment of this invention. 本発明の実施の形態による裏面接合型の光電変換素子を備える太陽光発電システムの構成の一例を示す概略図である。It is the schematic which shows an example of a structure of a solar energy power generation system provided with the back junction type photoelectric conversion element by embodiment of this invention. 図１１に示す光電変換モジュールアレイの構成の一例を示す概略図である。It is the schematic which shows an example of a structure of the photoelectric conversion module array shown in FIG. 本発明の実施の形態による裏面接合型の光電変換素子を備える太陽光発電システムの構成の一例を示す概略図である。It is the schematic which shows an example of a structure of a solar energy power generation system provided with the back junction type photoelectric conversion element by embodiment of this invention.
　本発明の実施の形態による裏面接合型の光電変換素子は、シリコン基板と、第１半導体層と、第２半導体層と、第１電極と、第２電極とを備える。第１半導体層は、第１導電型を有し、シリコン基板の裏面側に形成される。第２半導体層は、第１導電型とは反対の第２導電型を有し、シリコン基板の裏面側に形成される。第１電極は、第１半導体層に接して形成される。第２電極は、第２半導体層に接して形成される。シリコン基板の裏面であって、且つ、第１半導体層が形成された領域には、凹凸が形成される。シリコン基板の裏面であって、且つ、第２半導体層が形成された領域では、平均面粗さＲａが０．７５ｎｍ以下である。 A back junction photoelectric conversion element according to an embodiment of the present invention includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer has a first conductivity type and is formed on the back side of the silicon substrate. The second semiconductor layer has a second conductivity type opposite to the first conductivity type, and is formed on the back side of the silicon substrate. The first electrode is formed in contact with the first semiconductor layer. The second electrode is formed in contact with the second semiconductor layer. Irregularities are formed on the back surface of the silicon substrate and in the region where the first semiconductor layer is formed. On the back surface of the silicon substrate and in the region where the second semiconductor layer is formed, the average surface roughness Ra is 0.75 nm or less.
　裏面接合型の光電変換素子では、シリコン基板の裏面に凹凸を形成することにより、短絡電流を増加させることができる。なぜなら、長波長側の光が反射されて、シリコン基板内に戻ることにより、光吸収が増えるからである。 In the back junction type photoelectric conversion element, the short circuit current can be increased by forming irregularities on the back surface of the silicon substrate. This is because light absorption increases when light on the long wavelength side is reflected and returned into the silicon substrate.
　しかしながら、裏面に凹凸を形成すると、開放電圧が低下する。なぜなら、表面積が大きくなることにより、表面再結合が増えるからである。また、凹凸が不均一な箇所（例えば、凹凸がピラミッド状のテクスチャ構造である場合には、谷や稜線の部分）での表面再結合が増えるからである。 However, if irregularities are formed on the back surface, the open-circuit voltage decreases. This is because surface recombination increases as the surface area increases. Moreover, it is because the surface recombination in the location where unevenness | corrugation is non-uniform | heterogenous (For example, when unevenness | corrugation is a pyramid-like texture structure, the part of a trough or a ridgeline) increases.
　上記裏面接合型の光電変換素子においては、シリコン基板の裏面のうち、第１電極が接する第１半導体層が形成された領域に凹凸が形成される。そのため、短絡電流を増加させることができる。 In the back junction type photoelectric conversion element, irregularities are formed in a region of the back surface of the silicon substrate where the first semiconductor layer in contact with the first electrode is formed. Therefore, the short circuit current can be increased.
　上記裏面接合型の光電変換素子では、シリコン基板の裏面のうち、第２電極が接する第２半導体層が形成された領域において、平均面粗さＲａが０．７５ｎｍ以下である。この場合、シリコン基板と第２半導体層との界面における酸素濃度が、１.２×１０２０ｃｍ-3以下となる。そのため、当該領域における表面再結合を少なくすることができる。その結果、開放電圧の低下を抑えることができる。 In the back junction type photoelectric conversion element, the average surface roughness Ra is 0.75 nm or less in the region where the second semiconductor layer in contact with the second electrode is formed on the back surface of the silicon substrate. In this case, the oxygen concentration at the interface between the silicon substrate and the second semiconductor layer is 1.2 × 10 20 cm −3 or less. Therefore, surface recombination in the region can be reduced. As a result, it is possible to suppress a decrease in the open circuit voltage.
　上記裏面接合型の光電変換素子においては、短絡電流を増加させつつ、開放電圧の低下を抑えることができる。その結果、変換効率を向上させることができる。 In the back junction type photoelectric conversion element, it is possible to suppress a decrease in open circuit voltage while increasing a short-circuit current. As a result, conversion efficiency can be improved.
　好ましくは、シリコン基板の裏面のうち、第２電極が接する第２半導体層が形成された領域の平均面粗さＲａが０．４０ｎｍ以下である。この場合、シリコン基板と第２半導体層との界面における酸素濃度が、８×１０１９ｃｍ-3以下となる。その結果、当該領域における表面再結合をさらに少なくすることができる。 Preferably, the average surface roughness Ra of the region where the second semiconductor layer in contact with the second electrode is formed on the back surface of the silicon substrate is 0.40 nm or less. In this case, the oxygen concentration at the interface between the silicon substrate and the second semiconductor layer is 8 × 10 19 cm −3 or less. As a result, surface recombination in the region can be further reduced.
　上記裏面接合型の光電変換素子においては、第１半導体層が第１拡散領域であって、且つ、第２半導体層が第２拡散領域であってもよい。ここで、第１拡散領域は、シリコン基板中に形成され、第１導電型の不純物が拡散された領域である。第２拡散領域は、シリコン基板中に形成され、第２導電型の不純物が拡散された領域である。このような裏面接合型の光電変換素子であっても、変換効率を向上させることができる。 In the back junction type photoelectric conversion element, the first semiconductor layer may be the first diffusion region, and the second semiconductor layer may be the second diffusion region. Here, the first diffusion region is a region formed in the silicon substrate and in which the first conductivity type impurity is diffused. The second diffusion region is a region formed in the silicon substrate and diffused with the second conductivity type impurity. Even with such a back junction type photoelectric conversion element, the conversion efficiency can be improved.
　上記裏面接合型の光電変換素子は、真性非晶質半導体層をさらに備えてもよい。真性非晶質半導体層は、シリコン基板の裏面に接して形成され、真性の非晶質半導体からなる。この場合、第１半導体層は第１非晶質半導体層であり、第２半導体層は第２非晶質半導体層である。ここで、第１非晶質半導体層は、真性非晶質半導体層に接して形成され、第１導電型の不純物を含む非晶質半導体からなる。第２非晶質半導体層は、真性非晶質半導体層に接して形成され、第２導電型の不純物を含む非晶質半導体からなる。このような裏面接合型の光電変換素子であっても、変換効率を向上させることができる。 The back junction photoelectric conversion element may further include an intrinsic amorphous semiconductor layer. The intrinsic amorphous semiconductor layer is formed in contact with the back surface of the silicon substrate and is made of an intrinsic amorphous semiconductor. In this case, the first semiconductor layer is a first amorphous semiconductor layer, and the second semiconductor layer is a second amorphous semiconductor layer. Here, the first amorphous semiconductor layer is formed in contact with the intrinsic amorphous semiconductor layer and is made of an amorphous semiconductor containing an impurity of the first conductivity type. The second amorphous semiconductor layer is formed in contact with the intrinsic amorphous semiconductor layer and is made of an amorphous semiconductor containing a second conductivity type impurity. Even with such a back junction type photoelectric conversion element, the conversion efficiency can be improved.
　以下、本発明のより具体的な実施形態について、図面を参照しながら説明する。図中同一または相当部分には同一符号を付してその説明は繰り返さない。 Hereinafter, more specific embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.
　［第１の実施の形態］
　図１を参照しながら、本発明の第１の実施の形態による裏面接合型の光電変換素子１０について説明する。光電変換素子１０は、シリコン基板１２と、真性非晶質半導体層としての真性非晶質半導体層１４，１６と、第１半導体層としてのｎ型非晶質半導体層１８と、第２半導体層としてのｐ型非晶質半導体層２０と、第１電極としての電極２２と、第２電極としての電極２４と、真性非晶質半導体層２６と、ｎ型非晶質半導体層２８と、反射防止膜３０とを備える。 [First Embodiment]
A back junction photoelectric conversion element 10 according to a first embodiment of the present invention will be described with reference to FIG. The photoelectric conversion element 10 includes a silicon substrate 12, intrinsic amorphous semiconductor layers 14 and 16 as intrinsic amorphous semiconductor layers, an n-type amorphous semiconductor layer 18 as a first semiconductor layer, and a second semiconductor layer. A p-type amorphous semiconductor layer 20, an electrode 22 as a first electrode, an electrode 24 as a second electrode, an intrinsic amorphous semiconductor layer 26, an n-type amorphous semiconductor layer 28, a reflection A prevention film 30.
　シリコン基板１２は、ｎ型の単結晶シリコン基板である。シリコン基板１２の厚さは、例えば、１００～３００μｍである。シリコン基板１２の比抵抗は、例えば、１．０～１０．０Ω・ｃｍである。 The silicon substrate 12 is an n-type single crystal silicon substrate. The thickness of the silicon substrate 12 is, for example, 100 to 300 μm. The specific resistance of the silicon substrate 12 is, for example, 1.0 to 10.0 Ω · cm.
　シリコン基板１２の受光面には、テクスチャ構造３２が形成されている。これにより、シリコン基板１２に入射した光を閉じ込めて、光の利用効率を高めることができる。 A texture structure 32 is formed on the light receiving surface of the silicon substrate 12. Thereby, the light incident on the silicon substrate 12 can be confined and the light use efficiency can be improved.
　シリコン基板１２の面方位は（１００）が望ましい。これにより、テクスチャ構造３２の形成が容易になる。 The plane orientation of the silicon substrate 12 is preferably (100). Thereby, formation of the texture structure 32 becomes easy.
　シリコン基板１２の受光面は、真性非晶質半導体層２６で覆われている。真性非晶質半導体層２６は、例えば、ｉ型アモルファスシリコン（ａ‐Ｓｉ）からなる。真性非晶質半導体層２６の厚みは、例えば、２～２５ｎｍである。 The light receiving surface of the silicon substrate 12 is covered with an intrinsic amorphous semiconductor layer 26. The intrinsic amorphous semiconductor layer 26 is made of, for example, i-type amorphous silicon (a-Si). The thickness of the intrinsic amorphous semiconductor layer 26 is, for example, 2 to 25 nm.
　真性非晶質半導体層２６は、ｎ型非晶質半導体層２８で覆われている。ｎ型非晶質半導体層２８は、例えば、ｎ型不純物（例えば、リン）を含む非晶質シリコンからなる。ｎ型非晶質半導体層２８の厚みは、例えば、２～５０ｎｍである。 The intrinsic amorphous semiconductor layer 26 is covered with an n-type amorphous semiconductor layer 28. The n-type amorphous semiconductor layer 28 is made of, for example, amorphous silicon containing an n-type impurity (for example, phosphorus). The thickness of the n-type amorphous semiconductor layer 28 is, for example, 2 to 50 nm.
　ｎ型非晶質半導体層２８は、反射防止膜３０で覆われている。反射防止膜３０は、例えば、酸化シリコン、窒化シリコン、酸窒化シリコンからなる。反射防止膜３０は、ｎ型非晶質半導体層２８の表面のパッシベーションを考慮すると、好ましくは、窒化シリコン又は酸窒化シリコンからなる。反射防止膜３０の厚みは、例えば、８０～３００ｎｍである。 The n-type amorphous semiconductor layer 28 is covered with an antireflection film 30. The antireflection film 30 is made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. In consideration of passivation of the surface of the n-type amorphous semiconductor layer 28, the antireflection film 30 is preferably made of silicon nitride or silicon oxynitride. The thickness of the antireflection film 30 is, for example, 80 to 300 nm.
　シリコン基板１２の裏面は、真性非晶質半導体層１４、１６で覆われている。 The back surface of the silicon substrate 12 is covered with intrinsic amorphous semiconductor layers 14 and 16.
　真性非晶質半導体層１４，１６は、例えば、ｉ型アモルファスシリコン（ａ‐Ｓｉ）からなる。真性非晶質半導体層１４はシリコン基板１２の裏面の一部に形成されている。真性非晶質半導体層１６は、シリコン基板１２の裏面において真性非晶質半導体層１４が形成された領域に隣接して形成されている。つまり、真性非晶質半導体層１４、１６は、シリコン基板１２の裏面の全体に形成されている。真性非晶質半導体層１４、１６の厚みは、例えば、２～１０ｎｍである。 The intrinsic amorphous semiconductor layers 14 and 16 are made of, for example, i-type amorphous silicon (a-Si). The intrinsic amorphous semiconductor layer 14 is formed on a part of the back surface of the silicon substrate 12. The intrinsic amorphous semiconductor layer 16 is formed adjacent to the region where the intrinsic amorphous semiconductor layer 14 is formed on the back surface of the silicon substrate 12. That is, the intrinsic amorphous semiconductor layers 14 and 16 are formed on the entire back surface of the silicon substrate 12. The intrinsic amorphous semiconductor layers 14 and 16 have a thickness of 2 to 10 nm, for example.
　ｎ型非晶質半導体層１８は、ｎ型不純物（例えば、リン）を含む非晶質シリコンからなる。ｎ型非晶質半導体層１８の厚さは、例えば、２～５０ｎｍである。 The n-type amorphous semiconductor layer 18 is made of amorphous silicon containing an n-type impurity (for example, phosphorus). The thickness of the n-type amorphous semiconductor layer 18 is, for example, 2 to 50 nm.
　ｐ型非晶質半導体層２０は、ｐ型不純物（例えば、ボロン）を含む非晶質シリコンからなる。ｐ型非晶質半導体層２０の厚さは、例えば、２～５０ｎｍである。 The p-type amorphous semiconductor layer 20 is made of amorphous silicon containing a p-type impurity (for example, boron). The thickness of the p-type amorphous semiconductor layer 20 is, for example, 2 to 50 nm.
　電極２２は、ｎ型非晶質半導体層１８に接して形成されている。これにより、電極２２がｎ型非晶質半導体層１８に対して電気的に接続されている。 The electrode 22 is formed in contact with the n-type amorphous semiconductor layer 18. Thereby, the electrode 22 is electrically connected to the n-type amorphous semiconductor layer 18.
　電極２２は、透明導電層２２Ａと、金属層２２Ｂとを含む。透明導電層２２Ａは、ｎ型非晶質半導体層１８に接して形成される。透明導電層２２Ａは、例えば、酸化インジウム錫（ＩＴＯ）からなる。金属層２２Ｂは、透明導電層２２Ａに接して形成される。金属層２２Ｂは、例えば、銀からなる。 The electrode 22 includes a transparent conductive layer 22A and a metal layer 22B. The transparent conductive layer 22A is formed in contact with the n-type amorphous semiconductor layer 18. The transparent conductive layer 22A is made of indium tin oxide (ITO), for example. The metal layer 22B is formed in contact with the transparent conductive layer 22A. The metal layer 22B is made of, for example, silver.
　電極２４は、ｐ型非晶質半導体層２０に接して形成されている。これにより、電極２４がｐ型非晶質半導体層２０に対して電気的に接続されている。 The electrode 24 is formed in contact with the p-type amorphous semiconductor layer 20. Thereby, the electrode 24 is electrically connected to the p-type amorphous semiconductor layer 20.
　電極２４は、透明導電層２４Ａと、金属層２４Ｂとを含む。透明導電層２４Ａは、ｐ型非晶質半導体層２０に接して形成される。透明導電層２４Ａは、例えば、酸化インジウム錫（ＩＴＯ）からなる。金属層２４Ｂは、透明導電層２４Ａに接して形成される。金属層２４Ｂは、例えば、銀からなる。 The electrode 24 includes a transparent conductive layer 24A and a metal layer 24B. The transparent conductive layer 24 </ b> A is formed in contact with the p-type amorphous semiconductor layer 20. The transparent conductive layer 24A is made of indium tin oxide (ITO), for example. The metal layer 24B is formed in contact with the transparent conductive layer 24A. The metal layer 24B is made of silver, for example.
　ここで、シリコン基板１２の厚さ方向から見て、シリコン基板１２の裏面のうち、ｎ型非晶質半導体層１８と重なる領域には、凹凸３４が形成されている。そのため、真性非晶質半導体層１４の表面には、シリコン基板１２の裏面に形成された凹凸３４に対応する凹凸３４Ａが形成されている。また、ｎ型非晶質半導体層１８の表面には、シリコン基板１２の裏面に形成された凹凸３４に対応する凹凸３４Ｂが形成されている。 Here, as viewed from the thickness direction of the silicon substrate 12, irregularities 34 are formed in a region overlapping the n-type amorphous semiconductor layer 18 on the back surface of the silicon substrate 12. Therefore, on the surface of the intrinsic amorphous semiconductor layer 14, irregularities 34 </ b> A corresponding to the irregularities 34 formed on the back surface of the silicon substrate 12 are formed. Further, on the surface of the n-type amorphous semiconductor layer 18, irregularities 34 </ b> B corresponding to the irregularities 34 formed on the back surface of the silicon substrate 12 are formed.
　凹凸３４は、例えば、テクスチャ構造である。凹凸３４は、規則性を有していてもよいし、ランダムであってもよい。凹凸３４の高低差は、テクスチャ構造３２の高低差と同じであってもよいし、異なっていてもよい。 The unevenness 34 has, for example, a texture structure. The unevenness 34 may have regularity or may be random. The height difference of the unevenness 34 may be the same as or different from the height difference of the texture structure 32.
　シリコン基板１２の裏面全体に対して凹凸３４の形成領域が占める割合は、好ましくは、２０～８０％である。この場合、短絡電流を増加させることができる。 The ratio of the formation region of the unevenness 34 to the entire back surface of the silicon substrate 12 is preferably 20 to 80%. In this case, the short circuit current can be increased.
　凹凸３４の高低差は、好ましくは、１～１０μｍである。この場合、短絡電流を増加させることができる。 The height difference of the irregularities 34 is preferably 1 to 10 μm. In this case, the short circuit current can be increased.
　シリコン基板１２の裏面のうち、凹凸３４が形成されていない領域の平均面粗さＲａは、０．７５ｎｍ以下であり、好ましくは、０．４０ｎｍ以下である。ここで、平均面粗さＲａは、原子間力顕微鏡（ＡＦＭ）で測定した面の凹凸量（高低差）を定量化する指標であって、以下の式で定義される。 The average surface roughness Ra of the region where the irregularities 34 are not formed on the back surface of the silicon substrate 12 is 0.75 nm or less, and preferably 0.40 nm or less. Here, the average surface roughness Ra is an index for quantifying the surface unevenness (height difference) measured by an atomic force microscope (AFM), and is defined by the following equation.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　ここで、Ｚ（ｉ）は、ある測定点における高低差（面の高さ）であり、Ｚｅは、高低差（面の高さ）の平均値である。 Here, Z (i) is a height difference (surface height) at a certain measurement point, and Ze is an average value of the height difference (surface height).
　なお、本発明の実施の形態では、Ｒａを上記のように定義しているが、「凹凸３４が形成されていない領域の平均面粗さＲａが０．７５ｎｍ以下」と記載しても、凹凸３４が形成されていない領域の全てにおいて完全にＲａが０．７５ｎｍ以下になっているわけではない。例えば、異常箇所が一部形成されている場合がある。しかしながら、当該異常箇所は、面積的に非常に小さい。そのため、本発明の実施の形態に記載された効果が影響を受けるわけではない。凹凸３４が形成されていない領域の平均面粗さＲａが０．７５ｎｍ以下と記載している場合であっても、凹凸３４が形成されていない領域の全面積の９０％以上において平均面粗さが記載の範囲に入っていれば問題ないものとする。 In the embodiment of the present invention, Ra is defined as described above. However, even if “the average surface roughness Ra of the region where the unevenness 34 is not formed is 0.75 nm or less” is described, the unevenness In all the regions where 34 is not formed, Ra is not completely 0.75 nm or less. For example, there may be a case where a part of the abnormality is formed. However, the abnormal part is very small in area. Therefore, the effects described in the embodiments of the present invention are not affected. Even if the average surface roughness Ra of the region where the unevenness 34 is not formed is described as 0.75 nm or less, the average surface roughness is 90% or more of the total area of the region where the unevenness 34 is not formed. If is within the stated range, there will be no problem.
　［光電変換素子の製造方法］
　図２Ａ～図２Ｅを参照しながら、光電変換素子１０の製造方法について説明する。 [Production Method of Photoelectric Conversion Element]
A method for manufacturing the photoelectric conversion element 10 will be described with reference to FIGS. 2A to 2E.
　先ず、図２Ａに示すように、受光面の全体にテクスチャ構造３２を有するとともに、裏面の一部に凹凸３４を有するシリコン基板１２を準備する。具体的には、以下のとおりである。 First, as shown in FIG. 2A, a silicon substrate 12 having a texture structure 32 on the entire light-receiving surface and having irregularities 34 on a part of the back surface is prepared. Specifically, it is as follows.
　最初に、シリコンのインゴットをスライスして、シリコン基板を切り出す。続いて、切り出したシリコン基板をアルカリ溶液で薄肉化する。その後、フッ硝酸溶液でシリコン基板をエッチングして、所定の厚みを有するシリコン基板を得る。このときのフッ硝酸溶液の混合比及び処理時間により、あとで得られるシリコン基板の裏面のうち凹凸３４が形成されていない領域の平均面粗さＲａが変化する。 First, slice the silicon ingot and cut out the silicon substrate. Subsequently, the cut silicon substrate is thinned with an alkaline solution. Thereafter, the silicon substrate is etched with a hydrofluoric acid solution to obtain a silicon substrate having a predetermined thickness. The average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate to be obtained later varies depending on the mixing ratio of the hydrofluoric acid solution and the processing time.
　フッ硝酸の混合比は、例えば、フッ酸（ＨＦ）が８．３重量％であり、硝酸（ＨＮＯ３）が５０．０％であり、水（Ｈ２Ｏ）が４１.７重量％である。エッチングの時間は、例
えば、１分である。 As for the mixing ratio of hydrofluoric acid, for example, hydrofluoric acid (HF) is 8.3% by weight, nitric acid (HNO 3 ) is 50.0%, and water (H 2 O) is 41.7% by weight. . The etching time is, for example, 1 minute.
　続いて、スパッタ等により、シリコン基板の裏面にシリコン酸化膜を形成する。シリコン酸化膜の膜厚は、例えば、１００～１０００ｎｍである。その後、フォトリソグラフィ法により、シリコン酸化膜をパターニングする。これにより、シリコン基板の裏面の一部にのみ、シリコン酸化膜が残る。この状態で、シリコン基板をウェットエッチングする。これにより、受光面の全体にテクスチャ構造３２が形成され、且つ、裏面の一部に凹凸３４が形成される。 Subsequently, a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like. The film thickness of the silicon oxide film is, for example, 100 to 1000 nm. Thereafter, the silicon oxide film is patterned by photolithography. As a result, the silicon oxide film remains only on a part of the back surface of the silicon substrate. In this state, the silicon substrate is wet etched. Thereby, the texture structure 32 is formed on the entire light receiving surface, and the unevenness 34 is formed on a part of the back surface.
　上記ウェットエッチングに用いられる溶液は、例えば、水酸化カリウム（ＫＯＨ）と、イソプロピルアルコール（ＩＰＡ）とを水に溶かしたものである。上記溶液における水酸化カリウムの割合は、例えば、１～５重量％である。上記溶液におけるイソプロピルアルコールの割合は、例えば、１～１０重量％である。上記溶液の温度は、例えば、８０～９０℃である。エッチングの時間は、例えば、１０～６０分である。 The solution used for the wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water. The proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight. The proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight. The temperature of the solution is, for example, 80 to 90 ° C. The etching time is, for example, 10 to 60 minutes.
　なお、上記の方法では、受光面のテクスチャ３２と裏面の凹凸を同時に形成しているが、例えば、以下のようにして、別々に形成することもできる。 In the above method, the texture 32 on the light receiving surface and the unevenness on the back surface are formed at the same time. However, for example, they can be formed separately as follows.
　先ず、スパッタ等により、シリコン基板の裏面にシリコン酸化膜を形成する。シリコン酸化膜の膜厚は、例えば、１００～１０００ｎｍである。この状態でシリコン基板をウェットエッチングする。これにより、受光面の全体にテクスチャ構造３２が形成される。このとき、ウェットエッチングに用いられる溶液は、例えば、水酸化カリウム（ＫＯＨ）と、イソプロピルアルコール（ＩＰＡ）とを水に溶かしたものである。上記溶液における水酸化カリウムの割合は、例えば、１～５重量％である。上記溶液におけるイソプロピルアルコールの割合は、例えば、１～１０重量％である。上記溶液の温度は、例えば、８０～９０℃である。エッチングの時間は、例えば、１０～６０分である。 First, a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like. The film thickness of the silicon oxide film is, for example, 100 to 1000 nm. In this state, the silicon substrate is wet etched. Thereby, the texture structure 32 is formed in the whole light-receiving surface. At this time, the solution used for wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water. The proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight. The proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight. The temperature of the solution is, for example, 80 to 90 ° C. The etching time is, for example, 10 to 60 minutes.
　次に、スパッタ等により、テクスチャ構造３２の形成されたシリコン基板の受光面にシリコン酸化膜を形成する。シリコン酸化膜の膜厚は、例えば、１００～１０００ｎｍである。その後、フォトリソグラフィ法により、裏面のシリコン酸化膜をパターニングする。これにより、シリコン基板の受光面と裏面の一部にのみ、シリコン酸化膜が残った状態になる。この状態で、シリコン基板をウェットエッチングする。これにより、裏面の一部に凹凸３４が形成される。このとき、ウェットエッチングに用いられる溶液は、例えば、水酸化カリウム（ＫＯＨ）と、イソプロピルアルコール（ＩＰＡ）とを水に溶かしたものである。上記溶液における水酸化カリウムの割合は、例えば、１～５重量％である。上記溶液におけるイソプロピルアルコールの割合は、例えば、１～１０重量％である。上記溶液の温度は、例えば、８０～９０℃である。エッチングの時間は、例えば、１０～６０分である。このときの溶液の組成、濃度、温度、時間の条件は、上記の受光面のウェットエッチングのときと同じであってもよいが、異なっていてもよい。異なっている場合には、受光面のテクスチャとは異なる凹凸を形成することができる。 Next, a silicon oxide film is formed on the light receiving surface of the silicon substrate on which the texture structure 32 is formed by sputtering or the like. The film thickness of the silicon oxide film is, for example, 100 to 1000 nm. Thereafter, the silicon oxide film on the back surface is patterned by photolithography. As a result, the silicon oxide film remains only on a part of the light receiving surface and the back surface of the silicon substrate. In this state, the silicon substrate is wet etched. Thereby, the unevenness | corrugation 34 is formed in a part of back surface. At this time, the solution used for wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water. The proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight. The proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight. The temperature of the solution is, for example, 80 to 90 ° C. The etching time is, for example, 10 to 60 minutes. The conditions of the composition, concentration, temperature, and time of the solution at this time may be the same as those in the above-described wet etching of the light receiving surface, but may be different. If they are different, irregularities different from the texture of the light receiving surface can be formed.
　受光面の全体にテクスチャ構造３２が形成され、且つ、裏面の一部に凹凸３４が形成された状態で、シリコン基板１２の裏面の一部、あるいは受光面と裏面の一部に、残っているシリコン酸化膜を５.２重量％のフッ化水素酸を用いたウェットエッチングにより除去する。これにより、目的とするシリコン基板１２が得られる。このとき、シリコン基板の裏面のうち凹凸３４が形成されていない領域の平均面粗さＲａは、０．２６ｎｍになる。 With the texture structure 32 formed on the entire light receiving surface and the unevenness 34 formed on a part of the back surface, it remains on a part of the back surface of the silicon substrate 12 or a part of the light receiving surface and the back surface. The silicon oxide film is removed by wet etching using 5.2 wt% hydrofluoric acid. Thereby, the target silicon substrate 12 is obtained. At this time, the average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate is 0.26 nm.
　続いて、図２Ｂに示すように、シリコン基板１２の受光面に真性非晶質半導体層２６及びｎ型非晶質半導体層２８を形成し、且つ、シリコン基板１２の裏面の一部に真性非晶質半導体層１６及びｐ型非晶質半導体層２０を形成する。具体的には、以下のとおりである。 Subsequently, as shown in FIG. 2B, an intrinsic amorphous semiconductor layer 26 and an n-type amorphous semiconductor layer 28 are formed on the light receiving surface of the silicon substrate 12, and intrinsic non-existence is formed on a part of the back surface of the silicon substrate 12. A crystalline semiconductor layer 16 and a p-type amorphous semiconductor layer 20 are formed. Specifically, it is as follows.
　先ず、シリコン基板１２の受光面に真性非晶質半導体層２６及びｎ型非晶質半導体層２８を形成する。真性非晶質半導体層２６及びｎ型非晶質半導体層２８は、例えば、プラズマＣＶＤ法により形成することができる。 First, the intrinsic amorphous semiconductor layer 26 and the n-type amorphous semiconductor layer 28 are formed on the light receiving surface of the silicon substrate 12. The intrinsic amorphous semiconductor layer 26 and the n-type amorphous semiconductor layer 28 can be formed by, for example, a plasma CVD method.
　続いて、シリコン基板１２の裏面に、真性非晶質半導体層及びｐ型非晶質半導体層を形成する。真性非晶質半導体層及びｐ型非晶質半導体層は、例えば、プラズマＣＶＤ法により形成することができる。続いて、フォトリソグラフィ法により、真性非晶質半導体層及びｐ型非晶質半導体層をパターニングする。これにより、シリコン基板１２の裏面のうち、凹凸３４が形成された領域が露出され、それ以外の領域が真性非晶質半導体層１６及びｐ型非晶質半導体層２０で覆われる。 Subsequently, an intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer are formed on the back surface of the silicon substrate 12. The intrinsic amorphous semiconductor layer and the p-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method. Subsequently, the intrinsic amorphous semiconductor layer and the p-type amorphous semiconductor layer are patterned by photolithography. As a result, the region where the irregularities 34 are formed is exposed on the back surface of the silicon substrate 12, and the other region is covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20.
　続いて、図２Ｃに示すように、シリコン基板１２の裏面のうち、真性非晶質半導体層１６及びｐ型非晶質半導体層２０で覆われていない領域に、真性非晶質半導体層１４及びｎ型非晶質半導体層１８を形成する。具体的には、以下のとおりである。 Subsequently, as illustrated in FIG. 2C, the intrinsic amorphous semiconductor layer 14 and the region not covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20 on the back surface of the silicon substrate 12 are formed. An n-type amorphous semiconductor layer 18 is formed. Specifically, it is as follows.
　先ず、シリコン基板１２の裏面と、ｐ型非晶質半導体層２０とを覆う真性非晶質半導体層及びｎ型非晶質半導体層を形成する。真性非晶質半導体層及びｎ型非晶質半導体層は、例えば、プラズマＣＶＤ法により形成することができる。続いて、フォトリソグラフィ法により、真性非晶質半導体層及びｎ型非晶質半導体層をパターニングする。これにより、シリコン基板１２の裏面のうち、真性非晶質半導体層１６及びｐ型非晶質半導体層２０で覆われていない領域に、真性非晶質半導体層１４及びｎ型非晶質半導体層１８が形成される。 First, an intrinsic amorphous semiconductor layer and an n-type amorphous semiconductor layer that cover the back surface of the silicon substrate 12 and the p-type amorphous semiconductor layer 20 are formed. The intrinsic amorphous semiconductor layer and the n-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method. Subsequently, the intrinsic amorphous semiconductor layer and the n-type amorphous semiconductor layer are patterned by photolithography. As a result, the intrinsic amorphous semiconductor layer 14 and the n-type amorphous semiconductor layer are formed on the back surface of the silicon substrate 12 in a region not covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20. 18 is formed.
　続いて、図２Ｄに示すように、ｎ型非晶質半導体層２８上に反射防止膜３０を形成する。反射防止膜３０は、例えば、プラズマＣＶＤ法により形成できる。 Subsequently, as shown in FIG. 2D, an antireflection film 30 is formed on the n-type amorphous semiconductor layer 28. The antireflection film 30 can be formed by, for example, a plasma CVD method.
　続いて、図２Ｅに示すように、電極２２、２４を形成する。具体的には、以下のとおりである。 Subsequently, electrodes 22 and 24 are formed as shown in FIG. 2E. Specifically, it is as follows.
　先ず、ｎ型非晶質半導体層１８及びｐ型非晶質半導体層２０を覆う透明導電層を形成する。透明導電層は、例えば、スパッタ等によって形成できる。 First, a transparent conductive layer covering the n-type amorphous semiconductor layer 18 and the p-type amorphous semiconductor layer 20 is formed. The transparent conductive layer can be formed by sputtering, for example.
　続いて、透明導電層を覆う金属層を形成する。金属層は、例えば、スパッタや蒸着等によって形成できる。 Subsequently, a metal layer covering the transparent conductive layer is formed. The metal layer can be formed by sputtering or vapor deposition, for example.
　続いて、フォトリソグラフィ法により、透明導電層及び金属層をパターニングする。これにより、電極２２、２４が形成され、目的とする光電変換素子１０が得られる。 Subsequently, the transparent conductive layer and the metal layer are patterned by photolithography. Thereby, the electrodes 22 and 24 are formed, and the target photoelectric conversion element 10 is obtained.
　このような光電変換素子１０においては、シリコン基板１２の裏面の一部に凹凸３４が形成されている。そのため、裏面全体に凹凸が形成されている場合と比べて、開放電圧の低下を抑えることができる。したがって、光電変換素子１０においては、開放電圧の低下を抑えつつ、変換効率の向上を図ることができる。 In such a photoelectric conversion element 10, irregularities 34 are formed on a part of the back surface of the silicon substrate 12. Therefore, a decrease in open circuit voltage can be suppressed as compared with the case where unevenness is formed on the entire back surface. Therefore, in the photoelectric conversion element 10, it is possible to improve the conversion efficiency while suppressing a decrease in the open circuit voltage.
　［第１の実施の形態の応用例］
　図３は、第１の実施の形態の応用例に係る光電変換素子１０Ａを示す。光電変換素子１０Ａにおいては、シリコン基板１２の裏面のうち、シリコン基板１２の厚さ方向から見て、ｐ型非晶質半導体層２０が重なる領域に凹凸３４が形成されている。また、光電変換素子１０Ａにおいては、シリコン基板１２の裏面のうち、凹凸３４が形成されていない領域の平均面粗さＲａが０．７５ｎｍ以下である。光電変換素子１０Ａにおいても、第１の実施の形態と同様に、開放電圧の低下を抑制しつつ、変換効率の向上を図ることができる。 [Application example of the first embodiment]
FIG. 3 shows a photoelectric conversion element 10A according to an application example of the first embodiment. In the photoelectric conversion element 10 </ b> A, unevenness 34 is formed in a region of the back surface of the silicon substrate 12 where the p-type amorphous semiconductor layer 20 overlaps when viewed from the thickness direction of the silicon substrate 12. Further, in the photoelectric conversion element 10A, the average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate 12 is 0.75 nm or less. Also in the photoelectric conversion element 10A, as in the first embodiment, it is possible to improve conversion efficiency while suppressing a decrease in open-circuit voltage.
　［実施例］
　第１の実施の形態による光電変換素子１０、及び、第１の実施の形態の応用例に係る光電変換素子１０Ａについて、ソーラーシミュレータを用いて、光電変換特性を評価した。第１の実施の形態による光電変換素子１０については、平均面粗さＲａが０．２６ｎｍである光電変換素子（実施例１）と、平均面粗さＲａが０．４０ｎｍである光電変換素子（実施例２）と、平均面粗さＲａが０．５３ｎｍである光電変換素子（実施例３）と、平均面粗さＲａが０．７５ｎｍである光電変換素子（実施例４）と、平均面粗さＲａが１．０２ｎｍである光電変換素子（比較例１）とを準備した。第１の実施の形態の応用例に係る光電変換素子１０Ａについては、平均面粗さＲａが０．２６ｎｍである光電変換素子（実施例５）を準備した。 [Example]
The photoelectric conversion characteristics of the photoelectric conversion element 10 according to the first embodiment and the photoelectric conversion element 10A according to the application example of the first embodiment were evaluated using a solar simulator. Regarding the photoelectric conversion element 10 according to the first embodiment, a photoelectric conversion element (Example 1) having an average surface roughness Ra of 0.26 nm and a photoelectric conversion element (average surface roughness Ra of 0.40 nm) ( Example 2), a photoelectric conversion element (Example 3) having an average surface roughness Ra of 0.53 nm, a photoelectric conversion element (Example 4) having an average surface roughness Ra of 0.75 nm, and an average surface A photoelectric conversion element (Comparative Example 1) having a roughness Ra of 1.02 nm was prepared. For the photoelectric conversion element 10A according to the application example of the first embodiment, a photoelectric conversion element (Example 5) having an average surface roughness Ra of 0.26 nm was prepared.
　ここで、平均面粗さＲａを０．２６ｎｍにするために、フッ硝酸溶液でシリコン基板をエッチングする条件は、以下のとおりであった。 Here, in order to set the average surface roughness Ra to 0.26 nm, the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
　フッ硝酸の混合比は、フッ酸（ＨＦ）が８．３重量％であり、硝酸（ＨＮＯ３）が５０．０％であり、水（Ｈ２Ｏ）が４１．７重量％であった。エッチングの時間は、１分であった。 The mixing ratio of hydrofluoric acid was 8.3% by weight for hydrofluoric acid (HF), 50.0% for nitric acid (HNO 3 ), and 41.7% by weight for water (H 2 O). The etching time was 1 minute.
　平均面粗さＲａを０．４０ｎｍにするために、フッ硝酸溶液でシリコン基板をエッチングする条件は、以下のとおりであった。 In order to set the average surface roughness Ra to 0.40 nm, the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
　フッ硝酸の混合比は、フッ酸（ＨＦ）が３.９重量％であり、硝酸（ＨＮＯ３）が５５
．３％であり、水（Ｈ２Ｏ）が４０．８重量％であった。エッチングの時間は、２分であった。 The mixing ratio of hydrofluoric acid is 3.9% by weight for hydrofluoric acid (HF) and 55% for nitric acid (HNO 3 ).
. 3% and water (H 2 O) was 40.8% by weight. The etching time was 2 minutes.
　平均面粗さＲａを０．５３ｎｍにするために、フッ硝酸溶液でシリコン基板をエッチングする条件は、以下のとおりであった。 In order to set the average surface roughness Ra to 0.53 nm, the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
　フッ硝酸の混合比は、フッ酸（ＨＦ）が２．０重量％であり、硝酸（ＨＮＯ３）が５７.６％であり、水（Ｈ２Ｏ）が４０．４重量％であった。エッチングの時間は、３分であ
った。 The mixing ratio of hydrofluoric acid was 2.0% by weight for hydrofluoric acid (HF), 57.6% for nitric acid (HNO 3 ), and 40.4% by weight for water (H 2 O). The etching time was 3 minutes.
　平均面粗さＲａを０．７５ｎｍにするために、フッ硝酸溶液でシリコン基板をエッチングする条件は、以下のとおりであった。 In order to set the average surface roughness Ra to 0.75 nm, the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
　フッ硝酸の混合比は、フッ酸（ＨＦ）が０．４重量％であり、硝酸（ＨＮＯ３）が５９．５％であり、水（Ｈ２Ｏ）が４０．１重量％であった。エッチングの時間は、５分であった。 The mixing ratio of hydrofluoric acid was 0.4% by weight for hydrofluoric acid (HF), 59.5% for nitric acid (HNO 3 ), and 40.1% by weight for water (H 2 O). The etching time was 5 minutes.
　平均面粗さＲａを１．０２ｎｍにするために、フッ硝酸溶液でシリコン基板をエッチングする条件は、以下のとおりであった。 In order to set the average surface roughness Ra to 1.02 nm, the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
　フッ硝酸の混合比は、フッ酸（ＨＦ）が０．３重量％であり、硝酸（ＨＮＯ３）が４３．８％であり、水（Ｈ２Ｏ）が５５．９重量％であった。エッチングの時間は、３０分であった。 The mixing ratio of hydrofluoric acid was 0.3% by weight for hydrofluoric acid (HF), 43.8% for nitric acid (HNO 3 ), and 55.9% by weight for water (H 2 O). The etching time was 30 minutes.
　上記の実施例１～４および比較例１の光電変換素子について、真性非晶質半導体層とシリコン基板との界面近傍の酸素原子の濃度プロファイルを、ＳＩＭＳ（Secondary Ion Mass Spectrometer）を用いて測定した。 For the photoelectric conversion elements of Examples 1 to 4 and Comparative Example 1 above, the concentration profile of oxygen atoms in the vicinity of the interface between the intrinsic amorphous semiconductor layer and the silicon substrate was measured using SIMS (Secondary Ion Mass Spectrometer). .
　図４には、ＳＩＭＳにより測定した実施例２と実施例４の酸素原子の濃度プロファイルが示されている。いずれも真性非晶質半導体層とシリコン基板との界面で酸素原子の濃度はピークをもっていた。なお、図示はしていないが、他の実施例及び比較例においても、同様に界面において酸素濃度はピークを持っていた。 FIG. 4 shows oxygen atom concentration profiles of Example 2 and Example 4 measured by SIMS. In any case, the concentration of oxygen atoms had a peak at the interface between the intrinsic amorphous semiconductor layer and the silicon substrate. Although not shown, the oxygen concentration also had a peak at the interface in the other examples and comparative examples.
　実施例１～４及び比較例１について、そのピークでの酸素濃度の値と基板の平均面粗さＲａとの関係を図５に示す。図５に示すように、Ｒａが小さくなると酸素濃度が低くなっていた。Ｒａが０．７５ｎｍ以下の場合、酸素濃度は１.２×１０２０ｃｍ-3以下になり、とくにＲａが０．４０ｎｍ以下では酸素濃度は８×１０１９ｃｍ-3以下まで低くなっていた。 For Examples 1 to 4 and Comparative Example 1, the relationship between the value of the oxygen concentration at the peak and the average surface roughness Ra of the substrate is shown in FIG. As shown in FIG. 5, the oxygen concentration was low when Ra was small. When Ra was 0.75 nm or less, the oxygen concentration was 1.2 × 10 20 cm −3 or less, and particularly when Ra was 0.40 nm or less, the oxygen concentration was lowered to 8 × 10 19 cm −3 or less.
　また、図６及び図７に示す光電変換素子についても、光電変換特性を評価した。図６に示す光電変換素子６０（比較例２）は、光電変換素子１０と比べて、シリコン基板１２の裏面に凹凸３４が形成されていない。光電変換素子６０において、裏面の平均面粗さＲａは０．２６ｎｍであった。図７に示す光電変換素子７０（比較例３）は、光電変換素子１０と比べて、裏面の全体に凹凸３４が形成されていた。実施例１～５及び比較例１～３の何れにおいても、セル面積は、２ｃｍ×２ｃｍであった。照射光は、ＡＭ１．５相当の光であった。 Also, the photoelectric conversion characteristics of the photoelectric conversion elements shown in FIGS. 6 and 7 were evaluated. In the photoelectric conversion element 60 (Comparative Example 2) illustrated in FIG. 6, the unevenness 34 is not formed on the back surface of the silicon substrate 12 as compared with the photoelectric conversion element 10. In the photoelectric conversion element 60, the average surface roughness Ra of the back surface was 0.26 nm. In the photoelectric conversion element 70 (Comparative Example 3) shown in FIG. 7, as compared with the photoelectric conversion element 10, the unevenness 34 was formed on the entire back surface. In any of Examples 1 to 5 and Comparative Examples 1 to 3, the cell area was 2 cm × 2 cm. Irradiation light was light equivalent to AM1.5.
　評価の結果を表１に示す。なお、表１では、比較例２の場合を基準として規格化している。 Table 1 shows the evaluation results. In Table 1, the case of Comparative Example 2 is standardized.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　表１から明らかなように、実施例１～５は、比較例１と比べて、開放電圧の低下が抑えられたので、変換効率が向上した。実施例４は、比較例１と比べて、変換効率が向上した。実施例３は、実施例４よりも平均面粗さＲａが小さいので、変換効率がさらに向上した。実施例２は、実施例３よりも平均面粗さＲａが小さいので、変換効率がさらに向上した。実施例１は、実施例２よりも平均面粗さＲａが小さいので、変換効率がさらに向上した。 As can be seen from Table 1, in Examples 1 to 5, compared to Comparative Example 1, since the decrease in open-circuit voltage was suppressed, the conversion efficiency was improved. In Example 4, the conversion efficiency was improved as compared with Comparative Example 1. In Example 3, since the average surface roughness Ra was smaller than that in Example 4, the conversion efficiency was further improved. In Example 2, since the average surface roughness Ra was smaller than that in Example 3, the conversion efficiency was further improved. In Example 1, since the average surface roughness Ra was smaller than that in Example 2, the conversion efficiency was further improved.
　［第２の実施の形態］
　図８を参照しながら、本発明の第２の実施の形態による裏面接合型の光電変換素子５０について説明する。光電変換素子５０は、シリコン基板５２と、反射防止膜５４と、パッシベーション膜５６と、パッシベーション膜５８と、電極６０と、電極６２とを備える。 [Second Embodiment]
A back junction photoelectric conversion element 50 according to a second embodiment of the present invention will be described with reference to FIG. The photoelectric conversion element 50 includes a silicon substrate 52, an antireflection film 54, a passivation film 56, a passivation film 58, an electrode 60, and an electrode 62.
　シリコン基板５２は、ｎ型の単結晶シリコン基板である。シリコン基板５２の厚さや比抵抗等は、シリコン基板１２と同じである。シリコン基板５２の受光面には、テクスチャ構造６８が形成されている。 The silicon substrate 52 is an n-type single crystal silicon substrate. The thickness and specific resistance of the silicon substrate 52 are the same as those of the silicon substrate 12. A texture structure 68 is formed on the light receiving surface of the silicon substrate 52.
　シリコン基板５２は、第１半導体層としてのｎ型拡散領域６４と、第２半導体層としてのｐ型拡散領域６６とを含む。 The silicon substrate 52 includes an n-type diffusion region 64 as a first semiconductor layer and a p-type diffusion region 66 as a second semiconductor layer.
　ｎ型拡散領域６４の不純物濃度は、例えば、１×１０１９ｃｍ－３～１×１０２０ｃｍ－３である。ｎ型拡散領域６４の深さ寸法（図８の上下方向の寸法）は、例えば、０．３～１．０μｍである。 The impurity concentration of the n-type diffusion region 64 is, for example, 1 × 10 19 cm −3 to 1 × 10 20 cm −3 . The depth dimension (vertical dimension in FIG. 8) of the n-type diffusion region 64 is, for example, 0.3 to 1.0 μm.
　ｐ型拡散領域６６の不純物濃度は、例えば、１×１０１９ｃｍ－３～１×１０２０ｃｍ－３である。ｐ型拡散領域６６の深さ寸法（図８の上下方向の寸法）は、例えば、０．３～１．０μｍである。 The impurity concentration of the p-type diffusion region 66 is, for example, 1 × 10 19 cm −3 to 1 × 10 20 cm −3 . The depth dimension (vertical dimension in FIG. 8) of the p-type diffusion region 66 is, for example, 0.3 to 1.0 μm.
　シリコン基板５２の受光面は、反射防止膜５４で覆われている。反射防止膜５４は、例えば、シリコン窒化膜である。シリコン窒化膜の厚さは、例えば、８０～３００ｎｍである。 The light receiving surface of the silicon substrate 52 is covered with an antireflection film 54. The antireflection film 54 is, for example, a silicon nitride film. The thickness of the silicon nitride film is, for example, 80 to 300 nm.
　パッシベーション膜５６は、ｐ型拡散領域６６に接して形成される。本実施形態では、シリコン基板５２の裏面のうち、ｐ型拡散領域５６の形成された領域がパッシベーション５６で覆われている。パッシベーション膜５６は、例えば、シリコン窒化膜やシリコン酸窒化膜である。パッシベーション膜５６の厚さは、例えば、５～１００ｎｍである。 The passivation film 56 is formed in contact with the p-type diffusion region 66. In the present embodiment, the region where the p-type diffusion region 56 is formed on the back surface of the silicon substrate 52 is covered with the passivation 56. The passivation film 56 is, for example, a silicon nitride film or a silicon oxynitride film. The thickness of the passivation film 56 is, for example, 5 to 100 nm.
　パッシベーション膜５８は、ｎ型拡散領域６４に接して形成される。本実施形態では、シリコン基板５２の裏面のうち、ｐ型拡散領域５６の形成された領域を除いた領域がパッシベーション５８で覆われている。パッシベーション膜５８は、例えば、シリコン窒化膜やシリコン酸窒化膜である。パッシベーション膜５８の厚さは、例えば、１０～２００ｎｍである。 The passivation film 58 is formed in contact with the n-type diffusion region 64. In the present embodiment, the region excluding the region where the p-type diffusion region 56 is formed on the back surface of the silicon substrate 52 is covered with the passivation 58. The passivation film 58 is, for example, a silicon nitride film or a silicon oxynitride film. The thickness of the passivation film 58 is, for example, 10 to 200 nm.
　電極６０は、ｎ型拡散領域６４に接して形成されている。これにより、電極６０がｎ型拡散領域６４に対して電気的に接続されている。電極６０は、例えば、銀からなる。 The electrode 60 is formed in contact with the n-type diffusion region 64. As a result, the electrode 60 is electrically connected to the n-type diffusion region 64. The electrode 60 is made of, for example, silver.
　電極６２は、ｐ型拡散領域６６に接して形成されている。これにより、電極６２がｐ型拡散領域６６に対して電気的に接続されている。電極６２は、例えば、銀からなる。 The electrode 62 is formed in contact with the p-type diffusion region 66. Thereby, the electrode 62 is electrically connected to the p-type diffusion region 66. The electrode 62 is made of silver, for example.
　ここで、シリコン基板５２の裏面のうち、ｐ型拡散領域６６の形成された領域以外の領域には、凹凸７０が形成されている。 Here, unevenness 70 is formed in a region other than the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate 52.
　凹凸７０は、例えば、テクスチャ構造である。凹凸７０は、規則性を有していてもよいし、ランダムであってもよい。凹凸７０の高低差は、テクスチャ構造６８の高低差と同じであってもよいし、異なっていてもよい。 The unevenness 70 has, for example, a texture structure. The unevenness 70 may have regularity or may be random. The height difference of the unevenness 70 may be the same as or different from the height difference of the texture structure 68.
　シリコン基板５２の裏面全体に対して凹凸７０の形成領域が占める割合は、好ましくは、２０～８０％である。この場合、短絡電流を増加させることができる。 The ratio of the formation region of the unevenness 70 to the entire back surface of the silicon substrate 52 is preferably 20 to 80%. In this case, the short circuit current can be increased.
　凹凸７０の高低差は、好ましくは、１～１０μｍである。この場合、短絡電流を増加させることができる。 The height difference of the unevenness 70 is preferably 1 to 10 μm. In this case, the short circuit current can be increased.
　シリコン基板５２の裏面のうち、ｐ型拡散領域６６が形成された領域の平均面粗さＲａは、０．７５ｎｍ以下であり、好ましくは、０．４０ｎｍ以下である。 Of the back surface of the silicon substrate 52, the average surface roughness Ra of the region where the p-type diffusion region 66 is formed is 0.75 nm or less, and preferably 0.40 nm or less.
　［光電変換素子の製造方法］
　続いて、図９Ａ～図９Ｅを参照しながら、光電変換素子５０の製造方法について説明する。 [Production Method of Photoelectric Conversion Element]
Next, a method for manufacturing the photoelectric conversion element 50 will be described with reference to FIGS. 9A to 9E.
　先ず、図９Ａに示すように、受光面の全体にテクスチャ構造６８を有するとともに、裏面の一部に凹凸７０を有するシリコン基板５２を準備する。具体的には、以下のとおりである。 First, as shown in FIG. 9A, a silicon substrate 52 having a texture structure 68 on the entire light receiving surface and having irregularities 70 on a part of the back surface is prepared. Specifically, it is as follows.
　最初に、所定の厚みを有するシリコン基板を、第１の実施の形態で説明した方法により準備する。続いて、スパッタ等により、シリコン基板の裏面にシリコン酸化膜を形成する。シリコン酸化膜の膜厚は、例えば、１００～１０００ｎｍである。その後、フォトリソグラフィ法により、シリコン酸化膜をパターニングする。これにより、シリコン基板の裏面の一部にのみ、シリコン酸化膜が残る。シリコン酸化膜が残っている領域は、後にｐ型拡散領域６６が形成される領域である。この状態で、シリコン基板をウェットエッチングする。これにより、受光面の全体にテクスチャ構造６８が形成され、且つ、裏面の一部に凹凸７０が形成される。 First, a silicon substrate having a predetermined thickness is prepared by the method described in the first embodiment. Subsequently, a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like. The film thickness of the silicon oxide film is, for example, 100 to 1000 nm. Thereafter, the silicon oxide film is patterned by photolithography. As a result, the silicon oxide film remains only on a part of the back surface of the silicon substrate. The region where the silicon oxide film remains is a region where the p-type diffusion region 66 is formed later. In this state, the silicon substrate is wet etched. Thereby, the texture structure 68 is formed on the entire light receiving surface, and the unevenness 70 is formed on a part of the back surface.
　なお、上記の方法では、受光面のテクスチャ３２と裏面の凹凸を同時に形成しているが、例えば、以下のようにして、別々に形成することもできる。 In the above method, the texture 32 on the light receiving surface and the unevenness on the back surface are formed at the same time. However, for example, they can be formed separately as follows.
　先ず、スパッタ等により、シリコン基板の裏面にシリコン酸化膜を形成する。シリコン酸化膜の膜厚は、例えば、１００～１０００ｎｍである。この状態でシリコン基板をウェットエッチングする。これにより、受光面の全体にテクスチャ構造３２が形成される。 First, a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like. The film thickness of the silicon oxide film is, for example, 100 to 1000 nm. In this state, the silicon substrate is wet etched. Thereby, the texture structure 32 is formed in the whole light-receiving surface.
　次に、スパッタ等により、テクスチャ構造３２の形成されたシリコン基板の受光面にシリコン酸化膜を形成する。シリコン酸化膜の膜厚は、例えば、１００～１０００ｎｍである。その後、フォトリソグラフィ法により、裏面のシリコン酸化膜をパターニングする。これにより、シリコン基板の受光面と裏面の一部にのみ、シリコン酸化膜が残った状態になる。このとき、裏面においてシリコン酸化膜が残っている領域は、後にｐ型拡散領域６６が形成される領域である。この状態で、シリコン基板をウェットエッチングする。これにより、裏面の一部に凹凸３４が形成される。このときの溶液の組成、濃度、温度、時間の条件は、上記の受光面のウェットエッチングのときと同じであってもよいが、異なっていてもよい。異なっている場合には、受光面のテクスチャとは異なる凹凸を形成することができる。 Next, a silicon oxide film is formed on the light receiving surface of the silicon substrate on which the texture structure 32 is formed by sputtering or the like. The film thickness of the silicon oxide film is, for example, 100 to 1000 nm. Thereafter, the silicon oxide film on the back surface is patterned by photolithography. As a result, the silicon oxide film remains only on a part of the light receiving surface and the back surface of the silicon substrate. At this time, the region where the silicon oxide film remains on the back surface is a region where the p-type diffusion region 66 is formed later. In this state, the silicon substrate is wet etched. Thereby, the unevenness | corrugation 34 is formed in a part of back surface. The conditions of the composition, concentration, temperature, and time of the solution at this time may be the same as those in the above-described wet etching of the light receiving surface, but may be different. If they are different, irregularities different from the texture of the light receiving surface can be formed.
　続いて、図９Ｂに示すように、シリコン基板５２の裏面側にｎ型拡散領域６４とｐ型拡散領域６６とを形成する。具体的には、以下のとおりである。 Subsequently, as shown in FIG. 9B, an n-type diffusion region 64 and a p-type diffusion region 66 are formed on the back side of the silicon substrate 52. Specifically, it is as follows.
　先ず、シリコン基板５２の受光面及び裏面にシリコン酸化膜を形成する。続いて、シリコン基板５２の裏面に形成されたシリコン酸化膜にエッチングペーストを印刷する。エッチングペーストを印刷する方法としては、例えば、スクリーン印刷法等がある。続いて、エッチングペーストが印刷されたシリコン基板５２を加熱する。これにより、シリコン基板５２の裏面に形成されたシリコン酸化膜のうち、エッチングペーストの印刷された部分のみが除去される。その後、シリコン基板５２を水中に浸し、超音波洗浄等を施す。これにより、エッチングペーストが除去される。 First, a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52. Subsequently, an etching paste is printed on the silicon oxide film formed on the back surface of the silicon substrate 52. Examples of a method for printing the etching paste include a screen printing method. Subsequently, the silicon substrate 52 on which the etching paste is printed is heated. As a result, only the portion where the etching paste is printed is removed from the silicon oxide film formed on the back surface of the silicon substrate 52. Thereafter, the silicon substrate 52 is immersed in water and subjected to ultrasonic cleaning or the like. Thereby, the etching paste is removed.
　続いて、ｐ型不純物としてのボロンを気相拡散させる。これにより、シリコン基板５２のうち、シリコン酸化膜で覆われていない部分にｐ型拡散領域６６が形成される。その後、シリコン基板５２の受光面及び裏面に形成されたシリコン酸化膜、及び、ボロンを気相拡散することで形成されたＢＳＧ（Boron Silicate Glass）膜等をフッ化水素水溶液等を用いて除去する。このときのフッ化水素水溶液としては、例えば、５.２重量％のフッ化水素酸水溶液を用いることができる。 Subsequently, boron as a p-type impurity is vapor-phase diffused. As a result, a p-type diffusion region 66 is formed in a portion of the silicon substrate 52 that is not covered with the silicon oxide film. Thereafter, the silicon oxide film formed on the light receiving surface and the back surface of the silicon substrate 52 and the BSG (Boron Silicate Glass) film formed by vapor-diffusing boron are removed using an aqueous hydrogen fluoride solution or the like. . As the hydrogen fluoride aqueous solution at this time, for example, a 5.2 wt% hydrofluoric acid aqueous solution can be used.
　続いて、シリコン基板５２の受光面及び裏面にシリコン酸化膜を形成する。続いて、シリコン基板５２の裏面に形成されたシリコン酸化膜をエッチングする。エッチングの方法としては、例えば、エッチングペーストを用いる方法がある。 Subsequently, a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52. Subsequently, the silicon oxide film formed on the back surface of the silicon substrate 52 is etched. As an etching method, for example, there is a method using an etching paste.
　続いて、ｎ型不純物としてのリンを気相拡散させる。これにより、シリコン基板５２のうち、シリコン酸化膜で覆われていない部分にｎ型拡散領域６４が形成される。その後、シリコン基板５２の受光面及び裏面に形成されたシリコン酸化膜、及び、リンを気相拡散することで形成されたＰＳＧ（Phosphorus Silicate Glass）膜等をフッ化水素水溶液等を用いて除去する。このときのフッ化水素水溶液としては、例えば、５.２重量％のフッ化水素酸水溶液を用いることができる。この状態において、シリコン基板の裏面のうち、ｐ型拡散領域６６が形成された領域の平均面粗さＲａは、０．７５ｎｍ以下になる。 Subsequently, phosphorus as an n-type impurity is vapor-phase diffused. Thereby, an n-type diffusion region 64 is formed in a portion of the silicon substrate 52 that is not covered with the silicon oxide film. Thereafter, the silicon oxide film formed on the light receiving surface and the back surface of the silicon substrate 52, the PSG (Phosphorus Silicate Glass) film formed by vapor phase diffusion of phosphorus, and the like are removed using a hydrogen fluoride aqueous solution or the like. . As the hydrogen fluoride aqueous solution at this time, for example, a 5.2 wt% hydrofluoric acid aqueous solution can be used. In this state, the average surface roughness Ra of the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate is 0.75 nm or less.
　続いて、図９Ｃに示すように、シリコン基板５２の裏面のうち、ｐ型拡散領域６６が形成された領域をパッシベーション膜５６で覆い、それ以外の領域をパッシベーション膜５８で覆う。具体的には、以下のとおりである。 Subsequently, as shown in FIG. 9C, the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate 52 is covered with the passivation film 56, and the other region is covered with the passivation film 58. Specifically, it is as follows.
　先ず、シリコン基板５２に対して、熱酸化処理を行う。これにより、シリコン基板５２の受光面及び裏面にシリコン酸化膜が形成される。続いて、シリコン基板５２の裏面に形成されたシリコン酸化膜をエッチングする。エッチングの方法としては、例えば、エッチングペーストを用いる方法がある。シリコン酸化膜をエッチングすることにより、シリコン酸化膜のうち、ｐ型拡散領域６６に接する部分のみが残る。 First, a thermal oxidation process is performed on the silicon substrate 52. Thereby, a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52. Subsequently, the silicon oxide film formed on the back surface of the silicon substrate 52 is etched. As an etching method, for example, there is a method using an etching paste. By etching the silicon oxide film, only the portion of the silicon oxide film that is in contact with the p-type diffusion region 66 remains.
　続いて、シリコン基板５２の裏面、及び、パッシベーション膜５６を覆うパッシベーション膜５８を形成する。パッシベーション膜５８は、例えば、プラズマＣＶＤ法により形成できる。 Subsequently, a passivation film 58 that covers the back surface of the silicon substrate 52 and the passivation film 56 is formed. The passivation film 58 can be formed by, for example, a plasma CVD method.
　続いて、シリコン基板５２の受光面に形成されたシリコン酸化膜をフッ化水素水溶液等を用いて除去する。これにより、図９Ｃに示すように、シリコン基板５２の受光面が露出され、且つ、シリコン基板５２の裏面がパッシベーション膜５６、５８で覆われる。 Subsequently, the silicon oxide film formed on the light receiving surface of the silicon substrate 52 is removed using a hydrogen fluoride aqueous solution or the like. 9C, the light receiving surface of the silicon substrate 52 is exposed, and the back surface of the silicon substrate 52 is covered with the passivation films 56 and 58.
　続いて、図９Ｄに示すように、シリコン基板５２の受光面に反射防止膜５４を形成する。反射防止膜５４は、例えば、プラズマＣＶＤ法等で形成できる。 Subsequently, as shown in FIG. 9D, an antireflection film 54 is formed on the light receiving surface of the silicon substrate 52. The antireflection film 54 can be formed by, for example, a plasma CVD method or the like.
　続いて、図９Ｅに示すように、電極６０、６２を形成する。具体的には、以下のとおりである。 Subsequently, as shown in FIG. 9E, electrodes 60 and 62 are formed. Specifically, it is as follows.
　先ず、パッシベーション膜５６、５８の一部をエッチングにより除去して、コンタクトホールを形成する。エッチングの方法としては、例えば、エッチングペーストを用いる方法等がある。 First, a part of the passivation films 56 and 58 is removed by etching to form a contact hole. Examples of the etching method include a method using an etching paste.
　続いて、コンタクトホールが形成された領域に、銀ペーストを印刷し、焼成する。これにより、電極６０、６２が形成され、目的とする光電変換素子５０が得られる。 Subsequently, a silver paste is printed and fired in the region where the contact hole is formed. Thereby, the electrodes 60 and 62 are formed, and the target photoelectric conversion element 50 is obtained.
　このような光電変換素子５０においても、第１の実施の形態と同様な効果を得ることができる。 Also in such a photoelectric conversion element 50, the same effect as that of the first embodiment can be obtained.
　［第２の実施の形態の応用例］
　例えば、シリコン基板５２の裏面のうち、ｎ型拡散領域６４が形成された領域の平均面粗さＲａを０．７５ｎｍとし、且つ、シリコン基板５２の裏面のうち、ｎ型拡散領域６４の形成領域以外の領域に凹凸７０を形成してもよい。 [Application example of second embodiment]
For example, the average surface roughness Ra of the region where the n-type diffusion region 64 is formed in the back surface of the silicon substrate 52 is 0.75 nm, and the region where the n-type diffusion region 64 is formed in the back surface of the silicon substrate 52 The unevenness 70 may be formed in a region other than the above.
　以下、本発明の実施の形態による光電変換素子を備える光電変換モジュール及び太陽光発電システムについて説明する。 Hereinafter, a photoelectric conversion module including a photoelectric conversion element according to an embodiment of the present invention and a solar power generation system will be described.
　本発明の実施の形態による光電変換素子は、高い変換効率を有する。そのため、本発明の実施の形態による光電変換素子を備える光電変換モジュール及び太陽光発電システムも高い変換効率を有することができる。 The photoelectric conversion element according to the embodiment of the present invention has high conversion efficiency. Therefore, the photoelectric conversion module and the photovoltaic power generation system including the photoelectric conversion element according to the embodiment of the present invention can also have high conversion efficiency.
　［光電変換モジュール］
　図１０は、本実施形態に係る光電変換モジュールの構成の一例を示す概略図である。図１０を参照して光電変換モジュール１０００は、複数の光電変換素子１００１と、カバー１００２と、出力端子１０１３，１０１４とを備える。 [Photoelectric conversion module]
FIG. 10 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module according to the present embodiment. Referring to FIG. 10, the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1013 and 1014.
　複数の光電変換素子１００１はアレイ状に配列され直列に接続されている。図１０では、光電変換素子１００１を直列に接続する配列を図示しているが、配列および接続方式はこれに限定されず、並列に接続して配列してもよいし、直列と並列とを組み合わせた配列としてもよい。複数の光電変換素子１００１の各々には、本発明の実施の形態による光電変換素子が用いられる。なお、光電変換モジュール１０００に含まれる光電変換素子１００１の数は、２以上の任意の整数とすることができる。 A plurality of photoelectric conversion elements 1001 are arranged in an array and connected in series. In FIG. 10, an arrangement in which the photoelectric conversion elements 1001 are connected in series is illustrated, but the arrangement and connection method are not limited thereto, and the photoelectric conversion elements 1001 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement. For each of the plurality of photoelectric conversion elements 1001, the photoelectric conversion element according to the embodiment of the present invention is used. Note that the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 can be any integer of 2 or more.
　カバー１００２は、耐候性のカバーから構成されており、複数の光電変換素子１００１を覆う。 The cover 1002 is composed of a weatherproof cover and covers the plurality of photoelectric conversion elements 1001.
　出力端子１０１３は、直列に接続された複数の光電変換素子１００１の一方端に配置される光電変換素子１００１に接続される。 The output terminal 1013 is connected to a photoelectric conversion element 1001 arranged at one end of a plurality of photoelectric conversion elements 1001 connected in series.
　出力端子１０１４は、直列に接続された複数の光電変換素子１００１の他方端に配置される光電変換素子１００１に接続される。 The output terminal 1014 is connected to the photoelectric conversion element 1001 arranged at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
　［太陽光発電システム］
　図１１は、本実施形態に係る太陽光発電システムの構成の一例を示す概略図である。図１１を参照して、太陽光発電システム２０００は、光電変換モジュールアレイ２００１と、接続箱２００２と、パワーコンディショナ２００３と、分電盤２００４と、電力メータ２００５とを備える。後述するように光電変換モジュールアレイ２００１は複数の光電変換モジュール１０００から構成される。 [Solar power system]
FIG. 11 is a schematic diagram illustrating an example of the configuration of the photovoltaic power generation system according to the present embodiment. Referring to FIG. 11, solar power generation system 2000 includes a photoelectric conversion module array 2001, a connection box 2002, a power conditioner 2003, a distribution board 2004, and a power meter 2005. As will be described later, the photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000.
　太陽光発電システム２０００には、一般に「ホーム・エネルギー・マネジメント・システム（ＨＥＭＳ：Home Energy Management System）」と呼ばれる機能を付加することができる。これにより部屋ごとの電力使用状況を監視しつつ個別の家単位で節電に貢献することもできる。 The solar power generation system 2000 can be added with a function generally called “Home Energy Management System (HEMS)”. As a result, it is possible to contribute to power saving for each individual house while monitoring the power usage status of each room.
　接続箱２００２は、光電変換モジュールアレイ２００１に接続される。パワーコンディショナ２００３は、接続箱２００２に接続される。分電盤２００４は、パワーコンディショナ２００３及び電気機器類２０１１に接続される。電力メータ２００５は、分電盤２００４及び系統連系に接続される。 The connection box 2002 is connected to the photoelectric conversion module array 2001. The power conditioner 2003 is connected to the connection box 2002. The distribution board 2004 is connected to the power conditioner 2003 and the electrical equipment 2011. The power meter 2005 is connected to the distribution board 2004 and the grid connection.
　続いて、太陽光発電システム２０００の動作を説明する。 Subsequently, the operation of the photovoltaic power generation system 2000 will be described.
　光電変換モジュールアレイ２００１は、太陽光を電気に変換して直流電力を発電し、直流電力を接続箱２００２へ供給する。 The photoelectric conversion module array 2001 generates sunlight by converting sunlight into electricity, and supplies the DC power to the connection box 2002.
　接続箱２００２は、光電変換モジュールアレイ２００１が発電した直流電力を受け、直流電力をパワーコンディショナ２００３へ供給する。 The connection box 2002 receives DC power generated by the photoelectric conversion module array 2001 and supplies DC power to the power conditioner 2003.
　パワーコンディショナ２００３は、接続箱２００２から受けた直流電力を交流電力に変換して分電盤２００４へ供給する。あるいは、接続箱２００２から受けた直流電力の一部を交流電力に変換せずに、直流電力のままで分電盤２００４へ供給してもよい。 The power conditioner 2003 converts the DC power received from the connection box 2002 into AC power and supplies it to the distribution board 2004. Alternatively, a part of the DC power received from the connection box 2002 may be supplied to the distribution board 2004 as it is without being converted into AC power.
　分電盤２００４は、パワーコンディショナ２００３から受けた交流電力及び電力メータ２００５を介して受けた商用電力の少なくともいずれかを電気機器類２０１１へ供給する。分電盤２００４は、パワーコンディショナ２００３から受けた交流電力が電気機器類２０１１の消費電力よりも多いとき、パワーコンディショナ２００３から受けた交流電力を電気機器類２０１１へ供給する。分電盤２００４は、余った交流電力を、電力メータ２００５を介して、系統連系へ供給する。 Distribution board 2004 supplies at least one of AC power received from power conditioner 2003 and commercial power received via power meter 2005 to electrical equipment 2011. The distribution board 2004 supplies the AC power received from the power conditioner 2003 to the electrical equipment 2011 when the AC power received from the power conditioner 2003 is larger than the power consumption of the electrical equipment 2011. The distribution board 2004 supplies the surplus AC power to the grid connection via the power meter 2005.
　分電盤２００４は、パワーコンディショナ２００３から受けた交流電力が電気機器類２０１１の消費電力よりも少ないとき、系統連系から受けた交流電力及びパワーコンディショナ２００３から受けた交流電力を電気機器類２０１１へ供給する。 When the AC power received from the power conditioner 2003 is less than the power consumption of the electrical equipment 2011, the distribution board 2004 uses the AC power received from the grid connection and the AC power received from the power conditioner 2003 to the electrical equipment. To 2011.
　電力メータ２００５は、系統連系から分電盤２００４へ向かう方向の電力を計測するとともに、分電盤２００４から系統連系へ向かう方向の電力を計測する。 The power meter 2005 measures the power in the direction from the grid connection to the distribution board 2004 and measures the power in the direction from the distribution board 2004 to the grid connection.
　続いて、光電変換モジュールアレイ２００１について説明する。 Subsequently, the photoelectric conversion module array 2001 will be described.
　図１２は、図１１に示す光電変換モジュールアレイ２００１の構成の一例を示す概略図である。図１２を参照して、光電変換モジュールアレイ２００１は、複数の光電変換モジュール１０００と出力端子２０１３，２０１４とを含む。 FIG. 12 is a schematic diagram showing an example of the configuration of the photoelectric conversion module array 2001 shown in FIG. Referring to FIG. 12, photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 and output terminals 2013 and 2014.
　複数の光電変換モジュール１０００は、アレイ状に配列され直列に接続されている。図１２では、光電変換モジュール１０００を直列に接続する配列を図示しているが、配列および接続方式はこれに限定されず、並列に接続して配列してもよいし、直列と並列とを組み合わせた配列としてもよい。なお、光電変換モジュールアレイ２００１に含まれる光電変換モジュール１０００の数は、２以上の任意の整数とすることができる。 The plurality of photoelectric conversion modules 1000 are arranged in an array and connected in series. Although FIG. 12 illustrates an arrangement in which the photoelectric conversion modules 1000 are connected in series, the arrangement and connection method are not limited to this, and the photoelectric conversion modules 1000 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement. Note that the number of photoelectric conversion modules 1000 included in the photoelectric conversion module array 2001 can be any integer of 2 or more.
　出力端子２０１３は、直列に接続された複数の光電変換モジュール１０００の一方端に位置する光電変換モジュール１０００に接続される。 The output terminal 2013 is connected to the photoelectric conversion module 1000 located at one end of the plurality of photoelectric conversion modules 1000 connected in series.
　出力端子２０１４は、直列に接続された複数の光電変換モジュール１０００の他方端に位置する光電変換モジュール１０００に接続される。 The output terminal 2014 is connected to the photoelectric conversion module 1000 located at the other end of the plurality of photoelectric conversion modules 1000 connected in series.
　なお、以上の説明はあくまでも一例であり、本実施形態の太陽光発電システムは、本発明の実施の形態による光電変換素子を備える限り、上記の説明に限定されず如何なる構成もとり得るものとする。 The above description is merely an example, and the solar power generation system of the present embodiment is not limited to the above description as long as it includes the photoelectric conversion element according to the embodiment of the present invention, and can take any configuration.
　［大規模太陽光発電システム］
　図１３は、太陽光発電システムの構成の他の一例を示す概略図である。図１３に示す太陽光発電システムは、図１１に示す太陽光発電システムよりも大規模な太陽光発電システムである。図１３に示す太陽光発電システムも、本発明の実施の形態による光電変換素子を備える。 [Large-scale solar power generation system]
FIG. 13 is a schematic diagram illustrating another example of the configuration of the photovoltaic power generation system. The photovoltaic power generation system shown in FIG. 13 is a larger scale photovoltaic power generation system than the photovoltaic power generation system shown in FIG. The photovoltaic power generation system shown in FIG. 13 also includes the photoelectric conversion element according to the embodiment of the present invention.
　図１３を参照して、太陽光発電システム４０００は、複数のサブシステム４００１と、複数のパワーコンディショナ４００３と、変圧器４００４とを備える。 Referring to FIG. 13, solar power generation system 4000 includes a plurality of subsystems 4001, a plurality of power conditioners 4003, and a transformer 4004.
　複数のパワーコンディショナ４００３は、それぞれサブシステム４００１に接続される。太陽光発電システム４０００において、パワーコンディショナ４００３及びそれに接続されるサブシステム４００１の数は、２以上の任意の整数とすることができる。 The plurality of power conditioners 4003 are each connected to the subsystem 4001. In the photovoltaic power generation system 4000, the number of the power conditioners 4003 and the subsystems 4001 connected thereto can be any integer of 2 or more.
　変圧器４００４は、複数のパワーコンディショナ４００３および系統連系に接続される。 The transformer 4004 is connected to a plurality of power conditioners 4003 and grid interconnection.
　複数のサブシステム４００１の各々は、複数のモジュールシステム３０００から構成される。サブシステム４００１内のモジュールシステム３０００の数は、２以上の任意の整数とすることができる。 Each of the plurality of subsystems 4001 includes a plurality of module systems 3000. The number of module systems 3000 in the subsystem 4001 can be any integer greater than or equal to two.
　複数のモジュールシステム３０００の各々は、複数の光電変換モジュールアレイ２００１と、複数の接続箱３００２と、集電箱３００４とを含む。モジュールシステム３０００内の接続箱３００２及びそれに接続される光電変換モジュールアレイ２００１の数は、２以上の任意の整数とすることができる。 Each of the plurality of module systems 3000 includes a plurality of photoelectric conversion module arrays 2001, a plurality of connection boxes 3002, and a current collection box 3004. The number of the junction box 3002 in the module system 3000 and the photoelectric conversion module array 2001 connected to the junction box 3002 can be any integer of 2 or more.
　集電箱３００４は、複数の接続箱３００２に接続される。パワーコンディショナ４００３は、サブシステム４００１内の複数の集電箱３００４に接続される。 The current collection box 3004 is connected to a plurality of connection boxes 3002. The power conditioner 4003 is connected to a plurality of current collection boxes 3004 in the subsystem 4001.
　続いて、太陽光発電システム４０００の動作を説明する。 Subsequently, the operation of the photovoltaic power generation system 4000 will be described.
　モジュールシステム３０００の複数の光電変換モジュールアレイ２００１は、太陽光を電気に変換して直流電力を発電し、直流電力を、接続箱３００２を介して、集電箱３００４へ供給する。サブシステム４００１内の複数の集電箱３００４は、直流電力をパワーコンディショナ４００３へ供給する。複数のパワーコンディショナ４００３は、直流電力を交流電力に変換して、交流電力を変圧器４００４へ供給する。 The plurality of photoelectric conversion module arrays 2001 of the module system 3000 convert sunlight into electricity to generate DC power, and supply the DC power to the current collection box 3004 via the connection box 3002. A plurality of current collection boxes 3004 in the subsystem 4001 supplies DC power to the power conditioner 4003. The plurality of power conditioners 4003 convert DC power into AC power and supply the AC power to the transformer 4004.
　変圧器４００４は、複数のパワーコンディショナ４００３から受けた交流電力の電圧レベルを変換して系統連系へ供給する。 The transformer 4004 converts the voltage level of AC power received from the plurality of power conditioners 4003 and supplies it to the grid interconnection.
　なお太陽光発電システム４０００は、本発明の実施の形態による光電変換素子を備えるものであればよく、太陽光発電システム４０００に含まれる全ての光電変換素子が本発明の実施の形態による光電変換素子でなくてもよい。例えば、あるサブシステム４００１に含まれる光電変換素子の全てが本発明の実施の形態による光電変換素子であり、別のサブシステム４００１に含まれる光電変換素子の一部もしくは全部が、本発明の実施の形態による光電変換素子でない場合もあり得るものとする。 The photovoltaic power generation system 4000 only needs to include the photoelectric conversion element according to the embodiment of the present invention, and all the photoelectric conversion elements included in the photovoltaic power generation system 4000 are the photoelectric conversion elements according to the embodiment of the present invention. Not necessarily. For example, all of the photoelectric conversion elements included in one subsystem 4001 are the photoelectric conversion elements according to the embodiment of the present invention, and part or all of the photoelectric conversion elements included in another subsystem 4001 are the implementation of the present invention. In some cases, the photoelectric conversion element may not be a photoelectric conversion element.
　以上、本発明の実施形態について、詳述してきたが、これらはあくまでも例示であって、本発明は、上述の実施形態によって、何等、限定されない。 As mentioned above, although embodiment of this invention has been explained in full detail, these are illustrations to the last and this invention is not limited at all by the above-mentioned embodiment.

Claims (5)

  1. 　シリコン基板と、
    　第１導電型を有し、前記シリコン基板の裏面側に形成された第１半導体層と、
    　前記第１導電型と反対の第２導電型を有し、前記シリコン基板の裏面側に形成された第２半導体層と、
    　前記第１半導体層に接して形成された第１電極と、
    　前記第２半導体層に接して形成された第２電極とを備え、
    　前記シリコン基板の裏面であって、且つ、前記第１半導体層が形成された領域には、凹凸が形成され、
    　前記シリコン基板の裏面であって、且つ、前記第２半導体層が形成された領域では、平均面粗さＲａが０．７５ｎｍ以下である、裏面接合型の光電変換素子。     A silicon substrate;
    A first semiconductor layer having a first conductivity type and formed on the back side of the silicon substrate;
    A second semiconductor layer having a second conductivity type opposite to the first conductivity type and formed on the back side of the silicon substrate;
    A first electrode formed in contact with the first semiconductor layer;
    A second electrode formed in contact with the second semiconductor layer,
    On the back surface of the silicon substrate and in the region where the first semiconductor layer is formed, irregularities are formed,
    A back junction type photoelectric conversion element having an average surface roughness Ra of 0.75 nm or less in a region on the back surface of the silicon substrate and in which the second semiconductor layer is formed.
  2. 　請求項１に記載の裏面接合型の光電変換素子であって、
    　前記平均面粗さＲａが０．４０ｎｍ以下である、裏面接合型の光電変換素子。     The back junction type photoelectric conversion element according to claim 1,
    A back junction type photoelectric conversion element having an average surface roughness Ra of 0.40 nm or less.
  3. 　請求項１又は２に記載の裏面接合型の光電変換素子であって、
    　前記第１半導体層が、前記シリコン基板中に形成され、前記第１導電型の不純物が拡散された第１拡散領域であり、
    　前記第２半導体層が、前記シリコン基板中に形成され、前記第２導電型の不純物が拡散された第２拡散領域である、裏面接合型の光電変換素子。     The back junction type photoelectric conversion element according to claim 1 or 2,
    The first semiconductor layer is a first diffusion region formed in the silicon substrate and in which the impurity of the first conductivity type is diffused;
    A back junction type photoelectric conversion element, wherein the second semiconductor layer is a second diffusion region formed in the silicon substrate and in which the second conductivity type impurity is diffused.
  4. 　請求項１又は２に記載の裏面接合型の光電変換素子であって、
    　前記シリコン基板の裏面に接して形成され、真性の非晶質半導体からなる真性非晶質半導体層をさらに備え、
    　前記第１半導体層が、前記真性非晶質半導体層に接して形成され、前記第１導電型の不純物を含む非晶質半導体からなる第１非晶質半導体層であり、
    　前記第２半導体層が、前記真性非晶質半導体層に接して形成され、前記第２導電型の不純物を含む非晶質半導体からなる第２非晶質半導体層である、裏面接合型の光電変換素子。     The back junction type photoelectric conversion element according to claim 1 or 2,
    Further comprising an intrinsic amorphous semiconductor layer formed in contact with the back surface of the silicon substrate and made of an intrinsic amorphous semiconductor;
    The first semiconductor layer is a first amorphous semiconductor layer formed in contact with the intrinsic amorphous semiconductor layer and made of an amorphous semiconductor containing an impurity of the first conductivity type;
    The second semiconductor layer is a second amorphous semiconductor layer formed in contact with the intrinsic amorphous semiconductor layer and made of an amorphous semiconductor containing the second conductivity type impurity. Conversion element.
  5. 　請求項１～４の何れか１項に記載の裏面接合型の光電変換素子を用いた光電変換素子モジュールを含む太陽光発電システム。 A solar power generation system including a photoelectric conversion element module using the back junction type photoelectric conversion element according to any one of claims 1 to 4.
PCT/JP2015/051340 2014-02-13 2015-01-20 Back-junction photoelectric conversion element and solar photovoltaic power generation system WO2015122242A1 (en)

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