JP2013187287A - Photoelectric conversion element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion element that allows preventing an increase in the contact resistance between a first semiconductor layer and a first electrode even if the width dimension of the first semiconductor layer is small in an in-plane direction of a silicon substrate.SOLUTION: A photoelectric conversion element 10 includes a silicon substrate 12, a first semiconductor layer 18, a second semiconductor layer 20, a first electrode 24n, and a second electrode 24p. The silicon substrate 12 has a first conductivity type. The first semiconductor layer 18 has the first conductivity type and is formed on a rear-surface side of the silicon substrate 12. The second semiconductor layer 20 has a second conductivity type opposite the first conductivity type, is formed adjacent to the first semiconductor layer in an in-plane direction of the silicon substrate 12, and has a larger width dimension in the in-plane direction of the silicon substrate 12 than the first semiconductor layer 18. The first electrode 24n is formed on the first semiconductor layer 18. The second electrode 24p is formed on the second semiconductor layer 20. The contact interface between the first electrode 24n and the first semiconductor layer 18 has an irregularity 22.

Description

  The present invention relates to a photoelectric conversion element, and more particularly to a back junction solar cell.

  In recent years, solar cells as photoelectric conversion elements have attracted attention. Solar cells include back junction solar cells.

  A back junction solar cell is disclosed in, for example, Japanese Patent Application Laid-Open No. 2006-332273. The back junction solar cell includes a silicon substrate, a first doping region (first semiconductor layer), a second doping region (second semiconductor layer), a first electrode, and a second electrode. The silicon substrate has a first conductivity type. The first doping region includes a first conductivity type dopant and is formed on the back side of the silicon substrate. The second doping region includes a dopant of a second conductivity type opposite to the first conductivity type, and is formed on the back surface side of the silicon substrate. The first electrode is formed on the first doping region. The second electrode is formed on the second doping region.

  In the back junction solar cell, in order to improve the conversion efficiency, it is necessary to make the width of the first doping region smaller than the width of the second diffusion region in the in-plane direction of the silicon substrate. Therefore, the contact area between the first electrode for extracting majority carriers and the first doping region is reduced. As a result, the contact resistance between the first electrode and the first doping region is increased.

JP 2006-332273 A

  The object of the present invention is to increase the contact resistance between the first electrode and the first semiconductor layer even if the width dimension of the first semiconductor layer is smaller than the width dimension of the second semiconductor layer in the in-plane direction of the silicon substrate. It is providing the photoelectric conversion element which can suppress this.

  The photoelectric conversion element of the present invention includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The silicon substrate has a first conductivity type. The first semiconductor layer has a first conductivity type and is formed on the back side of the silicon substrate. The second semiconductor layer has a second conductivity type opposite to the first conductivity type, and is formed adjacent to the first semiconductor layer in the in-plane direction of the silicon substrate, and more than the first semiconductor layer. The width dimension in the in-plane direction is large. The first electrode is formed on the first semiconductor layer. The second electrode is formed on the second semiconductor layer. Irregularities are formed at the contact interface between the first electrode and the first semiconductor layer.

  The photoelectric conversion element of the present invention has a large contact resistance between the first electrode and the first semiconductor layer even when the width dimension of the first semiconductor layer is smaller than the width dimension of the second semiconductor layer in the in-plane direction of the silicon substrate. Can be suppressed.

FIG. 1 is a cross-sectional view illustrating an example of a schematic configuration of the photoelectric conversion element according to the first embodiment of the present invention. 2A is a cross-sectional view for explaining a method of manufacturing the photoelectric conversion element shown in FIG. 1, in which a texture structure is formed on the entire light receiving surface of the silicon substrate, and unevenness is formed on a part of the back surface of the silicon substrate. It is sectional drawing which shows the state in which was formed. 2B is a cross-sectional view for explaining the method of manufacturing the photoelectric conversion element shown in FIG. 1, and shows a state in which an n-type diffusion region and a p-type diffusion region are formed on the back surface side of the silicon substrate. It is. FIG. 2C is a cross-sectional view for explaining the manufacturing method of the photoelectric conversion element shown in FIG. 1, and is a cross-sectional view showing a state in which a passivation film is formed on the light receiving surface of the silicon substrate. 2D is a cross-sectional view for explaining the method of manufacturing the photoelectric conversion element shown in FIG. 1, and is a cross-sectional view showing a state in which an electrode is formed on the back surface of the silicon substrate. FIG. 3 is a cross-sectional view illustrating an example of a schematic configuration of a photoelectric conversion element according to Application Example 1 of the first embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating an example of a schematic configuration of a photoelectric conversion element according to Application Example 2 of the first embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating an example of a schematic configuration of a photoelectric conversion element according to the second embodiment of the present invention. 6A is a cross-sectional view for explaining the method of manufacturing the photoelectric conversion element shown in FIG. 5, in which a texture structure is formed on the entire light receiving surface of the silicon substrate, and unevenness is formed on a part of the back surface of the silicon substrate. It is sectional drawing which shows the state in which was formed. FIG. 6B is a cross-sectional view for explaining the method of manufacturing the photoelectric conversion element shown in FIG. 5, and is a cross-sectional view showing a state where an intrinsic amorphous silicon layer is formed on the back surface of the silicon substrate. 6C is a cross-sectional view for explaining the method of manufacturing the photoelectric conversion element shown in FIG. 5, and shows a state in which a p-type amorphous silicon layer is formed on the intrinsic amorphous silicon layer. is there. 6D is a cross-sectional view for explaining the method of manufacturing the photoelectric conversion element shown in FIG. 5, and shows a state in which an n-type amorphous silicon layer is formed on the intrinsic amorphous silicon layer. is there. FIG. 6E is a cross-sectional view for explaining the method of manufacturing the photoelectric conversion element shown in FIG. 5, and is a cross-sectional view showing a state where a passivation film is formed on the light receiving surface of the silicon substrate. FIG. 6F is a cross-sectional view for explaining the method of manufacturing the photoelectric conversion element shown in FIG. 5, and is a cross-sectional view showing a state where electrodes are formed. FIG. 7: is sectional drawing which shows an example of schematic structure of the photoelectric conversion element which concerns on the application example 1 of the 2nd Embodiment of this invention. FIG. 8: is sectional drawing which shows an example of schematic structure of the photoelectric conversion element which concerns on the application example 2 of the 2nd Embodiment of this invention.

  A photoelectric conversion element according to an embodiment of the present invention includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The silicon substrate has a first conductivity type. The first semiconductor layer has a first conductivity type and is formed on the back side of the silicon substrate. The second semiconductor layer has a second conductivity type opposite to the first conductivity type, and is formed adjacent to the first semiconductor layer in the in-plane direction of the silicon substrate, and more than the first semiconductor layer. The width dimension in the in-plane direction is large. The first electrode is formed on the first semiconductor layer. The second electrode is formed on the second semiconductor layer. Irregularities are formed at the contact interface between the first electrode and the first semiconductor layer.

  In this case, the first semiconductor layer has the same conductivity type as the silicon substrate. On the other hand, the second semiconductor layer has a conductivity type opposite to that of the silicon substrate. That is, the first electrode formed on the first semiconductor layer collects majority carriers, and the second electrode formed on the second semiconductor layer collects minority carriers.

  In the in-plane direction of the silicon substrate, the width dimension of the first semiconductor layer is smaller than the width dimension of the second semiconductor layer. Therefore, the contact area between the first electrode and the first semiconductor layer is smaller than the contact area between the second electrode and the second semiconductor layer. That is, the contact resistance between the first electrode that collects majority carriers and the first semiconductor layer is larger than the contact resistance between the second electrode that collects minority carriers and the second semiconductor layer.

  Here, unevenness is formed at the contact interface between the first electrode and the first semiconductor layer. Therefore, the contact area between the first electrode and the first semiconductor layer increases. As a result, even if the width dimension of the first semiconductor layer is smaller than the width dimension of the second semiconductor layer in the in-plane direction of the silicon substrate, it is possible to suppress an increase in contact resistance between the first electrode and the first semiconductor layer. Can do.

  Hereinafter, more specific embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. Note that, in the drawings referred to below, the configuration is shown in a simplified or schematic manner, or some components are omitted for easy understanding of the description. Further, the dimensional ratio between the constituent members shown in each drawing does not necessarily indicate an actual dimensional ratio.

[First Embodiment]
FIG. 1 shows a photoelectric conversion element 10 according to the first embodiment of the present invention. The photoelectric conversion element 10 is a back junction solar cell.

[Overall configuration of photoelectric conversion element]
The photoelectric conversion element 10 includes a silicon substrate 12, a passivation film 16, an electrode (first electrode) 24n, and an electrode (second electrode) 24p. The silicon substrate 12 is made of an n-type single crystal silicon substrate, and includes an n-type diffusion region (first semiconductor layer) 18 and a p-type diffusion region (second semiconductor layer) 20. The thickness of the silicon substrate 12 is, for example, 100 to 300 μm. The specific resistance of the silicon substrate 12 is, for example, 1.0 to 10.0 Ω · cm.

  A texture structure 14 is formed on the light receiving surface of the silicon substrate 12. Thereby, the light incident on the silicon substrate 12 can be confined and the light use efficiency can be improved.

  The plane orientation of the silicon substrate 12 is preferably (100). Thereby, formation of the texture structure 14 becomes easy.

  The light receiving surface of the silicon substrate 12 is covered with a passivation film 16. The passivation film 16 is, for example, a silicon nitride film. The thickness of the passivation film 16 is, for example, 50 to 100 nm.

  On the back surface side of the silicon substrate 12 (the lower surface side in FIG. 1), n-type diffusion regions 18 and p-type diffusion regions 20 are alternately formed in the in-plane direction of the silicon substrate 12. In the example shown in FIG. 1, both the n-type diffusion region 18 and the p-type diffusion region 20 extend in a direction perpendicular to the paper surface of FIG.

The impurity concentration of the n-type diffusion region 18 is, for example, 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The depth dimension (the vertical dimension in FIG. 1) of the n-type diffusion region 18 is, for example, 0.3 to 1.0 μm.

The impurity concentration of the p-type diffusion region 20 is, for example, 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The depth dimension (vertical dimension in FIG. 1) of the p-type diffusion region 20 is, for example, 0.3 to 1.0 μm.

  In the in-plane direction of the silicon substrate 12, the width dimension of the n-type diffusion region 18 is smaller than the width dimension of the p-type diffusion region 20. As the ratio of the area of the p-type diffusion region 20 to the sum of the area of the n-type diffusion region 18 and the area of the p-type diffusion region 20 (area ratio of the p-type diffusion region 20) increases, the photogenerated minority carriers (holes) However, the distance that must be moved before reaching the p-type diffusion region 20 is reduced. Therefore, the number of holes that recombine before reaching the p-type diffusion region 20 decreases, and the short-circuit photocurrent increases. Therefore, the conversion efficiency of the photoelectric conversion element 10 is improved. A preferable area ratio of the p-type diffusion region 20 is 63 to 90%.

  Concavities and convexities 22 are formed on the surface of the n-type diffusion region 18. In the example illustrated in FIG. 1, the unevenness 22 has a texture structure. The irregularities 22 may have regularity or may be random. The height difference of the unevenness 22 is, for example, 1 to 20 μm. The height difference of the unevenness 22 may be the same as or different from the height difference of the texture structure 14. In the example shown in FIG. 1, the irregularities 22 are formed on the entire surface of the n-type diffusion region 18. In the example shown in FIG. 1, the depth dimension of the n-type diffusion region 18 is substantially constant throughout the n-type diffusion region 18.

  An electrode 24 n is formed on the n-type diffusion region 18. As a result, the electrode 24n is electrically connected to the n-type diffusion region 18. The electrode 24n is, for example, silver. The surface of the electrode 24n that contacts the n-type diffusion region 18 has a shape corresponding to the irregularities 22.

  An electrode 24 p is formed on the p-type diffusion region 20. Thereby, the electrode 24p is electrically connected to the p-type diffusion region 20. The electrode 24p is, for example, silver.

[Production Method of Photoelectric Conversion Element]
Then, the manufacturing method of the photoelectric conversion element 10 is demonstrated, referring FIG. 2A-FIG. 2D.

  First, as shown in FIG. 2A, a silicon substrate 12 having a texture structure 14 on the entire light receiving surface and having irregularities 22 on a part of the back surface is prepared.

  A method for forming the texture structure 14 and the unevenness 22 is, for example, as follows.

  First, a silicon oxide film as a mask is formed on the back surface of the silicon substrate 12. The silicon oxide film is formed by, for example, thermal CVD.

  Subsequently, the silicon oxide film formed on the silicon substrate 12 is patterned. Thereby, an opening is formed in the silicon oxide film. The patterning is performed by, for example, photolithography and etching. The opening is formed at a position where the n-type diffusion region 18 is formed later.

  Subsequently, wet etching is performed on the entire light receiving surface and part of the back surface of the silicon substrate 12. Thereby, the texture structure 14 is formed on the entire light receiving surface of the silicon substrate 12, and the unevenness 22 is formed on a part of the back surface of the silicon substrate 12. The wet etching is performed using, for example, an alkaline solution. The wet etching time is, for example, 10 to 60 minutes. The alkaline solution used for wet etching is, for example, NaOH or KOH, and its concentration is, for example, 5%.

  Subsequently, the silicon oxide film formed on the back surface of the silicon substrate 12 is removed. Thereby, while having the texture structure 14 in the whole light-receiving surface, the silicon substrate 12 which has the unevenness | corrugation 22 in a part of back surface is obtained.

  Subsequently, as shown in FIG. 2B, an n-type diffusion region 18 and a p-type diffusion region 20 are formed on the back surface side of the silicon substrate 12.

  For example, the n-type diffusion region 18 is formed by thermally diffusing an n-type impurity (for example, phosphorus) from the back surface of the silicon substrate 12. The n-type impurity diffusion source is, for example, PSG (Phosphorus Silicate Glass).

  The p-type diffusion region 20 is formed, for example, by thermally diffusing p-type impurities (for example, boron) from the back surface of the silicon substrate 12. The p-type impurity diffusion source is, for example, BSG (Boron Silicate Glass).

  Subsequently, as shown in FIG. 2C, a passivation film 16 is formed on the light receiving surface of the silicon substrate 12. The passivation film 16 is formed by, for example, plasma CVD.

  Subsequently, as shown in FIG. 2D, electrodes 24n and 24p are formed. Thereby, the target photoelectric conversion element 10 is obtained.

  The formation method of the electrodes 24n and 24p is, for example, as follows. First, the electrode paste is printed on the n-type diffusion region 18 and the p-type diffusion region 20. The electrode paste is printed by, for example, a screen printing method. The electrode paste is, for example, a silver paste. Subsequently, the silicon substrate 12 is heat-treated in a heating furnace or the like. Thereby, an electrode paste is baked. As a result, electrodes 24n and 24p are formed.

  In such a photoelectric conversion element 10, irregularities 22 are formed at the contact interface between the electrode 24 n that collects majority carriers and the n-type diffusion region 18. Therefore, the contact area between the electrode 24n and the n-type diffusion region 18 increases. As a result, even if the width dimension of the n-type diffusion region 18 is smaller than the width dimension of the p-type diffusion region 20 in the in-plane direction of the silicon substrate 12, the contact resistance between the electrode 24n and the n-type diffusion region 18 increases. It can be suppressed.

[Application 1 of the first embodiment]
In the example shown in FIG. 1, the depth dimension of the n-type diffusion region 18 is substantially the same throughout the n-type diffusion region 18, but differs, for example, in the n-type diffusion region 181 as shown in FIG. 3. It may be. In the silicon substrate 121 shown in FIG. 3, the depth dimension of the n-type diffusion region 181 is maximum at the tip of the convex portion and minimum at the bottom of the concave portion. In this case, it is necessary to form the irregularities 22 on the surface of the n-type diffusion region 181 after forming the n-type diffusion region 181. The irregularities 22 can be formed by dry etching such as reactive ion etching, for example. When the irregularities 22 are formed by reactive ion etching, the reactive gas is, for example, CF ₄ or SF ₆ . The pressure in the chamber is 1 Pa, for example. The power for generating plasma is, for example, 100 W to 1 kW. As a method of forming the irregularities 22 in addition to dry etching, for example, there is laser irradiation. When the irregularities 22 are formed by laser irradiation, the laser is, for example, a YAG laser. In the case of a YAG laser, the energy density is, for example, 100 to 600 mJ / cm ² , and the pulse oscillation frequency is, for example, 30 to 200 kHz. Before forming the irregularities 22, the depth dimension of the n-type diffusion region 181 may be, for example, 0.1 to 3 μm.

[Application 2 of the first embodiment]
The unevenness need not be formed in the entire n-type diffusion region 18. For example, only one recess 26 may be formed in the n-type diffusion region 182 as in the silicon substrate 122 shown in FIG. In this case, the electrode 24n is formed at the position where the recess 26 is formed. This increases the contact area between the electrode 24n and the n-type diffusion region 182. As a result, even if the width dimension of the n-type diffusion region 182 is smaller than the width dimension of the p-type diffusion region 20 in the in-plane direction of the silicon substrate 122, the contact resistance between the electrode 24n and the n-type diffusion region 182 increases. Can be suppressed. The recess 26 can be formed by dry etching such as reactive ion etching, for example. In the example shown in FIG. 4, the bottom surface of the recess 26 is flat, but it is of course possible to provide unevenness on the bottom surface of the recess 26.

[Application 3 of the first embodiment]
For example, irregularities may be formed on the surface of the p-type diffusion region 20. That is, irregularities may be formed at the contact interface between the p-type diffusion region 20 and the electrode 24p. In this case, the contact resistance between the p-type diffusion region 20 and the electrode 24p can be lowered.

[Second Embodiment]
A photoelectric conversion element 30 according to the second embodiment of the present invention will be described with reference to FIG. The photoelectric conversion element 30 of this embodiment includes a silicon substrate 13 instead of the silicon substrate 12. The silicon substrate 13 is the same as the silicon substrate 12 except that the n-type diffusion region 18 and the p-type diffusion region 20 are not provided. On the back surface of the silicon substrate 13, intrinsic amorphous silicon layers (intrinsic amorphous semiconductor layers) 32 and 33 are formed. On the intrinsic amorphous silicon layer 32, an n-type amorphous silicon layer (first amorphous semiconductor layer) 34 is formed. A p-type amorphous silicon layer (second amorphous semiconductor layer) 36 is formed on the intrinsic amorphous silicon layer 33.

  The intrinsic amorphous silicon layers 32 and 33 are made of, for example, i-type amorphous silicon (a-Si). The intrinsic amorphous silicon layer 32 is formed on a part of the back surface of the silicon substrate 13, and the intrinsic amorphous silicon layer 33 is adjacent to the formation region of the intrinsic amorphous silicon layer 32 on the back surface of the silicon substrate 13. Is formed. That is, the intrinsic amorphous silicon layers 32 and 33 are formed on the entire back surface of the silicon substrate 12. The thickness of the intrinsic amorphous silicon layers 32 and 33 is, for example, 10 nm.

  The n-type amorphous silicon layer 34 is made of amorphous silicon containing an n-type impurity (for example, phosphorus), for example, n-type a-Si. The thickness of the n-type amorphous silicon layer 34 is, for example, 10 nm.

  Here, in the silicon substrate 12, irregularities 22 are formed at positions where the n-type amorphous silicon layer 34 is formed. Therefore, irregularities 38 corresponding to the irregularities 22 formed on the back surface of the silicon substrate 13 are formed on the surface of the intrinsic amorphous silicon layer 32. Further, unevenness 40 corresponding to the unevenness 22 formed on the back surface of the silicon substrate 12 is formed on the surface of the n-type amorphous silicon layer 34. The surface of the electrode 24n that contacts the n-type amorphous silicon layer 34 has a shape corresponding to the irregularities 40.

  The p-type amorphous silicon layer 36 is made of amorphous silicon containing a p-type impurity (for example, boron), for example, p-type a-Si. The thickness of the p-type amorphous silicon layer 36 is, for example, 10 nm.

[Production Method of Photoelectric Conversion Element]
A method for manufacturing the photoelectric conversion element 30 will be described with reference to FIGS. 6A to 6F.

  First, as shown in FIG. 6A, a silicon substrate 13 having a texture structure 14 on the entire light receiving surface and having irregularities 22 on a part of the back surface is prepared. The method for forming the texture structure 14 and the unevenness 22 is, for example, the method described in the first embodiment.

  Subsequently, as shown in FIG. 6B, intrinsic amorphous silicon layers 32 and 33 are formed on the back surface of the silicon substrate 13. As a result, the unevenness 38 corresponding to the unevenness 22 formed on the back surface of the silicon substrate 13 is formed in the intrinsic amorphous silicon layer 32.

The intrinsic amorphous silicon layers 32 and 33 can be formed by plasma CVD, for example. When forming by plasma CVD, the reaction gas introduced into the reaction chamber with which a plasma CVD apparatus is provided is silane gas and hydrogen gas. The flow rate of silane gas is, for example, 10 sccm. The flow rate of hydrogen gas is, for example, 100 sccm. The temperature of the silicon substrate 12 is 200 ° C., for example. The pressure in the reaction chamber is, for example, 13.5 to 665 Pa. The output of the RF power source provided in the plasma CVD apparatus is, for example, 16 to 80 mW / cm ² .

  Subsequently, as shown in FIG. 6C, a p-type amorphous silicon layer 36 is formed on the intrinsic amorphous silicon layer 33. Specifically, first, a resist pattern as a mask is formed on the intrinsic amorphous silicon layer 32. This resist pattern can be obtained, for example, by patterning a resist formed on the intrinsic amorphous silicon layers 32 and 33. The patterning is performed by, for example, photolithography and etching.

Subsequently, a p-type amorphous silicon layer is formed on the resist pattern formed on the intrinsic amorphous silicon layer 33 and the intrinsic amorphous silicon layer 32. The p-type amorphous silicon layer can be formed by plasma CVD, for example. When forming by plasma CVD, the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is silane gas, hydrogen gas, and diborane gas diluted with hydrogen. The flow rate of the silane gas is 2 sccm, for example. The flow rate of hydrogen gas is, for example, 42 sccm. The flow rate of diborane gas diluted with hydrogen is, for example, 12 sccm. The concentration of diborane gas diluted with hydrogen is, for example, 0.1%. The temperature of the silicon substrate 13 is 200 ° C., for example. The pressure in the reaction chamber is, for example, 13.5 to 665 Pa. The output of the RF power source provided in the plasma CVD apparatus is, for example, 16 to 80 mW / cm ² .

  Subsequently, the resist pattern formed on the intrinsic amorphous silicon layer 32 is removed. As a result, a p-type amorphous silicon layer 36 is formed on the intrinsic amorphous silicon layer 33. A method for removing the resist pattern formed on the intrinsic amorphous silicon layer 32 is, for example, wet etching.

  Subsequently, as shown in FIG. 6D, an n-type amorphous silicon layer 34 is formed on the intrinsic amorphous silicon layer 32. Specifically, first, a resist pattern as a mask is formed on the p-type amorphous silicon layer 36. This resist pattern can be obtained by patterning a resist pattern formed on the intrinsic amorphous silicon layer 32 and the p-type amorphous silicon layer 36, for example. The patterning is performed by, for example, photolithography and etching.

Subsequently, an n-type amorphous silicon layer is formed on the resist pattern formed on the intrinsic amorphous silicon layer 32 and the p-type amorphous silicon layer 36. In the n-type amorphous silicon layer, the unevenness 40 corresponding to the unevenness 38 is formed in a region on the unevenness 38. The n-type amorphous silicon layer can be formed by plasma CVD, for example. When forming by plasma CVD, the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is silane gas, hydrogen gas, and phosphine gas diluted with hydrogen. The flow rate of the silane gas is, for example, 20 sccm. The flow rate of hydrogen gas is, for example, 150 sccm. The flow rate of the phosphine gas diluted with hydrogen is, for example, 50 sccm. The concentration of the phosphine gas diluted with hydrogen is, for example, 0.2%. The temperature of the silicon substrate 13 is 200 ° C., for example. The pressure in the reaction chamber is, for example, 13.5 to 665 Pa. The output of the RF power source provided in the plasma CVD apparatus is, for example, 16 to 80 mW / cm ² .

  Subsequently, the resist pattern formed on the p-type amorphous silicon layer 36 is removed. As a result, the p-type amorphous silicon layer 36 is formed on the intrinsic amorphous silicon layer 33, and the n-type amorphous silicon layer 34 is formed on the intrinsic amorphous silicon layer 32. A method for removing the resist pattern formed on the p-type amorphous silicon layer 36 is, for example, wet etching.

  Subsequently, as shown in FIG. 6E, a passivation film 16 is formed on the light receiving surface of the silicon substrate 12. The passivation film 16 is formed by, for example, plasma CVD.

  Subsequently, as shown in FIG. 6F, electrodes 24n and 24p are formed. Thereby, the target photoelectric conversion element 30 is obtained. The method for forming the electrodes 24n and 24p is, for example, the method described in the first embodiment.

  In such a photoelectric conversion element 30, irregularities 40 are formed at the contact interface between the electrode 24 n that collects majority carriers and the n-type amorphous silicon layer 34. Therefore, the contact area between the electrode 24n and the n-type amorphous silicon layer 34 increases. As a result, even if the width dimension of the n-type amorphous silicon layer 34 is smaller than the width dimension of the p-type amorphous silicon layer 36 in the in-plane direction of the silicon substrate 13, the electrode 24 n and the n-type amorphous silicon layer 34. It is possible to suppress an increase in contact resistance.

  The surface of the n-type amorphous silicon layer 34 on the electrode 24 n side has a shape corresponding to the irregularities 22 formed on the silicon substrate 13. Therefore, the irregularities 40 can be formed when the n-type amorphous silicon layer 34 is formed.

[Application 1 of the second embodiment]
In the example shown in FIG. 5, the thickness of the n-type amorphous silicon layer 34 is substantially the same for the entire n-type amorphous silicon layer 34. For example, as shown in FIG. It may be different in the crystalline silicon layer 341. In the silicon substrate 131 shown in FIG. 7, the irregularities 22 are not formed. Instead, irregularities 401 are formed in the n-type amorphous silicon layer 341. In the region where the projections and depressions 401 are formed, the film thickness of the n-type amorphous silicon layer 341 is maximum at the tip of the projection and is minimum at the bottom of the recess. In this case, after the n-type amorphous silicon layer 341 is formed, the unevenness 401 needs to be formed on the surface of the n-type amorphous silicon layer 341. The unevenness 401 can be formed by dry etching such as reactive ion etching, for example. When the unevenness 401 is formed by reactive ion etching, the reactive gas is, for example, CF ₄ or SF ₆ . The pressure in the chamber is 1 Pa, for example. The power for generating plasma is, for example, 100 W to 1 kW. Before forming the unevenness 401, the depth dimension of the n-type amorphous silicon layer 341 may be, for example, 5 to 10 nm.

[Application Example 2 of Second Embodiment]
The unevenness does not need to be formed on the entire n-type amorphous silicon layer 34. For example, a single recess 42 may be formed in the n-type amorphous silicon layer 342 as in the silicon substrate 132 shown in FIG. In this case, the electrode 24n is formed at the position where the recess 42 is formed. This increases the contact area between the electrode 24n and the n-type amorphous silicon layer 342. As a result, even if the width dimension of the n-type amorphous silicon layer 342 is smaller than the width dimension of the p-type amorphous silicon layer 36 in the in-plane direction of the silicon substrate 13, the electrode 24n and the n-type amorphous silicon layer 342 are formed. It is possible to suppress an increase in contact resistance. The recess 42 can be formed by dry etching such as reactive ion etching, for example. In the example shown in FIG. 8, the bottom surface of the recess 42 is flat, but it is of course possible to provide unevenness on the bottom surface of the recess 42.

[Application 3 of the second embodiment]
For example, irregularities may be formed on the surface of the p-type amorphous silicon layer 36. That is, irregularities may be formed at the contact interface between the p-type amorphous silicon layer 36 and the electrode 24p. In this case, the contact resistance between the p-type amorphous silicon layer 36 and the electrode 24p can be lowered.

  As mentioned above, although embodiment of this invention has been explained in full detail, these are illustrations to the last and this invention is not limited at all by the above-mentioned embodiment.

  For example, in the first embodiment, the silicon substrate 12 may be a p-type single crystal silicon substrate. In this case, the width dimension of the p-type diffusion region 20 is smaller than the width dimension of the n-type diffusion region 18 in the in-plane direction of the silicon substrate 12, and the contact interface between the electrode 24p and the p-type diffusion region 20 is uneven. It is formed. The same applies to the application examples 1 and 2 of the first embodiment.

  In the second embodiment, the silicon substrate 13 may be a p-type single crystal silicon substrate. In this case, the width dimension of the p-type amorphous silicon layer 36 is smaller than the width dimension of the n-type amorphous silicon layer 34 in the in-plane direction of the silicon substrate 13, and the electrode 24p and the p-type amorphous silicon layer Unevenness is formed at the contact interface with the layer 36. The same applies to the application examples 1 and 2 of the second embodiment.

  In the second embodiment, the intrinsic amorphous silicon layers 32 and 33 are not essential components. That is, the n-type amorphous silicon layer 34 and the p-type amorphous silicon layer 36 may be directly formed on the back surface of the silicon substrate 13. The same applies to the application examples 1 and 2 of the second embodiment.

  In the first and second embodiments, the texture structure 14 and the passivation 16 are not essential components. The same applies to the application examples of these embodiments.

  In the first and second embodiments, a high concentration region may be formed on the light receiving surface side of the silicon substrates 12 and 13. The high concentration region is a region in which impurities having the same conductivity type as the silicon substrates 12 and 13 are doped at a higher concentration than the silicon substrates 12 and 13. The high density region functions as an FSF (Front Surface Field). The same applies to the application examples of the first and second embodiments.

  In the first and second embodiments, the texture structure 14 on the light receiving surface side of the silicon substrates 12 and 13 and the unevenness 22 on the back surface side of the silicon substrates 12 and 13 do not need to be formed simultaneously. The same applies to the application examples of these embodiments.

  In the first embodiment, the n-type diffusion region 18 and the p-type diffusion region 20 are formed on the back surface side of the silicon substrate 12 and in the silicon substrate 12, and the n-type diffusion region 18 and the electrode are formed. Concavities and convexities 22 are formed on the contact interface with 24n. In the second embodiment, an n-type amorphous silicon layer 34 and a p-type amorphous silicon layer 36 are formed on the back surface of the silicon substrate 13, and the n-type amorphous silicon layer 34 and the electrode 24n are formed. Concavities and convexities 40 are formed between the two. That is, in the present invention, the first semiconductor layer having the same conductivity type as the silicon substrate and the second semiconductor layer having the conductivity type opposite to the silicon substrate are formed on the back surface side of the silicon substrate, and the first semiconductor Irregularities may be formed between the layer and the first electrode formed on the first semiconductor layer.

10: photoelectric conversion element, 12: silicon substrate, 18: n-type diffusion region, 20: p-type diffusion region, 22: unevenness, 24n: electrode, 24p: electrode, 30: photoelectric conversion device, 32: intrinsic amorphous silicon Layer 33: intrinsic amorphous silicon layer 34: p-type amorphous silicon layer 36: n-type amorphous silicon layer 40: irregularities

Claims (4)

A silicon substrate having a first conductivity type;
A first semiconductor layer having the first conductivity type and formed on the back side of the silicon substrate;
The second conductivity type opposite to the first conductivity type is formed adjacent to the first semiconductor layer in the in-plane direction of the silicon substrate, and the surface of the silicon substrate is more than the first semiconductor layer. A second semiconductor layer having a large width dimension in the inward direction;
A first electrode formed on the first semiconductor layer;
A second electrode formed on the second semiconductor layer,
A photoelectric conversion element, wherein irregularities are formed at a contact interface between the first electrode and the first semiconductor layer. The photoelectric conversion device according to claim 1,
The first semiconductor layer is a first diffusion region formed on the back side of the silicon substrate and in which the impurity of the first conductivity type is diffused;
The photoelectric conversion element, wherein the second semiconductor layer is a second diffusion region formed on a back surface side of the silicon substrate and in which the second conductivity type impurity is diffused. The photoelectric conversion device according to claim 1,
An intrinsic amorphous semiconductor layer formed on the back surface of the silicon substrate and made of an intrinsic amorphous semiconductor;
The first semiconductor layer is a first amorphous semiconductor layer formed on the intrinsic amorphous semiconductor layer and made of an amorphous semiconductor containing an impurity of the first conductivity type;
The photoelectric conversion element, wherein the second semiconductor layer is a second amorphous semiconductor layer formed on the intrinsic amorphous semiconductor layer and made of an amorphous semiconductor containing the second conductivity type impurity. It is a photoelectric conversion element given in any 1 paragraph of Claims 1-3,
The photoelectric conversion element in which the surface of the first electrode side of the first semiconductor layer has a shape corresponding to the unevenness of the substrate.

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