JP2005101240A - Photosensor and its manufacturing method - Google Patents

Photosensor and its manufacturing method Download PDF

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JP2005101240A
JP2005101240A JP2003332549A JP2003332549A JP2005101240A JP 2005101240 A JP2005101240 A JP 2005101240A JP 2003332549 A JP2003332549 A JP 2003332549A JP 2003332549 A JP2003332549 A JP 2003332549A JP 2005101240 A JP2005101240 A JP 2005101240A
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amorphous silicon
silicon film
type amorphous
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film
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JP4155899B2 (en
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Akira Terakawa
朗 寺川
Toshio Asaumi
利夫 浅海
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Sanyo Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a photosensor maximally utilizing an incident light and its manufacturing method for the photosensor. <P>SOLUTION: An i-type amorphous silicon film 2 and an antireflection film 3 composed of an amorphous silicon nitride or the like are formed successively on the main surface of an n-type single-crystal silicon substrate 1. A positive electrode 100 and a negative electrode 200 are mounted adjacently on the rear of the n-type silicon substrate 1. The positive electrode 100 has the i-type amorphous silicon film 5, a p-type amorphous silicon film 7, a rear electrode 9, and a collecting electrode 11 successively formed on the rear of the n-type silicon substrate 1. The negative electrode 200 has the i-type amorphous silicon film 4, an n-type amorphous silicon film 6, the rear electrode 8, and the collecting electrode 10 successively formed on the rear of the n-type silicon substrate 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体接合を用いた光起電力素子およびその製造方法に関する。   The present invention relates to a photovoltaic device using a semiconductor junction and a method for manufacturing the photovoltaic device.

近年、ｎ型単結晶シリコン基板とｐ型非晶質シリコン膜との接合を有する光起電力素子が開発されている。このような光起電力素子において、光電変換効率を向上させるためには、高い短絡電流Ｉｓｃおよび開放電圧Ｖｏｃを維持しつつ曲線因子Ｆ．Ｆ．を向上させる必要がある。   In recent years, photovoltaic devices having a junction between an n-type single crystal silicon substrate and a p-type amorphous silicon film have been developed. In such a photovoltaic device, in order to improve the photoelectric conversion efficiency, the fill factor F.V. is maintained while maintaining a high short circuit current Isc and an open circuit voltage Voc. F. It is necessary to improve.

しかしながら、ｎ型単結晶シリコン基板とｐ型非晶質シリコン膜との接合部においては、界面準位が多数存在するため、キャリアの再結合が発生し、開放電圧Ｖｏｃが低下する。   However, since there are many interface states at the junction between the n-type single crystal silicon substrate and the p-type amorphous silicon film, carrier recombination occurs and the open circuit voltage Voc decreases.

そこで、ｎ型単結晶シリコン基板とｐ型非晶質シリコン膜との接合部におけるキャリア再結合を抑制するために、ｎ型単結晶シリコン基板とｐ型非晶質シリコン膜との間に実質的に真性な非晶質シリコン膜（ｉ型非晶質シリコン膜）が挿入されたＨＩＴ（真性薄膜を有するヘテロ接合：Heterojunction with Intrinsic Thin-Layer）構造を有する光起電力素子が提案されている（例えば、特許文献１参照）。   Therefore, in order to suppress carrier recombination at the junction between the n-type single crystal silicon substrate and the p-type amorphous silicon film, a substantial gap is formed between the n-type single crystal silicon substrate and the p-type amorphous silicon film. A photovoltaic device having a HIT (Heterojunction with Intrinsic Thin-Layer) structure in which an intrinsic amorphous silicon film (i-type amorphous silicon film) is inserted is proposed ( For example, see Patent Document 1).

この光起電力素子は、ｎ型単結晶シリコン基板の主面側から受光し、ｎ型単結晶シリコン基板内で発電する。このときに発生する電力は、主面側および裏面側に設けられた電極により外部に取り出すことができる。
特開平１１−２２４９５４号公報 This photovoltaic element receives light from the main surface side of the n-type single crystal silicon substrate and generates power in the n-type single crystal silicon substrate. The electric power generated at this time can be taken out by the electrodes provided on the main surface side and the back surface side.
JP-A-11-224954

しかしながら、上記光起電力素子では、主面側の電極およびｐ型非晶質シリコン膜による光吸収により、ｎ型単結晶シリコン基板に入射するフォトン数が減少し、発電効率を制限することになる。   However, in the above photovoltaic element, the number of photons incident on the n-type single crystal silicon substrate is reduced due to light absorption by the electrode on the main surface side and the p-type amorphous silicon film, thereby limiting the power generation efficiency. .

本発明の目的は、入射光を最大限に活用できる光起電力素子およびその製造方法を提供することである。   An object of the present invention is to provide a photovoltaic device that can make the best use of incident light and a method for manufacturing the photovoltaic device.

本明細書中における結晶系半導体には単結晶半導体および多結晶半導体が含まれるものとし、非晶質系半導体には非晶質半導体および微結晶半導体が含まれるものとする。   In this specification, a crystalline semiconductor includes a single crystal semiconductor and a polycrystalline semiconductor, and an amorphous semiconductor includes an amorphous semiconductor and a microcrystalline semiconductor.

また、真性の非晶質系半導体膜とは、不純物が意図的にドープされていない非晶質系半導体膜であり、半導体原料に本来的に含まれる不純物または製造過程において自然に混入する不純物を含む非晶質系半導体膜も含む。   An intrinsic amorphous semiconductor film is an amorphous semiconductor film that is not intentionally doped with impurities, and contains impurities inherently contained in semiconductor raw materials or impurities that are naturally mixed in the manufacturing process. An amorphous semiconductor film is also included.

本発明に係る光起電力素子は、一面および他面を有する結晶系半導体を備え、結晶系半導体の一面の第１の領域に、真性の第１の非晶質系半導体膜と、一導電型を示す不純物を含む第２の非晶質系半導体膜と、第１の電極とを順に備え、結晶系半導体の一面の第２の領域に、一導電型と異なる他導電型を示す不純物を含む半導体層と、第２の電極とを順に備えるものである。   A photovoltaic device according to the present invention includes a crystalline semiconductor having one surface and another surface, and an intrinsic first amorphous semiconductor film and a one conductivity type in a first region on one surface of the crystalline semiconductor. A second amorphous semiconductor film containing an impurity indicating impurity and a first electrode in order, and the second region on one surface of the crystalline semiconductor includes an impurity having another conductivity type different from the one conductivity type A semiconductor layer and a second electrode are sequentially provided.

本発明に係る光起電力素子においては、結晶系半導体が他面側から受光すると正孔および電子が発生し、発生した正孔は第１の非晶質系半導体膜、第２の非晶質系半導体膜および第１の電極を経由する経路と半導体層および第２の電極を経由する経路とのいずれか一方の経路を通って外部へ取り出され、発生した電子は正孔とは逆の経路を通って外部へ取り出される。   In the photovoltaic device according to the present invention, when the crystalline semiconductor receives light from the other surface side, holes and electrons are generated, and the generated holes are the first amorphous semiconductor film and the second amorphous semiconductor film. The path through the semiconductor film and the first electrode and the path through the semiconductor layer and the second electrode are taken out through one of the paths, and the generated electrons are paths opposite to the holes. It is taken out through.

この場合、第１の電極および第２の電極が一面側に形成されているので、入射光が劣化しない。それにより、結晶系半導体の他面から受光することにより、入射光を最大限に活用することができる。   In this case, since the first electrode and the second electrode are formed on one surface side, incident light does not deteriorate. Accordingly, incident light can be utilized to the maximum by receiving light from the other surface of the crystalline semiconductor.

結晶系半導体は、一導電型を示す不純物を含んでもよい。この場合、結晶系半導体と半導体層との間にｐｎ接合が形成され、キャリアの取り出しが効率良く行われる。   The crystalline semiconductor may include an impurity having one conductivity type. In this case, a pn junction is formed between the crystalline semiconductor and the semiconductor layer, and carriers are efficiently extracted.

半導体層は、他導電型を示す不純物を含む第３の非晶質系半導体膜であり、結晶系半導体と第３の非晶質系半導体膜との間に真性の第４の非晶質系半導体膜をさらに備えてもよい。この場合、結晶系半導体と第３の非晶質系半導体膜との間のキャリアの再結合が防止され、発電効率が向上する。   The semiconductor layer is a third amorphous semiconductor film containing an impurity having another conductivity type, and an intrinsic fourth amorphous system is provided between the crystalline semiconductor and the third amorphous semiconductor film. A semiconductor film may be further provided. In this case, carrier recombination between the crystalline semiconductor and the third amorphous semiconductor film is prevented, and power generation efficiency is improved.

結晶系半導体の第１の領域の第１の非晶質系半導体膜と第２の領域の第４の非晶質系半導体膜とが連続する共通の非晶質系半導体膜であってもよい。この場合、結晶系半導体の一面側が真性の非晶質系半導体膜で覆われる。それにより、結晶系半導体の一面側の露出部がなくなり、結晶系半導体の一面側におけるキャリアの再結合が防止され、発電効率が向上する。   A common amorphous semiconductor film in which the first amorphous semiconductor film in the first region of the crystalline semiconductor and the fourth amorphous semiconductor film in the second region are continuous may be used. . In this case, one surface side of the crystalline semiconductor is covered with an intrinsic amorphous semiconductor film. This eliminates the exposed portion on the one surface side of the crystalline semiconductor, prevents recombination of carriers on the one surface side of the crystalline semiconductor, and improves power generation efficiency.

第１の領域と第２の領域とが間隔をおいて設けられ、第１の領域と第２の領域との間における結晶系半導体の表面に保護層を備えてもよい。この場合、結晶系半導体の一面側において第１の領域と第２の領域との間隔の露出部が保護層で覆われる。それにより、結晶系半導体の一面側の露出部がなくなり、結晶系半導体の一面側におけるキャリアの再結合が防止され、発電効率が向上する。   The first region and the second region may be provided at an interval, and a protective layer may be provided on the surface of the crystalline semiconductor between the first region and the second region. In this case, the exposed portion at the interval between the first region and the second region is covered with the protective layer on the one surface side of the crystalline semiconductor. This eliminates the exposed portion on the one surface side of the crystalline semiconductor, prevents recombination of carriers on the one surface side of the crystalline semiconductor, and improves power generation efficiency.

半導体層は、結晶系半導体の第２の領域に他導電型を示す不純物がドープされたドープ層であってもよい。この場合、ドープ層により結晶系半導体と第２の非晶質系半導体との電気的接触が得られる。   The semiconductor layer may be a doped layer in which the second region of the crystalline semiconductor is doped with an impurity having another conductivity type. In this case, electrical contact between the crystalline semiconductor and the second amorphous semiconductor is obtained by the doped layer.

他面の実質的に全面が光入射面であってもよい。この場合、他面から十分に光が入射するため、入射光を最大限に活用することができる。   The substantially entire other surface may be a light incident surface. In this case, since the light is sufficiently incident from the other surface, the incident light can be utilized to the maximum extent.

本発明に係る光起電力素子の製造方法は、結晶系半導体の一面の第１の領域に真性の第１の非晶質系半導体膜を形成する工程と、第１の非晶質系半導体膜上に一導電型を示す不純物を含む第２の非晶質系半導体膜を形成する工程と、結晶系半導体の一面の第２の領域に一導電型と異なる他導電型を示す不純物を含む半導体層を形成する工程と、第２の非晶質系半導体膜上に第１の電極を形成する工程と、半導体層上に第２の電極を形成する工程とを備えるものである。   The method for manufacturing a photovoltaic device according to the present invention includes a step of forming an intrinsic first amorphous semiconductor film in a first region on one surface of a crystalline semiconductor, and a first amorphous semiconductor film A step of forming a second amorphous semiconductor film containing an impurity of one conductivity type thereon, and a semiconductor containing an impurity of another conductivity type different from the one conductivity type in a second region of one surface of the crystalline semiconductor A step of forming a layer, a step of forming a first electrode on the second amorphous semiconductor film, and a step of forming a second electrode on the semiconductor layer.

本発明に係る光起電力素子の製造方法においては、結晶系半導体の一面の第１の領域に第１の非晶質系半導体膜、第２の非晶質系半導体膜および第１の電極が形成され、結晶系半導体の一面の第２の領域に半導体層および第２の電極が形成される。   In the method for manufacturing a photovoltaic device according to the present invention, the first amorphous semiconductor film, the second amorphous semiconductor film, and the first electrode are formed in the first region of one surface of the crystalline semiconductor. The semiconductor layer and the second electrode are formed in the second region of the one surface of the crystalline semiconductor.

この場合、結晶系半導体が他面側から受光すると、正孔および電子が発生し、発生した正孔は第１の非晶質系半導体膜、第２の非晶質計半導体膜および第１の電極を経由する経路と半導体層および第２の電極を経由する経路とのいずれか一方の経路を通って外部へ取り出され、発生した電子は正孔とは逆の経路を通って外部へ取り出される。この場合、第１の電極および第２の電極が結晶系半導体の一面側に設けられているので、結晶系半導体の他面側から入射した光の反射損失および吸収損失を抑制できる。したがって、結晶系半導体の他面から受光することにより、入射光を最大限に活用することができる。   In this case, when the crystalline semiconductor receives light from the other surface side, holes and electrons are generated, and the generated holes are generated by the first amorphous semiconductor film, the second amorphous meter semiconductor film, and the first amorphous semiconductor film. The electron is taken out through one of the path through the electrode and the path through the semiconductor layer and the second electrode, and the generated electrons are taken out through the path opposite to the hole. . In this case, since the first electrode and the second electrode are provided on the one surface side of the crystalline semiconductor, reflection loss and absorption loss of light incident from the other surface side of the crystalline semiconductor can be suppressed. Therefore, incident light can be utilized to the maximum by receiving light from the other surface of the crystalline semiconductor.

本発明に係る光起電力素子によれば、結晶系半導体の他面から受光することにより、入射光を最大限に活用することができる。   According to the photovoltaic device of the present invention, incident light can be utilized to the maximum by receiving light from the other surface of the crystalline semiconductor.

（第１の実施の形態）
以下、本発明の一実施の形態について説明する。 (First embodiment)
Hereinafter, an embodiment of the present invention will be described.

図１（ａ）は本実施の形態に係る光起電力素子５００の裏面を示す平面図であり、図１（ｂ）は図１（ａ）の一部拡大図である。   Fig.1 (a) is a top view which shows the back surface of the photovoltaic element 500 based on this Embodiment, FIG.1 (b) is a partially expanded view of Fig.1 (a).

図１（ａ）に示すように、光起電力素子５００は、長方形状を有する。例えば、短辺の長さが５ｃｍであり、長辺の長さが１０ｃｍである。光起電力素子５００の裏面は、くし形の正極１００およびくし形の負極２００から構成される。正極１００および負極２００は、光起電力素子５００の短辺方向に延び、交互に並んでいる。また、光起電力素子５００の裏面の両長辺に沿ってそれぞれ電極３００，４００が設けられている。   As shown in FIG. 1A, the photovoltaic element 500 has a rectangular shape. For example, the length of the short side is 5 cm and the length of the long side is 10 cm. The back surface of the photovoltaic element 500 includes a comb-shaped positive electrode 100 and a comb-shaped negative electrode 200. The positive electrode 100 and the negative electrode 200 extend in the short side direction of the photovoltaic element 500 and are alternately arranged. Electrodes 300 and 400 are provided along both long sides of the back surface of the photovoltaic element 500.

図１（ｂ）に示すように、正極１００および負極２００には集電極１１，１０がそれぞれ設けられている。集電極１０は電極３００に接続されており、集電極１１は電極４００に接続されている。   As shown in FIG. 1B, collector electrodes 11 and 10 are provided on the positive electrode 100 and the negative electrode 200, respectively. The collector electrode 10 is connected to the electrode 300, and the collector electrode 11 is connected to the electrode 400.

図２は、本実施の形態に係る光起電力素子５００の構造を示す模式的断面図である。   FIG. 2 is a schematic cross-sectional view showing the structure of the photovoltaic device 500 according to the present embodiment.

図２に示すように、ｎ型単結晶シリコン基板１の主面（表側の面）上にｉ型非晶質シリコン膜２（ノンドープ非晶質シリコン膜）および非晶質窒化シリコン等からなる反射防止膜３が順に形成されている。ｎ型単結晶シリコン基板１の主面側が光入射面となる。ｎ型単結晶シリコン基板１の裏面には、正極１００および負極２００が隣接するように設けられている。   As shown in FIG. 2, a reflection made of an i-type amorphous silicon film 2 (non-doped amorphous silicon film), amorphous silicon nitride or the like on the main surface (front surface) of an n-type single crystal silicon substrate 1. The prevention film 3 is formed in order. The main surface side of the n-type single crystal silicon substrate 1 is a light incident surface. A positive electrode 100 and a negative electrode 200 are provided adjacent to the back surface of the n-type single crystal silicon substrate 1.

正極１００は、ｎ型単結晶シリコン基板１の裏面上に順に形成された側ｉ型非晶質シリコン膜５、ｐ型非晶質シリコン膜７、裏面電極９および集電極１１を含む。負極２００は、ｎ型単結晶シリコン基板１の裏面上に順に形成されたｉ型非晶質シリコン膜４、ｎ型非晶質シリコン膜６、裏面電極８および集電極１０を含む。図２の光起電力素子５００では、ｎ型単結晶シリコン基板１が主たる発電層となる。   The positive electrode 100 includes a side i-type amorphous silicon film 5, a p-type amorphous silicon film 7, a back electrode 9, and a collector electrode 11 that are sequentially formed on the back surface of the n-type single crystal silicon substrate 1. The negative electrode 200 includes an i-type amorphous silicon film 4, an n-type amorphous silicon film 6, a back electrode 8, and a collector electrode 10 that are sequentially formed on the back surface of the n-type single crystal silicon substrate 1. In the photovoltaic element 500 of FIG. 2, the n-type single crystal silicon substrate 1 is a main power generation layer.

裏面電極８，９は、ＩＴＯ（酸化インジウム錫）、ＳｎＯ2 （酸化錫）、ＺｎＯ（酸化亜鉛）等からなる透明電極である。集電極１０，１１はＡｇ（銀）等からなる。 The back electrodes 8 and 9 are transparent electrodes made of ITO (indium tin oxide), SnO 2 (tin oxide), ZnO (zinc oxide), or the like. The collector electrodes 10 and 11 are made of Ag (silver) or the like.

ｉ型非晶質シリコン膜２の膜厚は例えば１０ｎｍ程度であり、反射防止膜３の膜厚は例えば７０ｎｍ程度であり、ｉ型非晶質シリコン膜４，５の膜厚は例えば１５ｎｍ程度であり、ｎ型非晶質シリコン膜６の膜厚は例えば２０ｎｍ程度であり、ｐ型非晶質シリコン膜７の膜厚は例えば１０ｎｍ程度であり、裏面電極８，９の膜厚は例えば７０ｎｍ程度であり、集電極１０，１１の膜厚は例えば２００ｎｍ程度であるが、それに限られない。   The film thickness of the i-type amorphous silicon film 2 is, for example, about 10 nm, the film thickness of the antireflection film 3 is, for example, about 70 nm, and the film thickness of the i-type amorphous silicon films 4, 5 is, for example, about 15 nm. The thickness of the n-type amorphous silicon film 6 is, for example, about 20 nm, the thickness of the p-type amorphous silicon film 7 is, for example, about 10 nm, and the thickness of the back electrodes 8, 9 is, for example, about 70 nm. The film thickness of the collector electrodes 10 and 11 is, for example, about 200 nm, but is not limited thereto.

なお、ｎ型単結晶シリコン基板１とｐ型非晶質シリコン膜７との間におけるキャリアの走行距離を短くすることにより発電効率が高まることから、ｐ型非晶質シリコン膜７の幅はｎ型非晶質シリコン膜６の幅よりも広い方が好ましい。   Note that since the power generation efficiency is increased by shortening the carrier travel distance between the n-type single crystal silicon substrate 1 and the p-type amorphous silicon film 7, the width of the p-type amorphous silicon film 7 is n. A width wider than the width of the type amorphous silicon film 6 is preferable.

本実施の形態の光起電力素子５００の正極１００は、ｐｎ接合特性を改善するためにｎ型単結晶シリコン基板１とｐ型非晶質シリコン膜７の間にｉ型非晶質シリコン膜５を設けたＨＩＴ構造を有し、負極２００は、キャリア再結合を防止するためにｎ型単結晶シリコン基板１の裏面にｉ型非晶質シリコン膜４およびｎ型非晶質シリコン膜６を設けたＢＳＦ（Back Surface Field）構造を有する。   The positive electrode 100 of the photovoltaic device 500 of the present embodiment has an i-type amorphous silicon film 5 between the n-type single crystal silicon substrate 1 and the p-type amorphous silicon film 7 in order to improve the pn junction characteristics. The negative electrode 200 is provided with an i-type amorphous silicon film 4 and an n-type amorphous silicon film 6 on the back surface of the n-type single crystal silicon substrate 1 in order to prevent carrier recombination. BSF (Back Surface Field) structure.

次に、図２の光起電力素子５００の製造方法を説明する。まず、洗浄したｎ型単結晶シリコン基板１を真空チャンバ内で加熱する。それにより、ｎ型単結晶シリコン基板１の表面に付着した水分が除去される。その後、真空チャンバ内にＨ2 （水素）ガスを導入して、プラズマ放電によりｎ型単結晶シリコン基板１表面のクリーニングを行う。 Next, a method for manufacturing the photovoltaic element 500 of FIG. 2 will be described. First, the cleaned n-type single crystal silicon substrate 1 is heated in a vacuum chamber. Thereby, moisture adhering to the surface of n-type single crystal silicon substrate 1 is removed. Thereafter, H 2 (hydrogen) gas is introduced into the vacuum chamber, and the surface of the n-type single crystal silicon substrate 1 is cleaned by plasma discharge.

次に、真空チャンバ内にＳｉＨ4 （シラン）ガスおよびＨ2 ガスを導入し、プラズマＣＶＤ（化学蒸着）法によりｎ型単結晶シリコン基板１の主面上にｉ型非晶質シリコン膜２を形成する。続いて、真空チャンバ内にＳｉＨ4 ガスおよびＮＨ3 （アンモニア）ガスを導入して、ｉ型非晶質シリコン膜２上にプラズマＣＶＤ法により反射防止膜３を形成する。 Next, SiH 4 (silane) gas and H 2 gas are introduced into the vacuum chamber, and the i-type amorphous silicon film 2 is formed on the main surface of the n-type single crystal silicon substrate 1 by plasma CVD (chemical vapor deposition). Form. Subsequently, SiH 4 gas and NH 3 (ammonia) gas are introduced into the vacuum chamber, and the antireflection film 3 is formed on the i-type amorphous silicon film 2 by plasma CVD.

次に、ｎ型単結晶シリコン基板１の裏面の一部にメタルマスクを被せる。続いて、真空チャンバ内にＳｉＨ4 ガスおよびＨ2 ガスを導入して、プラズマＣＶＤ法によりｎ型単結晶シリコン基板１の裏面のメタルマスクを除く部分にｉ型非晶質シリコン膜５を形成する。続いて、真空チャンバ内にＳｉＨ4 ガス、Ｈ2 ガスおよびＢ2 Ｈ6 ガスを導入して、ｉ型非晶質シリコン膜５上にプラズマＣＶＤ法によりｐ型非晶質シリコン膜７を形成する。 Next, a metal mask is put on a part of the back surface of the n-type single crystal silicon substrate 1. Subsequently, SiH 4 gas and H 2 gas are introduced into the vacuum chamber, and the i-type amorphous silicon film 5 is formed on the back surface of the n-type single crystal silicon substrate 1 except for the metal mask by plasma CVD. . Subsequently, SiH 4 gas, H 2 gas and B 2 H 6 gas are introduced into the vacuum chamber to form a p-type amorphous silicon film 7 on the i-type amorphous silicon film 5 by plasma CVD. .

次いで、ｎ型単結晶シリコン基板１の裏面の一部にｉ型非晶質シリコン膜５およびｐ型非晶質シリコン膜７を覆うようにメタルマスクを被せる。続いて、真空チャンバ内にＳｉＨ4 ガスおよびＨ2 ガスを導入して、プラズマＣＶＤ法によりｎ型単結晶シリコン基板１の裏面のメタルマスクを除く部分にｉ型非晶質シリコン膜４を形成する。続いて、真空チャンバ内にＳｉＨ4 ガス、Ｈ2 ガスおよびＰＨ3 （ホスフィン）ガスを導入して、ｉ型非晶質シリコン膜４上にプラズマＣＶＤ法によりｎ型非晶質シリコン膜６を形成する。 Next, a metal mask is placed on a part of the back surface of the n-type single crystal silicon substrate 1 so as to cover the i-type amorphous silicon film 5 and the p-type amorphous silicon film 7. Subsequently, SiH 4 gas and H 2 gas are introduced into the vacuum chamber, and the i-type amorphous silicon film 4 is formed on the back surface of the n-type single crystal silicon substrate 1 except for the metal mask by plasma CVD. . Subsequently, SiH 4 gas, H 2 gas and PH 3 (phosphine) gas are introduced into the vacuum chamber to form an n-type amorphous silicon film 6 on the i-type amorphous silicon film 4 by plasma CVD. To do.

次いで、スパッタリング法により、ｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７上にそれぞれ裏面電極８，９を形成する。さらに、スクリーン印刷法により、裏面電極８，９上にそれぞれ集電極１０，１１を形成する。   Next, back electrodes 8 and 9 are formed on the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7 by sputtering, respectively. Further, collector electrodes 10 and 11 are formed on the back electrodes 8 and 9, respectively, by screen printing.

本実施の形態の光起電力素子５００においては、入射光の有効利用を妨げる光入射面の導電型シリコン膜、透明電極および集電極が不要になる。それにより、製造工程が短縮化され、コストが低減されるとともに、入射光を最大限に活用できることから出力電圧および曲線因子を最大化できる。   In the photovoltaic device 500 of the present embodiment, the conductive silicon film, the transparent electrode, and the collector electrode on the light incident surface that hinder the effective use of incident light are not necessary. Thereby, the manufacturing process is shortened, the cost is reduced, and the incident light can be utilized to the maximum, so that the output voltage and the fill factor can be maximized.

また、本実施の形態の反射防止膜３には窒化シリコンを用いているが、酸化シリコンを用いてもよい。さらに、本実施の形態の光起電力素子５００においては、主面の界面特性を考慮する必要がないので、反射防止膜３は、光透過性に優れかつ入射光の反射を防止できる材料であればよい。ここで、シリコンの屈折率が約３．４であり、光起電力素子５００を使用する際に光起電力素子５００を覆うＥＶＡ（エチレン−酢酸ビニル樹脂）等の封止材の屈折率が約１．５であることから、屈折率が１．５〜３．４のものであれば反射防止膜３として使用できる。例えば、表１に示す材料が挙げられる。   Further, although silicon nitride is used for the antireflection film 3 of the present embodiment, silicon oxide may be used. Furthermore, in the photovoltaic element 500 of the present embodiment, since it is not necessary to consider the interface characteristics of the main surface, the antireflection film 3 should be a material that has excellent light transmission and can prevent reflection of incident light. That's fine. Here, the refractive index of silicon is about 3.4, and the refractive index of a sealing material such as EVA (ethylene-vinyl acetate resin) that covers the photovoltaic element 500 when the photovoltaic element 500 is used is about Since it is 1.5, if it has a refractive index of 1.5-3.4, it can be used as the antireflection film 3. For example, the material shown in Table 1 is mentioned.

Figure 2005101240
Figure 2005101240

また、本実施の形態のｎ型非晶質シリコン膜６には不純物としてＰ（リン）をドープしたが、それに限られない。例えば、不純物としてＡｓ（ヒ素）等のＶ族元素を不純物としてドープしてもよい。ｐ型非晶質シリコン膜７には不純物としてＢ（ボロン）をドープしたが、それに限られない。例えば、Ａｌ（アルミニウム）、Ｇａ（ガリウム）等のIII 族元素を不純物としてドープしてもよい。また、ｎ型単結晶シリコン基板１の代わりにｎ型多結晶シリコン基板を用いてもよい。さらに、ｉ型非晶質シリコン膜２，４，５、ｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７は微結晶シリコンを含んでもよい。   Further, although the n-type amorphous silicon film 6 of the present embodiment is doped with P (phosphorus) as an impurity, it is not limited thereto. For example, a V group element such as As (arsenic) may be doped as an impurity. The p-type amorphous silicon film 7 is doped with B (boron) as an impurity, but is not limited thereto. For example, a group III element such as Al (aluminum) or Ga (gallium) may be doped as an impurity. Further, an n-type polycrystalline silicon substrate may be used instead of the n-type single crystal silicon substrate 1. Further, the i-type amorphous silicon films 2, 4, 5, the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7 may contain microcrystalline silicon.

また、本実施の形態のｎ型単結晶シリコン基板１、ｉ型非晶質シリコン膜２，４，５、ｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７の代わりに、例えば、ＳｉＣ（炭化シリコン）、ＳｉＧｅ（シリコンゲルマニウム）、Ｇｅ（ゲルマニウム）等のような他のＩＶ族元素を用いてもよい。   Further, instead of the n-type single crystal silicon substrate 1, the i-type amorphous silicon films 2, 4, 5, the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7 of the present embodiment, for example Other group IV elements such as SiC (silicon carbide), SiGe (silicon germanium), Ge (germanium), etc. may be used.

また、本実施の形態の光起電力素子５００においては、ｎ型単結晶シリコン基板１を用いているがそれに限られない。例えば、ｐ型単結晶シリコン基板の主面にｉ型非晶質シリコン膜および窒化シリコン膜を形成し、裏面に本実施の形態に係る光起電力素子５００と同様の正極１００および負極２００を設けてもよい。   Moreover, in the photovoltaic element 500 of this Embodiment, although the n-type single crystal silicon substrate 1 is used, it is not restricted to it. For example, an i-type amorphous silicon film and a silicon nitride film are formed on the main surface of a p-type single crystal silicon substrate, and a positive electrode 100 and a negative electrode 200 similar to those of the photovoltaic element 500 according to the present embodiment are provided on the back surface. May be.

さらに、本発明は、図２に示す光起電力素子５００の構造に限定されず、他の種々の構造を有する光起電力素子に適用することができる。例えば、ｎ型単結晶シリコン基板１の裏面のｉ型非晶質シリコン膜４およびｎ型非晶質シリコン膜６を設けなくてもよい。   Furthermore, the present invention is not limited to the structure of the photovoltaic element 500 shown in FIG. 2, and can be applied to photovoltaic elements having other various structures. For example, the i-type amorphous silicon film 4 and the n-type amorphous silicon film 6 on the back surface of the n-type single crystal silicon substrate 1 may not be provided.

（第２の実施の形態）
以下、本発明の第２の実施の形態について説明する。 (Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described.

図３は、第２の実施の形態に係る光起電力素子５００ａの構造を示す模式的断面図である。図３の光起電力素子５００ａが図１の光起電力素子５００と異なる点は、ｉ型非晶質シリコン膜４およびｎ型非晶質シリコン膜６の代わりに、ｎ型単結晶シリコン基板１中に不純物拡散層１ａを備える点である。   FIG. 3 is a schematic cross-sectional view showing the structure of the photovoltaic element 500a according to the second embodiment. The photovoltaic element 500a in FIG. 3 is different from the photovoltaic element 500 in FIG. 1 in that an n-type single crystal silicon substrate 1 is used instead of the i-type amorphous silicon film 4 and the n-type amorphous silicon film 6. The point is that the impurity diffusion layer 1a is provided therein.

ｎ型単結晶シリコン基板１の裏面においてｉ型非晶質シリコン膜５が形成されていない領域の一部に高濃度のＰ（リン）を熱拡散させることにより不純物拡散層１ａを形成する。その後、不純物拡散層１ａ上に裏面電極８および集電極１０を形成する。   Impurity diffusion layer 1a is formed by thermally diffusing high-concentration P (phosphorus) in part of a region where i-type amorphous silicon film 5 is not formed on the back surface of n-type single crystal silicon substrate 1. Thereafter, the back electrode 8 and the collector electrode 10 are formed on the impurity diffusion layer 1a.

本実施の形態では、負極２００の作製の際にｉ型非晶質シリコン膜４およびｎ型非晶質シリコン膜６を形成する必要がないので、製造工程の短縮化を図ることができる。   In the present embodiment, since it is not necessary to form the i-type amorphous silicon film 4 and the n-type amorphous silicon film 6 when the negative electrode 200 is manufactured, the manufacturing process can be shortened.

（第３の実施の形態）
以下、本発明の第３の実施の形態について説明する。 (Third embodiment)
Hereinafter, a third embodiment of the present invention will be described.

図４は、第３の実施の形態に係る光起電力素子５００ｂの構造を示す模式的断面図である。図４の光起電力素子５００ｂが図１の光起電力素子５００と異なる点は、ｉ型非晶質シリコン膜４がｐ型非晶質シリコン膜７の端部に接している点である。   FIG. 4 is a schematic cross-sectional view showing the structure of the photovoltaic element 500b according to the third embodiment. The photovoltaic element 500b in FIG. 4 is different from the photovoltaic element 500 in FIG. 1 in that the i-type amorphous silicon film 4 is in contact with the end of the p-type amorphous silicon film 7.

以下、図４の光起電力素子５００ｂの製造方法について説明する。ｎ型単結晶シリコン基板１の主面側のｉ型非晶質シリコン膜２、反射防止膜３、裏面側のｉ型非晶質シリコン膜５およびｐ型非晶質シリコン膜７の形成方法は図２の光起電力素子５００と同じである。   Hereinafter, a method for manufacturing the photovoltaic element 500b of FIG. 4 will be described. The formation method of the i-type amorphous silicon film 2, the antireflection film 3, the i-type amorphous silicon film 5 and the p-type amorphous silicon film 7 on the main surface side of the n-type single crystal silicon substrate 1 is as follows. This is the same as the photovoltaic element 500 of FIG.

ｉ型非晶質シリコン膜４およびｎ型非晶質シリコン膜６を形成する際には、メタルマスクをｉ型非晶質シリコン膜５およびｐ型非晶質シリコン膜７の端面に揃うように被せる。それにより、ｎ型単結晶シリコン基板１の裏面の全面がｉ型非晶質シリコン膜４，５で覆われる。その結果、ｎ型単結晶シリコン基板１の露出部におけるキャリアの再結合が防止され、発電効率が向上する。   When the i-type amorphous silicon film 4 and the n-type amorphous silicon film 6 are formed, the metal mask is aligned with the end faces of the i-type amorphous silicon film 5 and the p-type amorphous silicon film 7. Cover. Thereby, the entire back surface of the n-type single crystal silicon substrate 1 is covered with the i-type amorphous silicon films 4 and 5. As a result, carrier recombination in the exposed portion of n-type single crystal silicon substrate 1 is prevented, and power generation efficiency is improved.

（第４の実施の形態）
以下、本発明の第４の実施の形態について説明する。 (Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described.

図５は、第４の実施の形態に係る光起電力素子５００ｃの構造を示す模式的断面図である。図５の光起電力素子５００ｃが図１の光起電力素子５００と異なる点は、ｎ型単結晶シリコン基板１の裏面全面にｉ型非晶質シリコン膜４が形成されている点である。それにより、ｎ型単結晶シリコン基板１の露出部におけるキャリアの再結合が防止され、発電効率が向上する。   FIG. 5 is a schematic cross-sectional view showing the structure of a photovoltaic element 500c according to the fourth embodiment. The photovoltaic element 500c in FIG. 5 differs from the photovoltaic element 500 in FIG. 1 in that an i-type amorphous silicon film 4 is formed on the entire back surface of the n-type single crystal silicon substrate 1. Thereby, recombination of carriers in the exposed portion of n-type single crystal silicon substrate 1 is prevented, and power generation efficiency is improved.

以下、図５の光起電力素子５００ｃの製造方法について説明する。ｎ型単結晶シリコン基板１の主面側のｉ型非晶質シリコン膜２および反射防止膜３の形成方法は図２の光起電力素子５００と同じである。   Hereinafter, a method for manufacturing the photovoltaic element 500c of FIG. 5 will be described. The formation method of the i-type amorphous silicon film 2 and the antireflection film 3 on the main surface side of the n-type single crystal silicon substrate 1 is the same as that of the photovoltaic element 500 of FIG.

ｉ型非晶質シリコン膜４をｎ型単結晶シリコン基板１の裏面全面に形成した後にｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７を形成する。それにより、ｉ型非晶質シリコン膜５を形成する必要がなくなり、製造工程の短縮化が図れる。   After the i-type amorphous silicon film 4 is formed on the entire back surface of the n-type single crystal silicon substrate 1, an n-type amorphous silicon film 6 and a p-type amorphous silicon film 7 are formed. Thereby, it is not necessary to form the i-type amorphous silicon film 5, and the manufacturing process can be shortened.

（第５の実施の形態）
以下、本発明の第５の実施の形態について説明する。 (Fifth embodiment)
The fifth embodiment of the present invention will be described below.

図６は、第５の実施の形態に係る光起電力素子５００ｄの構造を示す模式的断面図である。図６の光起電力素子５００ｄが図５の光起電力素子５００ｃと異なる点は、ｉ型非晶質シリコン膜４内に不純物拡散層４ａが形成され、ｎ型非晶質シリコン膜６がｉ型非晶質シリコン膜４上の全面に形成されている点である。   FIG. 6 is a schematic cross-sectional view showing the structure of a photovoltaic device 500d according to the fifth embodiment. The photovoltaic element 500d in FIG. 6 is different from the photovoltaic element 500c in FIG. 5 in that an impurity diffusion layer 4a is formed in the i-type amorphous silicon film 4 and the n-type amorphous silicon film 6 is i. It is a point formed on the entire surface of the type amorphous silicon film 4.

以下、図６の光起電力素子５００ｄの製造方法について説明する。ｎ型単結晶シリコン基板１の主面側のｉ型非晶質シリコン膜２および反射防止膜３の形成方法は図２の光起電力素子５００と同じである。   Hereinafter, a method for manufacturing the photovoltaic element 500d of FIG. 6 will be described. The formation method of the i-type amorphous silicon film 2 and the antireflection film 3 on the main surface side of the n-type single crystal silicon substrate 1 is the same as that of the photovoltaic element 500 of FIG.

ｉ型非晶質シリコン膜４上の一部の領域にメタルマスクを被せる。続いて、高濃度のＢ等のIII 族元素をｉ型非晶質シリコン膜４にプラズマドープ法によりドープし、不純物拡散層４ａを形成する。その後、ｉ型非晶質シリコン膜４上の全面にｎ型非晶質シリコン膜６を形成する。   A metal mask is put on a part of the region on the i-type amorphous silicon film 4. Subsequently, a high concentration group III element such as B is doped into the i-type amorphous silicon film 4 by a plasma doping method to form an impurity diffusion layer 4a. Thereafter, an n-type amorphous silicon film 6 is formed on the entire surface of the i-type amorphous silicon film 4.

本実施の形態では、ｎ型非晶質シリコン膜６を形成する際にメタルマスクを被せる工程が削減されるため、製造工程の短縮化を図ることができる。なお、ｎ型非晶質シリコン膜６の膜厚は非常に小さいため、不純物拡散層４ａとｎ型非晶質シリコン膜６との間のｐｎ接合は、発電効率にほとんど影響を及ぼさない。   In the present embodiment, since the process of covering the metal mask when forming the n-type amorphous silicon film 6 is reduced, the manufacturing process can be shortened. Since the thickness of the n-type amorphous silicon film 6 is very small, the pn junction between the impurity diffusion layer 4a and the n-type amorphous silicon film 6 hardly affects the power generation efficiency.

（第６の実施の形態）
以下、本発明の第６の実施の形態について説明する。 (Sixth embodiment)
The sixth embodiment of the present invention will be described below.

図７は、第６の実施の形態に係る光起電力素子５００ｅの構造を示す模式的断面図である。図７の光起電力素子５００ｅが図１の光起電力素子５００と異なる点は、
ｐ型非晶質シリコン膜７の全面に裏面電極９が形成されており、ｎ型非晶質シリコン膜６の全面に裏面電極８が形成されている点である。 FIG. 7 is a schematic cross-sectional view showing the structure of a photovoltaic device 500e according to the sixth embodiment. The photovoltaic element 500e in FIG. 7 is different from the photovoltaic element 500 in FIG.
The back electrode 9 is formed on the entire surface of the p-type amorphous silicon film 7, and the back electrode 8 is formed on the entire surface of the n-type amorphous silicon film 6.

以下、図７の光起電力素子５００ｃの製造方法について説明する。ｎ型単結晶シリコン基板１の主面側のｉ型非晶質シリコン膜２および反射防止膜３の形成方法は図２の光起電力素子５００と同じである。   Hereinafter, a method for manufacturing the photovoltaic element 500c of FIG. 7 will be described. The formation method of the i-type amorphous silicon film 2 and the antireflection film 3 on the main surface side of the n-type single crystal silicon substrate 1 is the same as that of the photovoltaic element 500 of FIG.

ｐ型非晶質シリコン膜７を形成する際に用いるメタルマスクを用いて裏面電極９を形成し、ｎ型非晶質シリコン膜６を形成する際に用いるメタルマスクを用いて裏面電極８を形成する。それにより、ｐ型非晶質シリコン膜７の全面に裏面電極９を形成し、ｎ型非晶質シリコン膜６の全面に裏面電極８を形成することができる。この場合、メタルマスクの位置決め回数が低減されるため、効率的である。   A back electrode 9 is formed using a metal mask used when the p-type amorphous silicon film 7 is formed, and a back electrode 8 is formed using a metal mask used when the n-type amorphous silicon film 6 is formed. To do. Thereby, the back electrode 9 can be formed on the entire surface of the p-type amorphous silicon film 7, and the back electrode 8 can be formed on the entire surface of the n-type amorphous silicon film 6. In this case, the number of times of positioning the metal mask is reduced, which is efficient.

また、ｉ型非晶質シリコン膜４，５をＣＶＤ法により形成する前に、ｉ型非晶質シリコン膜４とｉ型非晶質シリコン膜５との間に線状の樹脂からなるリフトオフ層をスクリーン印刷法により予め形成しておいてもよい。   Further, before the i-type amorphous silicon films 4 and 5 are formed by the CVD method, a lift-off layer made of a linear resin is formed between the i-type amorphous silicon film 4 and the i-type amorphous silicon film 5. May be formed in advance by a screen printing method.

この場合、図５の方法によりｉ型非晶質シリコン膜４，５、ｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７を形成し、ｎ型非晶質シリコン膜６、ｐ型非晶質シリコン膜７およびリフトオフ層の全面に裏面電極を形成し、リフトオフ層を取り除く。それにより、裏面電極８，９を形成することができる。   In this case, the i-type amorphous silicon films 4 and 5, the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7 are formed by the method of FIG. A back electrode is formed on the entire surface of the type amorphous silicon film 7 and the lift-off layer, and the lift-off layer is removed. Thereby, the back surface electrodes 8 and 9 can be formed.

また、図２の光起電力素子５００のｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７を形成した後に、裏面電極をｎ型非晶質シリコン膜６、ｐ型非晶質シリコン膜７およびｎ型単結晶シリコン基板１の露出部に形成し、レーザスクライブ法により裏面電極の不要な領域を除去することにより、裏面電極８，９を形成してもよい。レーザの照射条件を調整することにより裏面電極の一部領域を選択的に除去することができる。   Further, after forming the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7 of the photovoltaic element 500 of FIG. The back electrodes 8 and 9 may be formed by forming the silicon film 7 and the exposed portion of the n-type single crystal silicon substrate 1 and removing unnecessary regions of the back electrode by laser scribing. A partial region of the back electrode can be selectively removed by adjusting the laser irradiation conditions.

この場合、レーザの種類としては、エキシマもしくはＹＡＧ（イットリウムアルミニウムガーネット）のＳＨＧ（セカンドハーモニックジェネレーション）、ＴＨＧ（サードハーモニックジェネレーション）等を使用することができる。   In this case, excimer or YAG (yttrium aluminum garnet) SHG (second harmonic generation), THG (third harmonic generation), or the like can be used as the type of laser.

また、レーザスクライブ法の代わりに機械スクライブ法を用いてな裏面電極の不要な領域を除去してもよい。   Further, an unnecessary region of the back electrode may be removed using a mechanical scribe method instead of the laser scribe method.

本実施の形態に係る光起電力素子５００ｅにおいては、裏面電極８，９がｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７上の全面に形成されていることから、ｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７からキャリアの収集を効率良く行うことができる。それにより、光起電力素子５００ｅの発電効率が向上する。   In the photovoltaic device 500e according to the present embodiment, the back electrodes 8 and 9 are formed on the entire surface of the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7, and therefore the n-type. Carriers can be efficiently collected from the amorphous silicon film 6 and the p-type amorphous silicon film 7. Thereby, the power generation efficiency of the photovoltaic element 500e is improved.

（第７の実施の形態）
以下、本発明の第７の実施の形態について説明する。 (Seventh embodiment)
The seventh embodiment of the present invention will be described below.

図８は、第７の実施の形態に係る光起電力素子５００ｆの構造を示す模式的断面図である。図８の光起電力素子５００ｆが図７の光起電力素子５００ｅと異なる点は、ｉ型非晶質シリコン膜５とｉ型非晶質シリコン膜４との間に樹脂等からなる保護層１２が形成されている点である。   FIG. 8 is a schematic cross-sectional view showing the structure of a photovoltaic element 500f according to the seventh embodiment. The photovoltaic element 500f in FIG. 8 differs from the photovoltaic element 500e in FIG. 7 in that the protective layer 12 made of a resin or the like is provided between the i-type amorphous silicon film 5 and the i-type amorphous silicon film 4. Is formed.

ｉ型非晶質シリコン膜４，５を形成する前に予め保護層１０をスクリーン印刷法により形成しておくことにより、図７で説明したレーザスクライブ法、機械スクライブ法等により裏面電極の不要な領域を除去する際にｎ型単結晶シリコン基板１へのダメージを防止することができる。   By forming the protective layer 10 in advance by the screen printing method before forming the i-type amorphous silicon films 4 and 5, no back electrode is required by the laser scribe method, the mechanical scribe method, or the like described in FIG. When the region is removed, damage to the n-type single crystal silicon substrate 1 can be prevented.

（第８の実施の形態）
以下、本発明の第８の実施の形態について説明する。 (Eighth embodiment)
The eighth embodiment of the present invention will be described below.

図９は、第８の実施の形態に係る光起電力素子５００ｇの構造を示す模式的断面図である。図９の光起電力素子５００ｇが図７の光起電力素子５００ｅと異なる点は、ｉ型非晶質シリコン膜４がｎ型単結晶シリコン基板１の裏面全面に形成されている点である。   FIG. 9 is a schematic cross-sectional view showing the structure of a photovoltaic device 500g according to the eighth embodiment. The photovoltaic element 500g in FIG. 9 is different from the photovoltaic element 500e in FIG. 7 in that the i-type amorphous silicon film 4 is formed on the entire back surface of the n-type single crystal silicon substrate 1.

図５で説明した方法によりｉ型非晶質シリコン膜４まで形成した後に、図７で説明した方法によりｎ型非晶質シリコン膜６、ｐ型非晶質シリコン膜７、裏面電極９，１０および集電極１０，１１を形成することにより図９の光起電力素子５００ｇを製造することができる。   After forming up to the i-type amorphous silicon film 4 by the method described in FIG. 5, the n-type amorphous silicon film 6, the p-type amorphous silicon film 7, and the back electrodes 9, 10 are formed by the method described in FIG. Further, by forming the collector electrodes 10 and 11, the photovoltaic element 500g of FIG. 9 can be manufactured.

本実施の形態に係る光起電力素子５００ｇにおいては、ｎ型単結晶シリコン基板１の裏面全面にｉ型非晶質シリコン膜４が形成されていることから、ｎ型単結晶シリコン基板１の露出部におけるキャリアの再結合が防止されるとともに、裏面電極８，９がｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７上の全面に形成されていることからｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７からキャリアの収集を効率良く行うことができる。それにより、発電効率がさらに向上する。   In the photovoltaic device 500g according to the present embodiment, since the i-type amorphous silicon film 4 is formed on the entire back surface of the n-type single crystal silicon substrate 1, the n-type single crystal silicon substrate 1 is exposed. Since the recombination of carriers in the portion is prevented and the back electrodes 8 and 9 are formed on the entire surface of the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7, the n-type amorphous Carriers can be efficiently collected from the silicon film 6 and the p-type amorphous silicon film 7. Thereby, the power generation efficiency is further improved.

（第９の実施の形態）
以下、本発明の第９の実施の形態について説明する。 (Ninth embodiment)
The ninth embodiment of the present invention will be described below.

図１０は、第９の実施の形態に係る光起電力素子５００ｈの構造を示す模式的断面図である。図１０の光起電力素子５００ｈが図７の光起電力素子５００ｅと異なる点は、ｉ型非晶質シリコン膜４がｎ型単結晶シリコン基板１の裏面全面に形成されるとともに、ｎ型非晶質シリコン膜６とｐ型非晶質シリコン膜７との間に樹脂等からなる保護層１２が形成されている点である。   FIG. 10 is a schematic cross-sectional view showing the structure of a photovoltaic device 500h according to the ninth embodiment. The photovoltaic element 500h in FIG. 10 differs from the photovoltaic element 500e in FIG. 7 in that the i-type amorphous silicon film 4 is formed on the entire back surface of the n-type single crystal silicon substrate 1 and the n-type non-crystalline silicon film 4 is formed. A protective layer 12 made of a resin or the like is formed between the crystalline silicon film 6 and the p-type amorphous silicon film 7.

ｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７を形成する前に予め保護層１０をスクリーン印刷法により形成しておくことにより、図７で説明したレーザスクライブ法、機械スクライブ法等により裏面電極の不要な領域を除去する際にｉ型非晶質シリコン膜４へのダメージを防止することができる。   Before forming the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7, the protective layer 10 is formed in advance by a screen printing method, whereby the laser scribe method and the mechanical scribe method described in FIG. For example, damage to the i-type amorphous silicon film 4 can be prevented when an unnecessary region of the back electrode is removed.

本実施の形態に係る光起電力素子５００ｈにおいては、ｎ型単結晶シリコン基板１の裏面全面にｉ型非晶質シリコン膜４が形成されていることから、ｎ型単結晶シリコン基板１の露出部におけるキャリアの再結合が防止されるとともに、裏面電極８，９がｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７上の全面に形成されていることからｎ型非晶質シリコン膜６およびｐ型非晶質シリコン膜７からキャリアの収集を効率良く行うことができる。それにより、発電効率がさらに向上する。   In the photovoltaic device 500h according to the present embodiment, since the i-type amorphous silicon film 4 is formed on the entire back surface of the n-type single crystal silicon substrate 1, the n-type single crystal silicon substrate 1 is exposed. Since the recombination of carriers in the portion is prevented and the back electrodes 8 and 9 are formed on the entire surface of the n-type amorphous silicon film 6 and the p-type amorphous silicon film 7, the n-type amorphous Carriers can be efficiently collected from the silicon film 6 and the p-type amorphous silicon film 7. Thereby, the power generation efficiency is further improved.

（実施例）
以下の実施例では、上記実施の形態の方法で図５の構造を有する光起電力素子５００ｃを作製し、出力特性を測定した。実施例の光起電力素子の作製条件を表２に示す。 (Example)
In the following examples, the photovoltaic device 500c having the structure of FIG. 5 was manufactured by the method of the above embodiment, and the output characteristics were measured. Table 2 shows the conditions for producing the photovoltaic elements of the examples.

Figure 2005101240
Figure 2005101240

表２に示すように、ｐ型非晶質シリコン膜７を形成する際にはＨ2 ガス希釈したＢ2 Ｈ6 ガスを用い、ＳｉＨ4 に対するＢ2 Ｈ6 の濃度を２％にした。また、ｎ型非晶質シリコン膜６を形成する際にはＨ2 ガス希釈したＰＨ3 ガスを用い、ＳｉＨ4 に対するＰＨ3 の濃度を１％にした。 As shown in Table 2, B 2 H 6 gas diluted with H 2 gas was used to form the p-type amorphous silicon film 7, and the concentration of B 2 H 6 with respect to SiH 4 was set to 2%. Further, when the n-type amorphous silicon film 6 was formed, PH 3 gas diluted with H 2 gas was used, and the concentration of PH 3 with respect to SiH 4 was set to 1%.

（比較例）
図１１は、比較例の光起電力素子の構造を示す模式的断面図である。 (Comparative example)
FIG. 11 is a schematic cross-sectional view showing the structure of a photovoltaic element of a comparative example.

図１１に示すように、ｎ型単結晶シリコン基板１０１の主面（表側の面）上にｉ型非晶質シリコン膜１０５（ノンドープ非晶質シリコン膜）およびｐ型非晶質シリコン膜１０７が順に形成されている。ｐ型非晶質シリコン膜１０７上にＩＴＯからなる表面電極１０９が形成され、表面電極１０９上にＡｇからなるくし形の集電極１１１が形成されている。   As shown in FIG. 11, an i-type amorphous silicon film 105 (non-doped amorphous silicon film) and a p-type amorphous silicon film 107 are formed on the main surface (front surface) of an n-type single crystal silicon substrate 101. It is formed in order. A surface electrode 109 made of ITO is formed on the p-type amorphous silicon film 107, and a comb-shaped collector electrode 111 made of Ag is formed on the surface electrode 109.

ｎ型単結晶シリコン基板１０１の裏面には、ｉ型非晶質シリコン膜１０４およびｎ型非晶質シリコン膜１０６が順に形成されている。ｎ型非晶質シリコン膜１０６上にＩＴＯからなる裏面電極１０８が形成され、裏面電極１０８上にＡｇからなるくし形の集電極１１０が形成されている。比較例の光起電力素子では、ｎ型単結晶シリコン基板１０１が主たる発電層となる。   An i-type amorphous silicon film 104 and an n-type amorphous silicon film 106 are sequentially formed on the back surface of the n-type single crystal silicon substrate 101. A back electrode 108 made of ITO is formed on the n-type amorphous silicon film 106, and a comb-shaped collector electrode 110 made of Ag is formed on the back electrode 108. In the photovoltaic element of the comparative example, the n-type single crystal silicon substrate 101 is the main power generation layer.

比較例では、図１１の構造を有する光起電力素子を作製し、出力特性を測定した。比較例の光起電力素子の各膜作製条件は実施例と同じである。   In the comparative example, a photovoltaic device having the structure of FIG. 11 was produced, and the output characteristics were measured. The conditions for producing each film of the photovoltaic element of the comparative example are the same as those of the example.

（評価）
実施例および比較例の光起電力素子の出力特性を測定した。実施例および比較例の光起電力素子の出力特性を表３に示す。 (Evaluation)
The output characteristics of the photovoltaic elements of Examples and Comparative Examples were measured. Table 3 shows the output characteristics of the photovoltaic elements of Examples and Comparative Examples.

Figure 2005101240
Figure 2005101240

表３に示すように、実施例の光起電力素子は、比較例の光起電力素子に比して最大出力Ｐｍａｘ、開放電圧Ｖｏｃ、短絡電流Ｉｓｃおよび曲線因子Ｆ．Ｆ．のいずれも高い値となった。   As shown in Table 3, the photovoltaic elements of the examples had a maximum output Pmax, an open-circuit voltage Voc, a short-circuit current Isc, and a fill factor of F.V. as compared with the photovoltaic elements of the comparative examples. F. Both were high.

以上のことから、実施例の光起電力素子は比較例の光起電力素子よりも高い出力特性を有することがわかった。   From the above, it was found that the photovoltaic elements of the examples had higher output characteristics than the photovoltaic elements of the comparative examples.

以上のように、本発明に係る光起電力素子においては、入射光を最大限に活用できる。また、本発明に係る光起電力素子の製造方法においては、上記光起電力素子を製造することができる。したがって、本発明に係る光起電力素子は、半導体接合を用いた光起電力素子としての用途に適しており、本発明に係る光起電力素子の製造方法は、半導体接合を用いた光起電力素子を製造する用途に適している。   As described above, in the photovoltaic device according to the present invention, incident light can be utilized to the maximum. Moreover, in the manufacturing method of the photovoltaic element which concerns on this invention, the said photovoltaic element can be manufactured. Therefore, the photovoltaic device according to the present invention is suitable for use as a photovoltaic device using a semiconductor junction, and the method for producing a photovoltaic device according to the present invention includes a photovoltaic device using a semiconductor junction. It is suitable for use in manufacturing elements.

（ａ）は第１の実施の形態に係る光起電力素子の裏面を示す平面図であり、（ｂ）は（ａ）の一部拡大図である。(A) is a top view which shows the back surface of the photovoltaic element which concerns on 1st Embodiment, (b) is a partially expanded view of (a). 第１の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 1st Embodiment. 第２の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 2nd Embodiment. 第３の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 3rd Embodiment. 第４の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 4th Embodiment. 第５の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 5th Embodiment. 第６の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 6th Embodiment. 第７の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 7th Embodiment. 第８の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 8th Embodiment. 第９の実施の形態に係る光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element which concerns on 9th Embodiment. 比較例の光起電力素子の構造を示す模式的断面図である。It is typical sectional drawing which shows the structure of the photovoltaic element of a comparative example.

符号の説明Explanation of symbols

１ ｎ型単結晶シリコン基板
２ ｉ型非晶質シリコン膜
３ 反射防止膜
４，５ ｉ型非晶質シリコン膜
６ ｎ型非晶質シリコン膜
７ ｐ型非晶質シリコン膜
８，９ 裏面電極
１０，１１ 集電極
１００ 正極
２００ 負極
３００，４００ 電極
５００ 光起電力素子 1 n-type single crystal silicon substrate 2 i-type amorphous silicon film 3 antireflection film 4, 5 i-type amorphous silicon film 6 n-type amorphous silicon film 7 p-type amorphous silicon film 8, 9 back electrode 10, 11 Collector electrode 100 Positive electrode 200 Negative electrode 300,400 Electrode 500 Photovoltaic element

Claims (8)

一面および他面を有する結晶系半導体を備え、
前記結晶系半導体の前記一面の第１の領域に、真性の第１の非晶質系半導体膜と、一導電型を示す不純物を含む第２の非晶質系半導体膜と、第１の電極とを順に備え、
前記結晶系半導体の前記一面の第２の領域に、前記一導電型と異なる他導電型を示す不純物を含む半導体層と、第２の電極とを順に備えたことを特徴とする光起電力素子。 Comprising a crystalline semiconductor having one side and the other side;
In the first region of the one surface of the crystalline semiconductor, an intrinsic first amorphous semiconductor film, a second amorphous semiconductor film containing an impurity having one conductivity type, and a first electrode In order,
A photovoltaic element comprising a semiconductor layer containing an impurity having another conductivity type different from the one conductivity type, and a second electrode in order in the second region of the one surface of the crystalline semiconductor. . 前記結晶系半導体は、前記一導電型を示す不純物を含むことを特徴とする請求項１記載の光起電力素子。 The photovoltaic device according to claim 1, wherein the crystalline semiconductor includes an impurity having the one conductivity type. 前記半導体層は、前記他導電型を示す不純物を含む第３の非晶質系半導体膜であり、
前記結晶系半導体と前記第３の非晶質系半導体膜との間に真性の第４の非晶質系半導体膜をさらに備えたことを特徴とする請求項１または２記載の光起電力素子。 The semiconductor layer is a third amorphous semiconductor film containing an impurity having the other conductivity type,
3. The photovoltaic element according to claim 1, further comprising an intrinsic fourth amorphous semiconductor film between the crystalline semiconductor and the third amorphous semiconductor film. . 前記結晶系半導体の前記第１の領域の前記第１の非晶質系半導体膜と前記第２の領域の前記第４の非晶質系半導体膜とが連続する共通の非晶質系半導体膜であることを特徴とする請求項３記載の光起電力素子。 A common amorphous semiconductor film in which the first amorphous semiconductor film in the first region of the crystalline semiconductor and the fourth amorphous semiconductor film in the second region are continuous. The photovoltaic element according to claim 3, wherein: 前記第１の領域と前記第２の領域とが間隔をおいて設けられ、前記第１の領域と前記第２の領域との間における前記結晶系半導体の表面に保護層を備えたことを特徴とする請求項１〜３のいずれかに記載の光起電力素子。 The first region and the second region are provided at an interval, and a protective layer is provided on the surface of the crystalline semiconductor between the first region and the second region. The photovoltaic element according to any one of claims 1 to 3. 前記半導体層は、前記結晶系半導体の前記第２の領域に前記他導電型を示す不純物がドープされたドープ層であることを特徴とする請求項１または２記載の光起電力素子。 The photovoltaic element according to claim 1, wherein the semiconductor layer is a doped layer in which the second region of the crystalline semiconductor is doped with an impurity having the other conductivity type. 前記他面の実質的に全面が光入射面であることを特徴とする請求項１〜６のいずれかに記載の光起電力素子。 The photovoltaic element according to claim 1, wherein substantially the entire other surface is a light incident surface. 一導電型を示す不純物を含む結晶系半導体の一面の第１の領域に真性の第１の非晶質系半導体膜を形成する工程と、
前記第１の非晶質系半導体膜上に一導電型を示す不純物を含む第２の非晶質系半導体膜を形成する工程と、
前記結晶系半導体の前記一面の第２の領域に前記一導電型と異なる他導電型を示す不純物を含む半導体層を形成する工程と、
前記第２の非晶質系半導体膜上に第１の電極を形成する工程と、
前記半導体層上に第２の電極を形成する工程とを備えたことを特徴とする光起電力素子の製造方法。 Forming an intrinsic first amorphous semiconductor film in a first region of one surface of a crystalline semiconductor containing an impurity having one conductivity type;
Forming a second amorphous semiconductor film containing an impurity having one conductivity type on the first amorphous semiconductor film;
Forming a semiconductor layer containing an impurity having another conductivity type different from the one conductivity type in the second region of the one surface of the crystalline semiconductor;
Forming a first electrode on the second amorphous semiconductor film;
And a step of forming a second electrode on the semiconductor layer.
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