JP2013150021A - Solar battery element and method for manufacturing solar battery element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solar battery element capable of being easily manufactured, and a method for manufacturing the same.SOLUTION: A solar battery element includes: a polycrystalline silicon substrate including a front face and a back face of the front face, and having one conductivity type in which a longitudinal direction of crystal grains is substantially perpendicular to a thickness direction of the substrate; an intrinsic first thin-film layer on the back face of the polycrystalline silicon substrate; a second thin-film layer exhibiting a reverse conductive type and a first electrode on the first thin-film layer in a first region on the back face of the polycrystalline silicon substrate; and a first diffusion layer exhibiting one conductivity type and a second electrode in a second region on the back face of the polycrystalline silicon substrate.

Description

  The present invention relates to a solar cell element and a method for manufacturing the solar cell element.

  At present, the mainstream solar cell element is a bulk type crystalline silicon solar cell element using a crystalline silicon substrate. This crystalline silicon solar cell element is manufactured by processing a crystalline silicon substrate by an element forming process. A crystalline silicon solar cell module has a configuration in which a plurality of crystalline silicon solar cell elements are connected.

  The crystalline silicon solar cell element has a surface electrode made of metal on the light receiving surface (mostly metal electrodes called busbars and fingers), and has no positive electrode on the light receiving surface. Both positive and negative electrodes There is a so-called BC (back contact) type solar cell element in which is arranged on the non-light-receiving surface side.

  In the conventional BC type solar cell element, the longitudinal direction of the crystal grain of the polycrystalline silicon substrate is the thickness of the substrate for the purpose of suppressing the collision of the photogenerated carrier with the crystal grain boundary and further increasing the output characteristics. There was a BC type solar cell element formed so as to be substantially perpendicular to the vertical direction (see, for example, Patent Document 1).

JP 2005-333016 A

  However, in the above structure, the electrode and the diffusion region are formed in a comb-like shape, and are provided in a state where the p-type region and the n-type region are quite close to each other. For this reason, each counter electrode is in direct contact with the same crystal grain boundary, and the crystal grain boundary serves as a bridge between the electrodes, so that leakage easily occurs. Further, since diffusion regions having different conductivity types exist within the same grain boundary within the substrate, the impurity diffusion rate is high at the crystal grain boundary, so that each dopant diffuses into the crystal grain boundary and Since the high-concentration p-type region and the n-type region are in contact with each other, there is a problem that the tunnel current increases, and a sufficient improvement in output characteristics cannot be obtained.

  It is an object of the present invention to provide a BC type solar cell element with high output characteristics and a method for manufacturing the same.

  A solar cell element according to an embodiment of the present invention includes a polycrystalline silicon substrate having one conductivity type including a front surface and a back surface of the front surface, wherein the longitudinal direction of crystal grains is substantially perpendicular to the thickness direction of the substrate. A second thin film layer having an intrinsic first thin film layer on the back surface side of the polycrystalline silicon substrate and having a reverse conductivity type on the first thin film layer in the first region on the back surface side of the polycrystalline silicon substrate. And a first electrode, and the second region on the back surface side of the polycrystalline silicon substrate has a first diffusion layer exhibiting one conductivity type and a second electrode.

A method for manufacturing a solar cell element according to an aspect of the present invention includes a polycrystalline silicon having a one conductivity type including a front surface and a back surface of the front surface, wherein the longitudinal direction of crystal grains is substantially perpendicular to the thickness direction of the substrate. A step of preparing a substrate, a step of forming a first diffusion layer showing one conductivity type in a second region on the back side of the polycrystalline silicon substrate, and an intrinsic first thin film on the back side of the polycrystalline silicon substrate A step of forming a layer, a step of forming a second thin film layer having a reverse conductivity type on the first thin film layer in a first region on a back surface side of the polycrystalline silicon substrate, and A step of forming a first electrode thereon; and a step of forming a second electrode on the first diffusion layer.

It is a cross-sectional schematic diagram which shows the structure of the solar cell element of 1st embodiment of this invention. (A) The figure which looked at the solar cell element of one Embodiment of this invention from the surface (light-receiving surface) side, (b) was the figure which looked at the solar cell element of (a) from the back side, (c) was (b) FIG. 3 is a schematic diagram enlarging a region R of FIG. It is a cross-sectional schematic diagram which shows the structure of the solar cell element of 2nd embodiment of this invention. (A), (b), (c) is a cross-sectional schematic diagram which shows the modification of the structure of the solar cell element of 2nd embodiment of this invention. It is a schematic diagram which shows a polycrystal silicon ingot. (A) is sectional drawing which shows one Embodiment of a solar cell module, (b) is the top view which looked at the solar cell module of (a) from the surface (light-receiving surface) side.

In the present specification, the notation aEn represents a × 10 ⁿ .

<First embodiment>
≪Solar cell element≫
FIG. 1 is a schematic cross-sectional view partially showing the structure of the solar cell element of the first embodiment. 2A is a view of the solar cell element 20 shown in FIG. 1 as viewed from the front surface (light receiving surface) side, FIG. 2B is a view of the solar cell element as viewed from the back surface side, and FIG. It is R partial enlarged view of 2 (b). Note that the size relationship between the components illustrated in each drawing including FIGS. 1 and 2 does not necessarily reflect the actual relationship.

  In the solar cell element of the present embodiment, an intrinsic first thin film layer 2 (i-type silicon thin film layer) that is not doped with impurities is provided on the back surface side (the lower surface side in FIG. 1) of the silicon substrate 1. . On the first thin film layer 2, a second thin film layer 3 having a reverse conductivity type and a third thin film layer 4 having a single conductivity type are provided. A first electrode 5 is formed on the second thin film layer 3, and a second electrode 6 is formed on the first thin film layer 4. Thus, the solar cell element of this embodiment is a BC type solar cell element. The crystal grains 9 of the silicon substrate 1 are formed so that the longitudinal direction thereof is substantially perpendicular to the thickness direction a of the silicon substrate 1. In the present embodiment, the first region 7 is a region where the second thin film layer 3 and the first electrode 5 are formed on the first thin film layer 2, and the second region 8 is the first thin film layer 2. The region where the third thin film layer 4 is formed.

As the silicon substrate 1 of the solar cell element shown in FIG. 1, for example, a polycrystalline silicon substrate 1 having a predetermined dopant element (impurity for conductivity control) and having one conductivity type is used. When the p-type crystalline silicon substrate 1 is used, for example, B or Ga as a dopant element is doped by about 1E14 to 1E17 atoms / cm ³ . When the n-type crystalline silicon substrate 1 is used, for example, P is doped as a dopant element by about 1E14 to 1E17 atoms / cm ³ . In addition, plate-like silicon may be used. The thickness of the silicon substrate 1 is preferably 300 μm or less, more preferably 250 μm or less, and further preferably 150 μm or less. Then, by slicing parallel to the crystal growth direction of the polycrystalline silicon ingot, the longitudinal direction of the crystal grains 9 is formed so as to be substantially perpendicular to the thickness direction of the substrate. Hereinafter, in the present embodiment, the case where an n-type silicon substrate is used as the semiconductor substrate 1 will be described.

In FIG. 1, the light-receiving surface side (upper surface side in FIG. 1) of the silicon substrate 1 of the solar cell element may be a texture structure (uneven structure) 1a.
The texture structure (uneven structure) 1 a has a role of reducing the reflectance of incident light on the surface of the silicon substrate 1, and forms an uneven surface composed of a large number of fine protrusions 1 b on the light receiving surface side of the silicon substrate 1. To do. The protrusion 1b preferably has a width and a height of 2 μm or less and an aspect ratio (height / width) of 0.1 or more and 2 or less.

The antireflection layer 11 has a role of reducing reflection of incident light, and is formed on the light receiving surface of the silicon substrate 1. The antireflection layer 11 is formed of a silicon nitride film (SiN _x film (composition ratio (x) having a width centered on Si ₃ N ₄ stoichiometry)) or an oxide material film (TiO ₂ film, MgO film, (ITO film, SnO ₂ film, ZnO film, SiO _x film) or the like is preferable. Note that a film having a surface passivation effect may be used as the film constituting the antireflection layer 11, or a hydrogenated amorphous silicon (a-Si: H) film or hydrogenation is provided between the silicon substrate and the antireflection film. A passivation film formed by a single layer or a stacked layer of a microcrystalline silicon (μc-Si: H) film, a SiC film, a silicon nitride film, or a silicon oxide film may be provided.

  The i-type silicon thin film layer 2 is made of an i-type hydrogenated amorphous silicon film (a-Si: H (i) film) or an i-type hydrogenated microcrystalline silicon thin film (μc-Si: H (i) film). The thickness is preferably about 0.5 to 10 nm.

The second thin film layer (p-type silicon thin film layer) 3 is a p-type hydrogenated amorphous silicon obtained by doping, for example, B as a dopant on the i-type silicon thin film layer 2a to be the first region (p-type region) 7. Depending on the film (a-Si: H (p) film) or p-type hydrogenated microcrystalline silicon film (μc-Si: H (p) film), the thickness is about 5 to 50 nm and the dopant concentration is 1E18 to 1E21 atoms / cm. ^It is preferable to form with about ³ .

The third thin film layer (n-type silicon thin film layer) 4 is an n-type hydrogenated amorphous silicon obtained by doping, for example, P as a dopant on the i-type silicon thin film layer 2b to be the second region (n-type region) 8. Depending on the film (a-Si: H (n) film) or n-type hydrogenated microcrystalline silicon film (μc-Si: H (n) film), the thickness is about 5 to 50 nm and the dopant concentration is 1E18 to 1E21 atoms / cm. ^It is preferable to form with about ³ .
Note that microcrystalline silicon in this specification refers to silicon in a state where crystal silicon grain boundaries are filled with amorphous silicon.

  Thus, a so-called heterojunction is formed by the n-type polycrystalline silicon substrate 1, the i-type silicon thin film layer 2, the p-type silicon thin film layer 3, and the n-type silicon thin film layer 4.

  The first electrode (positive electrode) 5 and the second electrode (negative electrode) 6 are provided on the back side of the semiconductor substrate 1 shown in FIG. 2B as comb-like output extraction electrodes having a plurality of electrode fingers. ing. The first electrode 5 is provided on the second thin film layer 3, and the second electrode 6 is provided on the third thin film layer 4, which are different solar cell elements when modularizing the solar cell elements, respectively. The bus bar portions 5a and 6a to which wiring for connecting to each other is connected, and a plurality of finger portions 5b and 6b extending from the respective bus bar portions 5a and 6a and alternately positioned at predetermined intervals. . The width of the finger part 5b of the first electrode and the finger part 6b of the second electrode is 0.1 to 2 mm, and the distance between the finger part 5b of the first electrode and the finger part 6b of the second electrode is 0.1 ˜0.5 mm.

Moreover, the positive electrode 5 and the negative electrode 6 have the structure which formed the translucent conductive layer on the silicon thin film layer, and also formed the conductive layer, for example. The translucent conductive layer has a role of increasing the adhesive strength between the silicon thin film layer and the conductive layer. Further, the component that transmits through the silicon substrate 1 among incident light incident from the light receiving surface side, for example, a long wavelength light of 900 nm or more is reflected with a higher reflectivity and re-enters the silicon substrate 1. As the translucent conductive layer, for example, an ITO film, a SnO ₂ film, a ZnO film or the like is used, and the thickness is preferably about 5 to 100 nm. For example, the conductive layer is formed in a single layer or multiple layers containing Al, Ag, Cu, or the like as a main component. The thickness of the conductive layer is preferably about 0.1 to 3 μm, but may be formed thicker to further reduce resistance.

  Further, a solder region may be formed on the positive electrode 5 and the negative electrode 6 as necessary.

  The solar cell element of the first embodiment is formed such that the longitudinal direction of the crystal grains 9 of the silicon substrate 1 is substantially perpendicular to the thickness direction a of the substrate, as shown in FIG. Yes. Further, as shown in FIG. 2C, the extending direction of the finger portion 5 b of the first electrode and the finger portion 6 b of the second electrode is formed so as to be substantially perpendicular to the longitudinal direction of the crystal grains 9. Yes. If the photogenerated carriers diffuse and move in the lateral direction inside the silicon substrate 1 and do not reach the junction, they cannot be extracted as a photocurrent. However, a crystal grain boundary 10 is provided almost perpendicularly to the main surface of the substrate. Therefore, it is possible to reduce the collision of the photogenerated carriers with the crystal grain boundaries 10. That is, of the formed photogenerated carriers, the number of photogenerated carriers that reach the junction without colliding with the crystal grain boundary can be increased.

  The first electrode 5 and the second electrode 6 are isolated from the crystal grain boundary 10 because the first thin film layer 2 is interposed between the first electrode 5 and the second electrode 6. Therefore, the problem of leakage can be reduced. Furthermore, since the junction region is formed by a heterojunction, the dopant does not diffuse into the junction region as in the prior art, so that the high-concentration p-type region and the n-type region do not contact through the crystal grain boundary 10, An increase in tunnel current can be reduced. Furthermore, by forming a hydrogenated amorphous silicon film (first thin film layer 2) on the back surface of the substrate, hydrogen can be diffused and the crystal grain boundaries 10 can be hydrogen-passivated, thereby further improving the output characteristics. Can do.

  For the above reasons, the solar cell element of the first embodiment can obtain a highly efficient solar cell element with high output characteristics.

≪Method for manufacturing solar cell element≫
In the method for manufacturing a solar cell element according to the first embodiment, a polycrystalline silicon substrate having one conductivity type in which the longitudinal direction of crystal grains is substantially perpendicular to the thickness direction of the substrate is prepared. Forming intrinsic first thin film layer 2 on the side, and forming second thin film layer 3 having a reverse conductivity type on first thin film layer 2 in first region 7 on the back side of silicon substrate 1 Forming a third thin film layer 4 having one conductivity type on the first thin film layer 2 in the second region 8 on the back surface side of the silicon substrate 1, and a first electrode on the second thin film layer 3. 5 and a step of forming the second electrode 6 on the third thin film layer 4.

<Preparation process of silicon substrate>
First, a silicon substrate 1 having an n-type conductivity is prepared. As shown in FIG. 5, a polycrystalline silicon ingot 14 produced by a casting method, a solidification method in a mold, or the like is cut out in parallel to the crystal growth direction, so that the longitudinal direction of the crystal grains 9 is relative to the thickness direction of the substrate. Thus, a polycrystalline silicon substrate that is substantially vertical can be obtained. Such a crystalline silicon substrate having n-type conductivity is formed by doping P as a dopant element to about 1E13 to 1E17 atoms / cm ³ , more preferably about 1E14 to 1E16 atoms / cm ³ .

  However, since the dopant element in the silicon melt is taken into the silicon solid crystal at a constant ratio due to segregation during solidification growth, the resistivity (ρb) varies in the crystal growth direction. In particular, the segregation coefficient of P is 0.35, which is considerably smaller than the segregation coefficient of B, and the specific resistance is greatly different in the height direction of the polycrystalline silicon ingot 14. That is, the resistivity variation of the cut polycrystalline silicon substrate increases. Therefore, the height of the polycrystalline silicon ingot 14 is adjusted to be larger than the length of one side of the polycrystalline silicon substrate so that the specific resistance range of the polycrystalline silicon substrate is minimum ρb ≧ maximum ρb / 2. The upper part of the silicon ingot 14 is removed, and the lower part of the polycrystalline silicon ingot 14 is sliced parallel to the crystal growth direction. The upper part of the polycrystalline silicon ingot 14 is reused as a raw material for producing the next silicon ingot by removing impurities segregated on the outermost surface by wet etching or blasting.

  In addition, in order to remove the mechanical damage layer and the contamination layer on the surface layer portion of the silicon substrate 1 due to the cutting (slicing), the surface layer portions on the front surface side and the back surface side of the cut silicon substrate 1 are made of NaOH, KOH, or hydrofluoric acid. Etching is about 10 to 20 μm each with a mixed solution of nitric acid and nitric acid, and then washed with pure water to remove organic components and metal components. In addition, it is preferable that the surface on which the silicon thin film layer is formed is terminated with hydrogen in the following step by dilute hydrofluoric acid treatment + pure water rinsing treatment. In such a case, a heterojunction interface with excellent quality can be more easily formed between the silicon substrate 1 and the silicon thin film layer.

<Formation process of the first thin film layer>
Next, an i-type silicon thin film layer 2 which is an intrinsic first thin film layer is formed on the non-light-receiving surface side of the silicon substrate. Specifically, an a-Si: H (i) film or a μc-Si: H (i) film) is formed as the i-type silicon thin film layer 2. In addition, the aspect which processes the board | substrate surface in which the i-type silicon thin film layer 2 is formed with a cleaning gas may be sufficient as needed. For example, when the formation surface on the substrate is subjected to a small amount of etching treatment with gas plasma such as CF ₄ or SF ₆ , the surface can be suitably cleaned.

  As a method for forming the i-type silicon thin film layer 2, a CVD method, particularly a plasma CVD (PECVD) method, a Cat-CVD method, or the like can be preferably used. In particular, if the Cat-PECVD method is used, it is possible to form a silicon thin film layer with extremely high quality, so that the quality of the heterojunction formed between the silicon substrate 1 and the silicon thin film layer is improved. Thereby, it becomes easier to realize the high characteristics and high yield of the solar cell element.

  When these CVD methods are used, silane and hydrogen may be used as source gases.

In addition, as film formation conditions at that time, when using the plasma CVD method, adjusting the power density, using the Cat-CVD method, adjusting the type and temperature of the thermal catalyst, and using the Cat-PECVD method Adjust the power density, the type of thermal catalyst, and the temperature. Specifically, when the substrate temperature is 100 ° C. to 300 ° C. (for example, about 200 ° C.), the gas pressure is 10 Pa to 500 Pa, and tungsten is used as the thermal catalyst, the temperature of the thermal catalyst is 1500 ° C. to 2000 ° C. the power density to ^{0.01W / cm 2 ~1W / cm 2} . Thereby, an extremely high quality silicon thin film layer can be formed at a relatively low temperature of about 200 ° C. in a short time.

<Second thin film layer forming step>
Next, a p-type silicon thin film layer 3 which is a second thin film layer having a reverse conductivity type is formed on the i-type silicon thin film layer 2. Specifically, an a-Si: H (p) film or a μc-Si: H (p) film is formed as the p-type silicon thin film layer 3. This forms a heterojunction between the substrate / thin film layer.

  As a method for forming the p-type silicon thin film layer, the CVD method, in particular, the plasma CVD (PECVD) method, the Cat-CVD method, and the like are performed under the same conditions as the first thin film layer forming step, as in the first thin film layer 2. It can be used suitably.

  When the second thin film layer 3 is formed only in the first region 7, a metal mask is formed so as to cover other than the formation region, and after the second thin film layer is formed, unnecessary thin film layers are removed together with the metal mask. That's fine.

<Step of forming the third thin film layer>
Next, an n-type silicon thin film layer 4 which is a third thin film layer having one conductivity type is formed on the i-type silicon thin film layer 2. Specifically, an a-Si: H (p) film or a μc-Si: H (n) film is formed as the n-type silicon thin film layer 4.

  As a method for forming the n-type silicon thin film layer 4, as with the first thin film layer 2, a CVD method, in particular, a plasma CVD (PECVD) method, a Cat-CVD method, or the like is used under the same conditions as the first thin film layer forming step. Can be suitably used.

  When the third thin film layer 4 is formed only in the second region 8, a metal mask is formed so as to cover other than the formation region, and after the third thin film layer is formed, unnecessary thin film layers are removed together with the metal mask. That's fine.

<First electrode and second electrode forming step>
Next, a conductive layer is formed on the p-type silicon thin film layer 3 and the n-type silicon thin film layer 4. In particular, it is preferable to form the conductive layer after forming the above-described translucent conductive layer because the optical reflectance is improved.

The light-transmitting conductive layer can be formed by a sputtering method, a vapor deposition method, an ion plating method, a thermal CVD method, an MOCVD method, a sol-gel method, a method of spraying and heating a liquid material, an inkjet method, or the like. . For example, in the case where an ITO film or a ZnO film as a light-transmitting conductive layer is formed by sputtering, an ITO target doped with 0.5 wt% to 4 wt% of SnO 2 or 0.5 wt% to 4 wt% of Al. Ar gas or a mixed gas of Ar gas and O ₂ gas is flowed using a doped ZnO target, the substrate temperature is 25 ° C. to 250 ° C., the gas pressure is 0.1 to 1.5 Pa, and the power is 0.01 kW to 2 kW. It is a suitable example that the sputtering process is performed under the conditions. In order to separate the first electrode and the second electrode, a metal mask is formed so as to cover the region other than the formation region, and after forming the light-transmitting conductive film, the unnecessary light-transmitting conductive film is removed together with the metal mask. Or may be removed by etching after formation.

The conductive layer can be formed by a sputtering method, an evaporation method, an ion plating method, an inkjet method, or the like. In particular, it is preferable to use a sputtering method from the viewpoint that the heating temperature can be kept low, the heating time can be shortened, and the adhesive strength is high. For example, when an Ag film or an Al film as a conductive layer is formed by sputtering, Ar gas or a mixed gas of Ar gas and O ₂ gas is flowed using a silver or aluminum target, respectively, and the substrate temperature is 25 ° C. A preferred example is that the sputtering process is performed under conditions of ˜250 ° C., gas pressure of 0.1 to 1.5 Pa, and power of 0.01 kW to 2 kW. In order to separate the first electrode and the second electrode, a metal mask may be formed in the same manner as described above or removed by etching after formation. Alternatively, it may be formed by forming an electrode pattern made of a metal paste in which a metal powder such as Ag or Al and an organic component are mixed by a coating method such as a printing method and then firing. At this time, in order not to damage the silicon thin film layer, a resin binder that cures at around 200 ° C. is used. As such a resin binder, one or more of epoxy resin, phenol resin, urethane resin, and polyester resin can be used. Firing may be performed for about 1 hour. Further, the Cu film may be formed by a plating method, or may be formed by combining the above manufacturing methods.

<Texture structure forming process>
Next, it is preferable to form the texture structure 1a on the surface (light receiving surface) side of the silicon substrate 1 by an etching method.

  As a method for forming the texture structure 1a, a wet etching method using an alkaline aqueous solution or a dry etching method using an etching gas can be used. In the case of the wet etching method, it is preferable to perform it before forming the thin film layer.

When the dry etching method is used, the fine texture structure 1a can be formed only on the processing surface side (light receiving surface side). In the case of a BC type solar cell element such as the solar cell element 20A according to the present embodiment, if a texture structure is formed only on the light receiving surface side of the semiconductor substrate 1 by using a dry etching method, n / Since a texture structure is not formed at the p or p / p ⁺ junction formation site, the current density of the diode current (≈dark current density) caused by these junctions, or the diode current originating from the conductive layer interface A solar cell element having a small current density and excellent characteristics can be obtained. In the case of using a wet etching method, etching may be performed after a mask is formed on the back surface side.

Here, there are various methods for the dry etching method, and in particular, when the RIE method (Reactive Ion Etching method) is used, a fine texture structure 1a that can be suppressed to an extremely low light reflectance over a wide wavelength region has a wide area. And can be formed in a short time.

In the case of using the RIE method, for example, chlorine gas (Cl ₂ ), oxygen gas (O ₂ ), and sulfur hexafluoride gas (SF ₆ ) are mixed in the etching apparatus so as to have a mixing ratio of about 1: 5: 5. The substrate to be processed is introduced into the etching chamber (chamber), the reactive gas pressure is set to about 7 Pa, the RF power density is set to about 5 kW / m ² for plasma generation, and the etching process is performed for about 5 minutes. It can be formed satisfactorily. Note that the reading variables such as gas flow rate depend on the size of the chamber. If necessary, an appropriate amount of trifluoromethane gas (CHF ₃ ) or H ₂ O gas may be mixed with the above mixed gas.

  The formation of the texture structure 1a at this stage is not an essential aspect. For example, the texture structure 1a may be performed before the formation of the silicon thin film layer or may be performed after the electrodes are formed. When the wet etching method is used, the texture structure 1a can be formed in succession to the process for removing the damaged layer on the substrate surface layer described above.

<Formation process of antireflection layer>
Next, an antireflection layer 11 is formed on the light receiving surface side of the silicon substrate 1.
The antireflection layer 11 can be formed using PECVD, vapor deposition, sputtering, or the like. When the antireflection layer 11 is formed, the film forming temperature is 400 ° C. or lower, more preferably 300 ° C. or lower. Note that the antireflection layer 11 may also serve as a passivation layer.

<Solder formation process>
If necessary, a mode in which solder regions are formed on the first electrode 5 and the second electrode 6 by solder dipping may be used.
A solar cell element is produced by the procedure as described above.

<Second Embodiment>
FIG. 3 is a schematic cross-sectional view partially showing the structure of the solar cell element of the second embodiment. In addition, about the component which has the same effect as the component of the solar cell element which concerns on 1st embodiment among the components of a solar cell element, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

The silicon substrate 1 of the solar cell element of the present embodiment has a diffusion layer 12 inside in the second region 8 on the back surface side (lower surface side in FIG. 3). A first thin film layer 2 (i-type silicon thin film layer) is provided on the back surface side of the silicon substrate 1, and a second electrode having a reverse conductivity type is formed on the first thin film layer 2 in the first region 7. The thin film layer 3 and the first electrode 5 are sequentially laminated. The first thin film layer 2 has a through hole in the second region 8, and the second thin film layer 2 is formed on the diffusion layer 12 and the first thin film layer 2 exposed in the through hole. An electrode 6 is formed. Thus, the solar cell element of this embodiment is a BC type solar cell element.
Hereinafter, in the present embodiment, the case where an n-type silicon substrate is used as the semiconductor substrate 1 will be described.

In the n-type diffusion layer 12, for example, P (phosphorus) as a dopant is doped inside the surface of the silicon substrate serving as the second region 8, the depth is about 0.2 μm to 0.5 μm, and the dopant concentration is 1E18 to 1E21 atoms. / Cm ³ is preferable.

Thus, a so-called heterojunction is formed by the n-type polycrystalline silicon substrate 1, the i-type silicon thin film layer 2 and the p-type silicon thin film layer 3.

  Similar to the solar cell element of the first embodiment, the solar cell element of the second embodiment is formed such that the longitudinal direction of the crystal grains 9 of the silicon substrate 1 is substantially perpendicular to the thickness direction of the substrate. ing. Further, the extending direction of the second line portion 5 b of the first electrode and the second line portion 6 b of the second electrode is formed so as to be substantially perpendicular to the longitudinal direction of the crystal grains 9. Of the photogenerated carriers formed by the above configuration, the number of photogenerated carriers that reach the junction without colliding with the crystal grain boundary can be increased.

  And since the 1st thin film layer 2 interposes between the 1st electrode 5 and the silicon substrate 1, although the 2nd electrode 6 is contacting the crystal grain boundary 10, the 1st electrode 5 is a crystal grain boundary. Therefore, it is possible to reduce the problem of leakage due to being isolated from 10. Furthermore, since the junction region is formed by a heterojunction, the reverse conductivity type dopant (p-type) does not diffuse into the junction region, but a high-concentration n-type region is formed, but the p-type region and the p-type region are formed through the crystal grain boundary 10. There is no contact, and an increase in tunneling current can be reduced. Furthermore, by forming a hydrogenated amorphous silicon film (first thin film layer 2) on the back surface of the substrate, hydrogen can be diffused and the crystal grain boundaries 10 can be hydrogen-passivated, thereby further improving the output characteristics. Can do.

  The second electrode 6 may be connected to the first diffusion layer 12 via the first thin film layer 2.

  In FIG. 3, the first thin film layer 2 is formed on the first diffusion layer 12. However, as shown in FIG. 4A, the first thin film layer 2 is not provided on the first diffusion layer 12. May be. Further, as shown in FIG. 4B, a second diffusion layer 13 may be formed on the light receiving surface side of the silicon substrate 1, and the photogenerated carriers that have moved to the light receiving surface side are reflected to reach the junction region. The amount of carriers to be increased can be increased. Further, as shown in FIG. 4C, the third thin film layer 4 may be formed on the first diffusion layer, and the second electrode 6 may be formed thereon. Bonding can be reduced.

  For the above reasons, the solar cell element of the second embodiment can provide a highly efficient solar cell element with high output characteristics.

  In the method for manufacturing a solar cell element according to the second embodiment, a polycrystalline silicon substrate 1 having one conductivity type in which the longitudinal direction of crystal grains is substantially perpendicular to the thickness direction of the substrate is prepared. A step of forming a first diffusion layer 12 showing one conductivity type in the second region 8 on the back surface side, a step of forming an intrinsic first thin film layer 2 on the back surface side of the silicon substrate 1, and a polycrystalline silicon substrate Forming a second thin film layer 3 having a reverse conductivity type on the first thin film layer 2 in the first region 7 on the back side; forming a first electrode 5 on the second thin film layer; Forming the second electrode 6 on the first diffusion layer 12. Hereinafter, the same contents as those in the first embodiment will be omitted, and only the changed parts will be described.

<First diffusion layer forming step>
After preparing a silicon substrate as in the first embodiment, an n-type diffusion layer 11 that is a first diffusion layer is formed on the non-light-receiving surface side of the silicon substrate 1. Specifically, P is diffused in the silicon substrate.

As a method for forming the n-type diffusion layer 11, a coating thermal diffusion method in which P ₂ O ₅ in a paste state is applied to the surface of the silicon substrate 1 to thermally diffuse, and POCl ₃ (phosphorus oxychloride) in a gas state is used as a diffusion source. The gas phase thermal diffusion method and the ion implantation method for direct diffusion are used. In the case where the diffusion layer is formed only in the second region 8, a diffusion prevention film may be formed in advance other than the formation region, or the portion may be removed by etching later.

  In addition, when the second diffusion layer 13 is formed on the light receiving surface side of the silicon substrate 1, the same method as described above may be used. In the case of vapor phase thermal diffusion, both the light receiving surface and the non-light receiving surface are diffused simultaneously. A layer can be formed.

  Next, as in the first embodiment, the i-type silicon thin film layer 2 is formed on the non-light-receiving surface side of the silicon substrate 1 except for at least a part of the second region 8, and the i-type silicon is formed in the first region 7. A p-type silicon thin film layer 3 is formed on the thin film layer 2. And a solar cell element is produced by providing a conductive layer on the p-type silicon thin film layer 3 and the n-type diffusion layer 11 to form the first electrode 5 and the second electrode 6.

≪Solar cell module≫
The solar cell module is configured by connecting a plurality of solar cell elements in series and in parallel.

  FIG. 6 is a diagram schematically showing a configuration of a solar cell module 30 configured using a plurality of the solar cell elements 20 of FIG. 6A is a cross-sectional view of the solar cell module 30, and FIG. 6B is a plan view of the solar cell module 30 viewed from the surface (light receiving surface) side.

  As shown in FIG. 6A, the solar cell module 30 includes, for example, a transparent member 22 such as glass, a front side filler 24 made of a transparent ethylene vinyl acetate copolymer (EVA), and the wiring member 21. A plurality of solar cell elements 20 formed by alternately connecting the first electrodes 11 and the second electrodes 12 of adjacent solar cell elements, a back-side filler 25 made of EVA, polyethylene terephthalate (PET), and metal foil And a back surface protective material 23 sandwiched between polyvinyl fluoride resins (PVF). Adjacent solar cell elements 20 use, for example, a wiring member 21 in which the entire surface of a copper foil having a thickness of about 0.1 to 0.2 mm and a width of about 2 mm is covered with a solder material.

  In addition, among the plurality of solar cell elements 20 connected in series, one end of the electrode of the first solar cell element 20 and the last solar cell element 20 is connected to a terminal box 27 which is an output extraction unit by an output extraction wiring 26. Is done. Moreover, although illustration is abbreviate | omitted in Fig.6 (a), as shown in FIG.6 (b), the solar cell module 30 of this embodiment is provided with frames 28, such as aluminum.

  The solar cell module 30 of the present embodiment is a photoelectric conversion element and a photoelectric conversion module that are lower in cost and higher than conventional ones.

<Modification>
In addition, this invention is not limited to the above-mentioned embodiment, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

  For example, in the above-described embodiment, the case where a silicon substrate having n-type conductivity is used has been described, but a silicon substrate having p-type conductivity may be used instead. In this case, if the polarity of each layer is reversed, a solar cell element having the same effect can be obtained in the same process as in the above-described embodiment.

  In the above-described embodiment, the silicon substrate 1 and the thin film layer are described by taking silicon as an example. However, in the present invention, the material of the silicon substrate 1 and the thin film layer is not limited to this. It can also be applied to the case of using other semiconductor materials such as SiGe and Ge.

  In addition, the order of forming the solar cell elements is not limited to the above order. First, after performing the texture structure forming step on the light receiving surface side and the antireflection film forming step, the thin film forming step on the non-light receiving surface side and You may perform a conductive layer formation process.

1: Silicon substrate 2: First thin film layer (i-type silicon thin film layer)
3: Second thin film layer (p-type silicon thin film layer)
4: Third thin film layer (n-type silicon thin film layer)
5: First electrode (positive electrode)
6: Second electrode (negative electrode)
12: First diffusion layer (n-type diffusion layer)
20: Solar cell element

Claims (5)

A polycrystalline silicon substrate having one conductivity type including a front surface and a back surface of the front surface, wherein the longitudinal direction of the crystal grains is substantially perpendicular to the thickness direction of the substrate;
An intrinsic first thin film layer is provided on the back side of the polycrystalline silicon substrate,
In the first region on the back side of the polycrystalline silicon substrate, the second thin film layer showing a reverse conductivity type on the first thin film layer, and a first electrode,
The second region on the back side of the polycrystalline silicon substrate has a first diffusion layer having one conductivity type and a second electrode.   The solar cell element according to claim 1, wherein the first thin film layer is provided on the first diffusion layer.   The solar cell element according to claim 1, wherein the first thin film layer is amorphous silicon. Each of the first electrode and the second electrode is formed as a comb-like electrode having a plurality of electrode fingers on the back surface side of the polycrystalline silicon substrate,
The solar cell element according to any one of claims 1 to 3, wherein a direction in which the electrode fingers of the first electrode and the second electrode extend is substantially perpendicular to a longitudinal direction of the crystal grains. Providing a polycrystalline silicon substrate having one conductivity type including a front surface and a back surface of the front surface, wherein the longitudinal direction of the crystal grains is substantially perpendicular to the thickness direction of the substrate;
Forming a first diffusion layer having one conductivity type in the second region on the back surface side of the polycrystalline silicon substrate;
Forming an intrinsic first thin film layer on the back side of the polycrystalline silicon substrate;
Forming a second thin film layer having a reverse conductivity type on the first thin film layer in the first region on the back side of the polycrystalline silicon substrate;
Forming a first electrode on the second thin film layer;
Forming a second electrode on the first diffusion layer;
The manufacturing method of the solar cell element characterized by having.

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