JPWO2016114371A1 - Photoelectric conversion element, solar cell module and solar power generation system including the same - Google Patents

Abstract

A texture is formed on at least one surface of the semiconductor substrate (1). An n-type amorphous semiconductor layer (4) and a p-type amorphous semiconductor layer (5) are formed on the textured surface of the semiconductor substrate (1). The p-type amorphous semiconductor layer (5) is formed adjacent to the n-type amorphous semiconductor layer (4) in the in-plane direction of the semiconductor substrate (1). When the texture formed on the semiconductor substrate (1) is viewed in plan, the average value of the diameters of the circumscribed circles of the convex portions of the texture is less than 30 μm.

Description

  The present invention relates to a photoelectric conversion element, a solar cell module including the photoelectric conversion element, and a photovoltaic power generation system.

  Conventionally, intrinsic (i-type) amorphous silicon is interposed between an n-type crystalline silicon substrate and a p-type amorphous silicon layer to reduce defects at the interface, and characteristics at the heterojunction interface. There is known a photoelectric conversion device with improved characteristics. This photoelectric conversion device is called a heterojunction solar cell.

  A heterojunction solar cell described in International Publication No. 2013/133005 is shown in FIG. An n-electrode 1506 and a p-electrode 1507 are formed on the n-type amorphous semiconductor layer 1503 and the p-type amorphous semiconductor layer 1505, respectively. In the heterojunction solar cell, electrons which are majority carriers generated in the silicon substrate are diffused into the n-type amorphous semiconductor layer 1503 and collected by the n-electrode 1506. Further, holes that are minority carriers diffuse into the p-type amorphous semiconductor layer 1505 and are collected by the p-electrode 1507.

  In the solar cell shown in FIG. 29, an n-type amorphous semiconductor layer 1503 and a p-type amorphous semiconductor layer 1505 are formed on the back surface opposite to the light receiving surface. A heterojunction solar cell in which an n-type semiconductor layer and a p-type semiconductor layer are thus formed on the back surface is referred to as a back surface heterojunction solar cell.

  In the backside heterojunction solar cell described in International Publication No. 2013/133005, an n-type amorphous semiconductor layer and a p-type amorphous semiconductor layer are formed on a flat surface. Therefore, when a texture is formed on a substrate and an n-type semiconductor layer and a p-type semiconductor layer are formed on the textured surface, it is known how to form a high-quality solar cell. Absent.

  In an embodiment of the present invention, a photoelectric conversion element in which an n-type amorphous semiconductor layer and a p-type amorphous semiconductor layer are formed on the surface of a semiconductor substrate on which a texture is formed, the photoelectric conversion device capable of improving quality. A conversion element is provided.

  Moreover, in embodiment of this invention, the solar cell module provided with the photoelectric conversion element which can improve quality is provided.

  Furthermore, in embodiment of this invention, the solar power generation system provided with the photoelectric conversion element which can improve quality is provided.

  The photoelectric conversion element in one embodiment of the present invention is formed on a semiconductor substrate having a texture formed on at least one surface thereof, and on a surface of the semiconductor substrate on which the texture is formed, and has a first conductivity type. Formed on the surface of the semiconductor substrate on which the texture is formed and formed adjacent to the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate; A second amorphous semiconductor layer having a second conductivity type opposite to the first conductivity type, and an average diameter of circumscribed circles of the convex portions of the texture when the texture is viewed in plan The value is less than 30 μm.

  According to the embodiment of the present invention, when the texture formed on the semiconductor substrate is viewed in plan, the average value of the diameter of the circumscribed circle of the convex portion of the texture is less than 30 μm. Saturation can be suppressed and the quality of the photoelectric conversion element can be improved.

1 is a cross-sectional view showing a configuration of a photoelectric conversion element according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing a texture structure in which a plurality of pyramidal irregularities having various sizes and shapes are formed. FIG. 3 is a diagram illustrating the relationship between the texture size of the back surface of the semiconductor substrate and the reverse saturation current density. FIG. 4 is an enlarged view of the electrode and the protective film shown in FIG. FIG. 5 is a cross-sectional view showing a detailed structure of the n-type amorphous semiconductor layer shown in FIG. FIG. 6 is a cross-sectional view showing another detailed structure of the n-type amorphous semiconductor layer shown in FIG. FIG. 7 is a first process diagram showing a method for manufacturing the photoelectric conversion element shown in FIG. 1. FIG. 8 is a second process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 9 is a third process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 10 is a fourth process diagram illustrating the method of manufacturing the photoelectric conversion element shown in FIG. FIG. 11 is a fifth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 12 is a view showing an SEM photograph of a semiconductor substrate on which texture structures having different sizes are formed. FIG. 13 is a plan view seen from the back side of the photoelectric conversion element shown in FIG. FIG. 14 is a plan view of the wiring sheet. FIG. 15 is a diagram showing the results of a moisture-proof resistance test. FIG. 16 is a diagram for explaining the inclination angle of the texture. FIG. 17 is a diagram for explaining that a semiconductor layer and a dopant wrap around under a shadow mask when an n-type amorphous semiconductor layer and a p-type amorphous semiconductor layer are patterned. FIG. 18 is a diagram for explaining a void region between a semiconductor substrate on which a texture is formed and a shadow mask. FIG. 19 is a diagram for explaining that boron, which is a p-type dopant, wraps around inward from the edge of the shadow mask. FIG. 20 is a diagram for explaining that the wraparound width of boron varies depending on the texture size. FIG. 21 is a cross-sectional view showing the configuration of the photoelectric conversion element according to Embodiment 2 of the present invention. FIG. 22 is a schematic diagram showing a configuration of a cluster type CVD apparatus. FIG. 23 is a schematic diagram illustrating a configuration of a photoelectric conversion module including the photoelectric conversion element according to the third embodiment. FIG. 24 is a schematic diagram illustrating a configuration of a photovoltaic power generation system including the photoelectric conversion element according to the fourth embodiment. FIG. 25 is a schematic diagram showing the configuration of the photoelectric conversion module array shown in FIG. FIG. 26 is a schematic diagram illustrating a configuration of another photovoltaic power generation system including the photoelectric conversion element according to the fourth embodiment. FIG. 27 is a schematic diagram illustrating a configuration of a photovoltaic power generation system including the photoelectric conversion element according to the fifth embodiment. FIG. 28 is a schematic diagram illustrating a configuration of another photovoltaic power generation system including the photoelectric conversion element according to the fifth embodiment. FIG. 29 is a cross-sectional view showing a heterojunction solar cell described in International Publication No. 2013/133005. FIG. 30 is a cross-sectional view illustrating a configuration of the photoelectric conversion element in Embodiment 6. FIG. 31 is a diagram illustrating a part of the process for manufacturing the photoelectric conversion element in Embodiment 6, and after the p-type amorphous semiconductor layer is formed, the n-type amorphous semiconductor layer is formed. It is a figure for demonstrating the manufacturing method at the time of forming. FIG. 32 is a cross-sectional view showing the configuration of the photoelectric conversion element according to the sixth embodiment when no texture is formed on the back surface of the semiconductor substrate.

  The photoelectric conversion element in one embodiment of the present invention is formed on a semiconductor substrate having a texture formed on at least one surface thereof, and on a surface of the semiconductor substrate on which the texture is formed, and has a first conductivity type. Formed on the surface of the semiconductor substrate on which the texture is formed and formed adjacent to the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate; A second amorphous semiconductor layer having a second conductivity type opposite to the first conductivity type, and an average diameter of circumscribed circles of the convex portions of the texture when the texture is viewed in plan The value is less than 30 μm (first configuration).

  According to the first configuration, the saturation of the reverse saturation current density can be suppressed, so that the quality of the photoelectric conversion element can be improved. In addition, it is possible to improve the characteristics and reliability of the photoelectric conversion element by suppressing the wraparound of the source gas and the dopant gas used when forming the first amorphous semiconductor layer and the second amorphous semiconductor layer. Can do.

  In the first configuration, an intrinsic amorphous material formed between the surface of the semiconductor substrate on which the texture is formed and the first amorphous semiconductor layer and the second amorphous semiconductor layer. It can also be set as the structure further provided with a quality semiconductor layer (2nd structure). According to the second configuration, defects at the interface between the semiconductor substrate and the first amorphous semiconductor layer and at the interface between the semiconductor substrate and the second amorphous semiconductor layer can be reduced.

  In the first or second configuration, the photoelectric conversion element includes a first electrode formed on the first amorphous semiconductor layer and a second electrode formed on the second amorphous semiconductor layer. And a protective film formed so as to cover at least part of the first electrode and the second electrode (third configuration). According to the third configuration, the surface of the lower electrode of the protective film is protected by the protective film, and oxidation and discoloration of the surface can be prevented together, so that long-term reliability of the electrode can be ensured.

  In any one of the first to third configurations, in the one thin film formed on the semiconductor substrate, a point having the maximum film thickness is defined as a first point, and the in-plane direction of the one thin film The thin film thickness decreasing rate changes from the first decreasing rate to a second decreasing rate larger than the first decreasing rate, or in the in-plane direction of the one thin film. The point at which the sign of the rate of change of the change from negative to positive is defined as the second point, and the region from the first point to the second point in the in-plane direction of the one thin film is defined as the film thickness reduction region. In this case, at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer may have the thickness reduction region (fourth configuration). According to the fourth configuration, carriers are interposed via the amorphous semiconductor layer as compared with the configuration in which the first amorphous semiconductor layer and the second amorphous semiconductor layer do not have the film thickness reduction region. The resistance when reaching the electrode is reduced. Thereby, the conversion efficiency of a photoelectric conversion element can be improved.

  A photoelectric conversion element according to an embodiment of the present invention includes a semiconductor substrate, an n-type amorphous semiconductor layer formed on the semiconductor substrate and containing phosphorus as a dopant, and an in-plane direction of the semiconductor substrate on the semiconductor substrate. And a p-type amorphous semiconductor layer containing boron as a dopant, and formed between the n-type amorphous semiconductor layer and the semiconductor substrate. The high concentration region of boron whose boron concentration is higher than the boron concentration in the region where the p-type amorphous semiconductor layer is formed is not included (fifth configuration). According to the fifth configuration, since it is possible to suppress a decrease in electrical characteristics when the n-type amorphous semiconductor layer is formed on the boron high-concentration region, the quality of the photoelectric conversion element is improved. be able to.

  In the fifth configuration, a texture may be formed on a surface of the semiconductor substrate on which the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer are formed (sixth configuration). In the structure in which the texture is formed on the semiconductor substrate, the boron concentration in the high-concentration region of boron is larger and the width of the boron diffusion region is wider than in the structure in which the texture is not formed. However, according to the sixth configuration, even when the texture is formed on the surface on which the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer of the semiconductor substrate are formed, the n-type amorphous semiconductor Since the layer is formed so as not to overlap the high-concentration region of boron, the lifetime of minority carriers can be prevented from being lowered, so that the quality of the photoelectric conversion element can be improved.

  In the sixth configuration, when the texture is viewed in plan, the average value of the diameters of circumscribed circles of the convex portions of the texture can be less than 30 μm. According to the sixth configuration, the saturation of the reverse saturation current density can be suppressed, so that the quality of the photoelectric conversion element can be improved. In addition, it is possible to improve the characteristics and reliability of the photoelectric conversion element by suppressing the wraparound of the source gas and the dopant gas used when forming the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer. .

[Embodiment]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. In addition, in order to make the explanation easy to understand, in the drawings referred to below, the configuration is shown in a simplified or schematic manner, or some components are omitted. Further, the dimensional ratio between the constituent members shown in each drawing does not necessarily indicate an actual dimensional ratio.

  In this specification, the amorphous semiconductor layer may include a microcrystalline phase. The microcrystalline phase includes crystals having an average particle diameter of 1 to 50 nm.

[Embodiment 1]
1 is a cross-sectional view showing a configuration of a photoelectric conversion element according to Embodiment 1 of the present invention. Referring to FIG. 1, a photoelectric conversion element 10 according to Embodiment 1 of the present invention includes a semiconductor substrate 1, an antireflection film 2, a passivation film 3, an n-type amorphous semiconductor layer 4, and a p-type non-layer. A crystalline semiconductor layer 5, electrodes 6 and 7, and a protective film 8 are provided.

  The semiconductor substrate 1 is made of, for example, an n-type single crystal silicon substrate. The semiconductor substrate 1 has a thickness of 100 to 150 μm, for example. The semiconductor substrate 1 has a texture structure formed on both sides.

  The antireflection film 2 is disposed in contact with one surface (light receiving surface) of the semiconductor substrate 1. Of the both surfaces of the semiconductor substrate 1, in order to allow sunlight to enter from the surface on which the antireflection film 2 is disposed, the surface on which the antireflection film 2 is disposed is referred to as a light receiving surface. Of the two surfaces of the semiconductor substrate 1, the surface opposite to the light receiving surface is referred to as the back surface.

  In the photoelectric conversion element 10 in the present embodiment, the size of the texture formed on the back surface of the semiconductor substrate 1 is less than 30 μm. The definition of the texture size and the reason why the size of the texture formed on the back surface of the semiconductor substrate 1 is less than 30 μm will be described later.

  Note that an intrinsic amorphous semiconductor layer or an n-type or p-type conductive amorphous semiconductor layer may be provided between the antireflection film 2 and the light receiving surface of the semiconductor substrate 1. This configuration is preferable because the passivation property of the light receiving surface can be improved.

  The passivation film 3 is disposed in contact with the back surface of the semiconductor substrate 1.

  The n-type amorphous semiconductor layer 4 is disposed in contact with the passivation film 3.

  The p-type amorphous semiconductor layer 5 is disposed adjacent to the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1. More specifically, the p-type amorphous semiconductor layer 5 is arranged at a desired distance from the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1.

  The n-type amorphous semiconductor layers 4 and the p-type amorphous semiconductor layers 5 are alternately arranged in the in-plane direction of the semiconductor substrate 1.

  The electrode 6 is disposed on the n-type amorphous semiconductor layer 4 in contact with the n-type amorphous semiconductor layer 4.

  The electrode 7 is disposed on the p-type amorphous semiconductor layer 5 in contact with the p-type amorphous semiconductor layer 5.

  The protective film 8 is disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7. More specifically, the protective film 8 includes the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrode between the adjacent n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5. 6 and 7 and a portion of the passivation film 3 disposed between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. . The protective film 8 has an opening 8A on the electrodes 6 and 7, and is formed in a region of 5 μm or more from the ends of the electrodes 6 and 7 toward the inside of the electrodes 6 and 7.

  The antireflection film 2 is made of, for example, a silicon nitride film and has a film thickness of, for example, 60 nm.

  The passivation film 3 is made of, for example, any of amorphous silicon, amorphous silicon oxide, amorphous silicon nitride, amorphous silicon oxynitride, and polycrystalline silicon.

  In the case where the passivation film 3 is made of an oxide of amorphous silicon, the passivation film 3 may be made of a thermal oxide film of silicon or formed by a vapor phase film forming method such as a plasma CVD (Chemical Vapor Deposition) method. It may be made of a silicon oxide.

  The passivation film 3 has a film thickness of 1 to 20 nm, for example, and preferably has a film thickness of 1 to 3 nm. When the passivation film 3 is made of a silicon insulating film, the passivation film 3 has a film thickness that allows carriers (electrons and holes) to tunnel. In the first embodiment, the passivation film 3 is made of a thermal oxide film of silicon, and the thickness of the passivation film 3 is set to 2 nm.

  The n-type amorphous semiconductor layer 4 is an amorphous semiconductor layer having n-type conductivity and containing hydrogen. The n-type amorphous semiconductor layer 4 includes, for example, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, and n-type amorphous silicon nitride. N-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide, and the like.

  The n-type amorphous semiconductor layer 4 includes, for example, phosphorus (P) as an n-type dopant. The n-type amorphous semiconductor layer 4 has a thickness of 3 to 50 nm, for example.

  The p-type amorphous semiconductor layer 5 is an amorphous semiconductor layer having p-type conductivity and containing hydrogen. The p-type amorphous semiconductor layer 5 includes, for example, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, and p-type amorphous silicon nitride. , P-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, and the like.

  The p-type amorphous semiconductor layer 5 includes, for example, boron (B) as a p-type dopant. The p-type amorphous semiconductor layer 5 has a thickness of 5 to 50 nm, for example.

[Definition of texture size]
In this specification, the size of the texture means a size in a state in which the main surface of the semiconductor substrate is viewed in plan, that is, in a state viewed from vertically above the main surface. As a specific example of the texture, there is a pyramidal (quadrangular pyramid or quadrangular frustum-shaped) uneven structure obtained by performing anisotropic etching on an n-type single crystal silicon substrate having a (100) principal surface. is there. As shown in FIG. 2, the actual texture has a plurality of pyramidal irregularities of various sizes and shapes. This unevenness includes overlapping and deformed ones.

  Therefore, in the present embodiment, when the texture is viewed in plan, the average value of the diameters of the circumscribed circles of the convex portions of the texture is defined as the texture size. Here, the size of the texture was obtained by the following method.

  An area having a size of 100 μm × 100 μm is extracted from the semiconductor substrate 1, and 20 pieces (r 1, r 1, r 1) from the extracted area in order from the longest one of the oblique line lengths (the oblique line lengths in plan view) r r2,..., r20) are detected. Then, twice the average length of the detected 20 diagonal lengths r (r1, r2,..., R20) is set as the size of the texture structure. This is because, in a 100 μm × 100 μm region of the semiconductor substrate 1, when the texture is viewed in plan, the diameters R of the circumscribed circles of the pyramid-shaped convex portions are 20 in order from the longest one (R 1, R 2 ,..., R20) is detected, and is equal to the average length of the diameters R of the 20 circumscribed circles detected.

  Note that the size of the texture structure may be defined based on the length of one side of the bottom surface of the pyramidal unevenness, or the size of the texture structure may be defined based on the height of the pyramidal unevenness. . For example, when the shape of the pyramid-shaped unevenness is a quadrangular pyramid whose bottom surface is a square, the length a of one side of the bottom surface has a relationship of a diagonal line length r of the side surface in a plan view and a = 2 × r / √2. is there. When the angle formed between the bottom surface and the oblique side of the side surface is θ, the height b has a relationship of b = r × tan θ.

  As will be described later, the size of the texture is less than 30 μm. The texture size is preferably 25 μm or less. The texture size can be easily measured by observation with an SEM or the like.

[Reason why the size of the texture formed on the back surface of the semiconductor substrate 1 is less than 30 μm]
In the backside heterojunction solar cell in this embodiment, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are adjacent to each other on the backside of the semiconductor substrate 1. As will be described later, when the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed using the shadow mask, the source gas or the dopant gas wraps around the inner side in the in-plane direction below the shadow mask. Will occur. It has been found that the reverse saturation current density of the IV characteristic of the manufactured solar cell increases when this wraparound increases. It was also found that when the wraparound of the source gas and the dopant gas is increased, the insulation between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is impaired and current leakage occurs.

FIG. 3 is a diagram showing the relationship between the texture size of the back surface of the semiconductor substrate 1 and the reverse saturation current density. When the texture size is 30 μm or more, the reverse saturation current density is 5 × 10 ⁻³ mA / cm ² or more, and the reverse saturation current density shows a saturation tendency regardless of the texture size. From this, it is considered that current leakage is large.

On the other hand, when the texture size is less than 30 μm, the reverse saturation current density is about 6 × 10 ⁻⁴ mA / cm ² or less, and the reverse saturation current density can be reduced by about one digit. The reverse saturation current density determines the quality of the pn junction of the photoelectric conversion element. A smaller value can improve the static characteristics of the solar cell such as an open circuit voltage.

  As shown in FIG. 3, when the texture size is 30 μm or more, the reverse saturation current density has a substantially constant characteristic (k2), but when the texture size is less than 30 μm, the smaller the texture size, The reverse saturation current density is reduced (k1). That is, it was found that the characteristics differ greatly between the case where the texture size is 30 μm or more and the case where it is less than 30 μm. As described above, the smaller the reverse saturation current density can improve the static characteristics of the solar cell.

  That is, since it is critical to make the texture size less than 30 μm, in the photoelectric conversion element in the present embodiment, the size of the texture formed on the back surface of the semiconductor substrate 1 is made less than 30 μm.

  As shown in FIG. 3, when the texture size is 25 μm or less, there is a large step in the characteristics and the reverse saturation current density is reduced by about one digit compared to the case where the texture size is 30 μm or more. Therefore, since it is also critical to make the texture size 25 μm or less, the texture size is more preferably 25 μm or less.

Further, when the texture size is 10 μm or less, the reverse saturation current density is 3 × 10 ⁻⁵ mA / cm ² or less, which is more preferable.

  FIG. 4 is an enlarged view of the electrodes 6 and 7 and the protective film 8 shown in FIG. 4A is an enlarged view of a portion where the electrode 6 is formed, and FIG. 4B is an enlarged view of a portion where the electrode 7 is formed. However, in FIG. 4, for easy understanding of the structure, the back surface of the semiconductor substrate 1 is flat, and the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed on the flat passivation film 3. The structure in which is formed is shown. However, in actuality, as shown in FIG. 1, a texture structure is formed on the back surface of the substrate 1, a passivation film 3 is formed on the surface on which the texture structure is formed, and the passivation film 3 having an uneven shape. An n-type amorphous semiconductor layer 4 and a p-type amorphous semiconductor layer 5 are formed thereon.

  Referring to FIG. 4, electrode 6 includes conductive layers 6a and 6b.

  Conductive layer 6 a is disposed in contact with n-type amorphous semiconductor layer 4. The conductive layer 6b is disposed in contact with the conductive layer 6a. When the width of the opening 8A of the protective film 8 is L and the distance from the ends of the electrodes 6 and 7 to the opening 8A is H, the conductive layers 6a and 6b are in-plane with the n-type amorphous semiconductor layer 4. In the direction, the n-type amorphous semiconductor layer 4 is formed in a range of H + L / 2 on both sides from the center. The width L is, for example, 20 μm or more, and preferably 100 μm or more. By setting the width L to such a value, the adhesion between the external wiring and the electrodes 6 and 7 can be secured, and the contact resistance can be lowered. The distance H is, for example, 5 μm or more in consideration of the adhesion between the electrodes 6 and 7 and the protective film 8.

  The electrode 7 includes conductive layers 7a and 7b. Conductive layer 7 a is disposed in contact with p-type amorphous semiconductor layer 5. The conductive layer 7b is disposed in contact with the conductive layer 7a. The conductive layers 7 a and 7 b are formed in a range of H + L / 2 on both sides from the center of the p-type amorphous semiconductor layer 5 in the in-plane direction of the p-type amorphous semiconductor layer 5.

  As a result, each of the electrodes 6 and 7 has a length of 2H + L in the in-plane direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

  The protective film 8 has a two-layer structure of protective layers 8a and 8b, for example. When the protective film 8 is formed on the n-type amorphous semiconductor layer 4, the protective layer 8 a is disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4 and the electrode 6. The protective layer 8b is disposed in contact with the protective layer 8a. When the protective film 8 is formed on the p-type amorphous semiconductor layer 5, the protective layer 8 a is disposed in contact with the passivation film 3, the p-type amorphous semiconductor layer 5 and the electrode 7. The protective layer 8b is disposed in contact with the protective layer 8a.

  In the in-plane direction of the n-type amorphous semiconductor layer 4, a region outside the n-type amorphous semiconductor layer 4 from the end of the electrode 6 is referred to as a gap region G 1, and the p-type amorphous semiconductor layer 5 A region outside the end of the electrode 7 in the in-plane direction of the p-type amorphous semiconductor layer 5 is referred to as a gap region G2. As a result, the gap region G1 exists on both sides of the n-type amorphous semiconductor layer 4 in the in-plane direction of the n-type amorphous semiconductor layer 4. In addition, a gap region G <b> 2 exists on both sides of the p-type amorphous semiconductor layer 5 in the in-plane direction of the p-type amorphous semiconductor layer 5.

  As a result of the protective film 8 being disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4 and the electrode 6, and being disposed in contact with the passivation film 3, the p-type amorphous semiconductor layer 5 and the electrode 7, the semiconductor In the regions of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 that are adjacent in the in-plane direction of the substrate 1, there is a gap region G (= G1 + G2). As shown in FIG. 1, the protective film 8 is formed on a part of the electrodes 6 and 7 and the gap region G.

  The gap region G is a region where the passivation film 3, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are exposed, and has a width of 20 μm to 500 μm, for example.

  When the electrodes 6 and 7 are made of, for example, silver (Ag) or aluminum (Al), the reflectance of the electrodes 6 and 7 is 90% or more. The light that can reach the back surface of the semiconductor substrate 1 is light in a long wavelength region of about 800 to 1200 nm. The light incident from the light receiving surface of the semiconductor substrate 1 is reflected by the electrodes 6 and 7 and returns into the semiconductor substrate 1 when entering the region where the electrodes 6 and 7 are provided. The probability of being absorbed increases. However, when light is incident on the gap region G where the electrodes 6 and 7 are not provided, there is no reflection by the electrodes 6 and 7, so there is a case where the incident light cannot be effectively used because it passes through the back surface as it is. If the width of the gap region G is increased, light that is not reflected by the electrodes 6 and 7 increases, which is not preferable. For this reason, the width of the gap region G is preferably 500 μm or less, and more preferably 300 μm or less.

  Each of the conductive layers 6a and 7a is made of a transparent conductive film. The transparent conductive film is made of, for example, ITO (Indium Tin Oxide), ZnO, and IWO (Indium Tungsten Oxide).

  Each of the conductive layers 6b and 7b is made of metal. Examples of metals include Ag, Al, nickel (Ni), copper (Cu), tin (Sn), platinum (Pt), gold (Au), chromium (Cr), tungsten (W), cobalt (Co), and titanium. It is made of any one of (Ti), an alloy thereof, or a laminated film of two or more layers of these metals.

  As the conductive layers 6a and 7a, it is preferable to use transparent conductive films having good adhesion to the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively. As the conductive layers 6b and 7b, conductive films It is preferable to use a metal having a high rate.

  The film thickness of each of the conductive layers 6a and 7a is, for example, 3 to 100 nm. The film thickness of each of the conductive layers 6b and 7b is preferably 50 nm or more. In Embodiment 1, for example, the film thickness is 0.8 μm.

  In the first embodiment, the electrode 6 may be composed only of the conductive layer 6b, and the electrode 7 may be composed only of the conductive layer 7b. In this case, there are no conductive layers 6a and 7a, and the conductive layers 6b and 7b are in contact with the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively.

  When the conductive layers 6a and 7a are not provided, the conductive layers 6b and 7b are composed of metal films, and have adhesiveness with the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 that are the base layers, respectively. A high metal is preferred. For example, the conductive layers 6b and 7b are a laminate of an adhesion layer made of Ti, Ni, Al, Cr or the like and having a film thickness of about 1 to 10 nm, and a light reflecting metal mainly composed of Al, Ag, or the like. Consists of structure.

  Further, since the conductive layers 6 b and 7 b are in contact with the protective film 8, it is necessary to consider the adhesion with the protective film 8. When an oxide such as silicon, aluminum, titanium and zirconia, a silicon and aluminum nitride film, a silicon and aluminum oxynitride film, or the like is used as the protective film 8, the surface of the conductive layers 6b and 7b on the protective film 8 side is , Al, indium (In), Ti, Ni, Cu, Cr, W, Co, palladium (Pd), and Sn are preferable.

  Furthermore, each of the electrodes 6 and 7 may consist of a single film of a transparent conductive film. In this case, the transparent conductive film is made of the above-described ITO or the like.

  Each of the protective layers 8a and 8b is made of an inorganic insulating film. The inorganic insulating film is made of an oxide film, a nitride film, an oxynitride film, or the like.

  The oxide film is made of an oxide film such as silicon, aluminum, titanium, zirconia, hafnium, zinc, tantalum, and yttrium.

  The nitride film is made of a nitride film such as silicon and aluminum.

  The oxynitride film is made of an oxynitride film such as silicon and aluminum.

  The protective layer 8b is made of an inorganic insulating film different from the protective layer 8a. That is, two types of films are selected from the inorganic insulating films described above to form the protective layers 8a and 8b.

  Moreover, the protective layer 8a may consist of a semiconductor layer, and the protective layer 8b may consist of the inorganic insulating film mentioned above.

  In this case, the semiconductor layer is an amorphous semiconductor layer. The amorphous semiconductor layer is made of amorphous silicon, amorphous silicon germanium, amorphous germanium, amorphous silicon carbide, amorphous silicon nitride, amorphous silicon oxide, amorphous silicon oxynite. It consists of a ride and amorphous silicon carbon oxide. Since the higher insulation can suppress the leakage between the electrodes 6 and 7, the protective layer 8a is preferably made of an intrinsic amorphous semiconductor layer. For example, the protective layer 8a is made of intrinsic amorphous silicon, and the protective layer 8b is made of a silicon nitride film.

  However, when the protective layer 8b is made of an insulating film, the protective layer 8a may be made of an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer.

  The protective layer 8b is preferably made of a dielectric film having a positive fixed charge. The dielectric film having a positive fixed charge is, for example, a silicon nitride film and a silicon oxynitride film.

  Since the semiconductor substrate 1 is made of n-type single crystal silicon, when the protective layer 8b is made of a dielectric film having a positive fixed charge, the protective layer 8b applies an electric field to holes that are minority carriers, and the gap The lifetime of minority carriers (holes) in the region G can be maintained long.

  The protective film 8 is not limited to a two-layer structure, and may be a single layer or a multilayer structure of two or more layers.

  When the protective film 8 is composed of a single layer, the protective film 8 is composed of one kind of film selected from the inorganic insulating films described above.

  When the protective film 8 has a multilayer structure, the protective film 8 includes the protective layers 8a and 8b described above in the multilayer structure.

  As described above, when the protective film 8 has a two-layer structure, the protective layer 8a is formed of an amorphous semiconductor layer, and the protective layer 8b is formed of an insulating film, whereby the n-type amorphous semiconductor layer 4 and This is preferable because the passivation property for the p-type amorphous semiconductor layer 5 and the insulation between the electrodes 6 and 7 can be compatible.

  When the semiconductor substrate 1 is made of an n-type silicon substrate, the protective layer 8b is formed of a dielectric film having a positive fixed charge, so that an electric field is applied to the gap region, and minority carriers (holes) in the gap region are formed. Since lifetime can be lengthened, it is further preferable.

  Further, when the above-described inorganic insulating film is included in the multilayer structure of the protective film 8, it diffuses into the amorphous semiconductor layers (n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5). Since the moisture-proof effect which prevents a moisture etc. can be acquired, it is preferable. Among the inorganic insulating films described above, a silicon nitride film and a silicon oxynitride film are particularly preferable because they have a particularly high moisture resistance as compared with other inorganic insulating films. When an n-type silicon substrate is used, moisture resistance and the electric field effect due to positive fixed charges can be obtained together, so that both long-term reliability and high efficiency of the photoelectric conversion element 10 are achieved. can do.

  For example, when the protective film 8 is a multilayer film having a two-layer structure or more, for example, a three-layer structure, one protective layer (a protective layer in contact with the n-type amorphous semiconductor layer 4 or the p-type amorphous semiconductor layer 5). Is made of an amorphous semiconductor layer, and the remaining two protective layers are made of two types of films selected from inorganic insulating films.

  Further, when the protective film 8 is composed of a single layer or multiple layers, the protective film 8 may have a structure in which an organic insulating film or the like is formed on the above-described inorganic insulating film.

  The organic substance includes, for example, an imide resin, an epoxy resin, a fluororesin, a polycarbonate, a liquid crystal polymer, and the like.

  The imide resin is, for example, polyimide. The fluororesin is, for example, polytetrafluoroethylene (PTFE). The organic substance may be a resist formed by screen printing.

  FIG. 5 is a cross-sectional view showing the detailed structure of the n-type amorphous semiconductor layer 4 shown in FIG. However, FIG. 5 shows a structure in which the back surface of the semiconductor substrate 1 is flat and the n-type amorphous semiconductor layer 4 is formed on the flat passivation film 3 as in FIG. Actually, a texture structure is formed on the back surface of the semiconductor substrate 1.

  Referring to FIG. 5, n-type amorphous semiconductor layer 4 has a flat region FT and a film thickness reduction region TD in the in-plane direction of n-type amorphous semiconductor layer 4. The flat region FT is a portion of the n-type amorphous semiconductor layer 4 that has the thickest film thickness and is substantially constant.

  When the point at both ends of the flat region FT is A, and the point at which the film thickness decrease rate changes from the first decrease rate to the second decrease rate larger than the first decrease rate is B point, the film thickness The decrease region TD is a region from point A to point B in the in-plane direction of the n-type amorphous semiconductor layer 4.

  The film thickness reduction region TD is disposed on both sides of the flat region FT in the in-plane direction of the n-type amorphous semiconductor layer 4.

  The n-type amorphous semiconductor layer 4 has the reduced thickness region TD because the n-type amorphous semiconductor layer 4 is formed by plasma CVD using a shadow mask, as will be described later. Since the film thickness reduction region TD has a thinner film thickness than the flat region FT, the dopant concentration of the film thickness reduction region TD is higher than the dopant concentration of the flat region FT.

  The electrode 6 is disposed in contact with the entire flat region FT of the n-type amorphous semiconductor layer 4 and a part of the film thickness reduction region TD.

  The p-type amorphous semiconductor layer 5 also has the same structure as the n-type amorphous semiconductor layer 4 shown in FIG. The electrode 7 is disposed in contact with the entire flat region FT of the p-type amorphous semiconductor layer 5 and a part of the film thickness reduction region TD.

  As a result, the resistance when carriers (electrons) reach the electrode 6 through the n-type amorphous semiconductor layer 4 is n-type amorphous semiconductor layer having a constant film thickness in the in-plane direction of the passivation film 3. As compared with the case where is formed, the resistance becomes low. The resistance when carriers (holes) reach the electrode 7 through the p-type amorphous semiconductor layer 5 is a p-type amorphous semiconductor layer having a constant film thickness in the in-plane direction of the passivation film 3. As compared with the case where is formed, the resistance becomes low. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

  The electrode 6 may be in contact with the entire thickness reducing region TD of the n-type amorphous semiconductor layer 4, and the electrode 7 may be in contact with the entire thickness reducing region TD of the p-type amorphous semiconductor layer 5. You may touch.

  FIG. 6 is a cross-sectional view showing another detailed structure of the n-type amorphous semiconductor layer 4 shown in FIG. Referring to FIG. 6A, the photoelectric conversion element 10 includes an n-type amorphous semiconductor layer 41 instead of the n-type amorphous semiconductor layer 4, and includes an electrode 61 instead of the electrode 6. Also good.

  In the n-type amorphous semiconductor layer 41, the point at which the film thickness is maximum is C point, and the film thickness decrease rate changes from the first decrease rate to the second decrease rate larger than the first decrease rate. Let the point be point D. As a result, the film thickness reduction region TD is a region from the point C to the point D in the in-plane direction of the n-type amorphous semiconductor layer 41.

  The n-type amorphous semiconductor layer 41 has two thickness reduction regions TD in the in-plane direction of the n-type amorphous semiconductor layer 41. The two film thickness reduction regions TD are arranged in contact with each other in the in-plane direction of the n-type amorphous semiconductor layer 41.

  The electrode 61 is disposed in contact with a part of one film thickness reduction region TD and a part of the other film thickness reduction region TD among the two film thickness reduction regions TD.

  The photoelectric conversion element 10 includes a p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 41 shown in FIG. 6A instead of the p-type amorphous semiconductor layer 5. Also good.

  As a result, the resistance when carriers (electrons) reach the electrode 61 via the n-type amorphous semiconductor layer 41 is an n-type amorphous semiconductor layer having a constant film thickness in the in-plane direction of the passivation film 3. As compared with the case where is formed, the resistance becomes low. The resistance when carriers (holes) reach the electrode through the p-type amorphous semiconductor layer having the same structure as that of the n-type amorphous semiconductor layer 41 is constant in the in-plane direction of the passivation film 3. The resistance is lower than when a p-type amorphous semiconductor layer having a film thickness is formed. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

  The electrode is in contact with the whole of the two thickness reduction regions TD in the n-type amorphous semiconductor layer 41 and the p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 41. It may be arranged.

  With reference to FIG. 6B, the photoelectric conversion element 10 includes an n-type amorphous semiconductor layer 42 instead of the n-type amorphous semiconductor layer 4, and includes an electrode 62 instead of the electrode 6. Also good.

  In the n-type amorphous semiconductor layer 42, the point at which the film thickness is maximum is taken as point E, and the film thickness decrease rate changes from the first rate of decrease to a second rate of decrease that is greater than the first rate of decrease. Let the point be the F point, and let the point where the sign of the rate of change of the film thickness changes from negative to positive.

  As a result, the film thickness reduction region TD1 is a region from the point E to the point F in the in-plane direction of the n-type amorphous semiconductor layer 42, and the film thickness reduction region TD2 is the region of the n-type amorphous semiconductor layer 42. This is the region from point E to point G in the in-plane direction.

  The n-type amorphous semiconductor layer 42 has two film thickness reduction regions TD1 and two film thickness reduction regions TD2 in the in-plane direction of the n-type amorphous semiconductor layer 42.

  The two film thickness reduction regions TD2 are arranged so that the film thickness distribution in the in-plane direction of the n-type amorphous semiconductor layer 42 is symmetric with respect to a line passing through the G point. The two film thickness reduction regions TD1 are arranged on both sides of the two film thickness reduction regions TD2 in the in-plane direction of the n-type amorphous semiconductor layer 42.

  The electrode 62 is disposed in contact with the entire two film thickness reduction regions TD2, a part of one film thickness reduction region TD1, and a part of the other film thickness reduction region TD1.

  The photoelectric conversion element 10 includes a p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 42 shown in FIG. 6B instead of the p-type amorphous semiconductor layer 5. Also good.

  As a result, the resistance when carriers (electrons) reach the electrode 62 via the n-type amorphous semiconductor layer 42 is an n-type amorphous semiconductor layer having a constant thickness in the in-plane direction of the passivation film 3. As compared with the case where is formed, the resistance becomes low. The resistance when carriers (holes) reach the electrode through the p-type amorphous semiconductor layer having the same structure as that of the n-type amorphous semiconductor layer 42 is constant in the in-plane direction of the passivation film 3. The resistance is lower than when a p-type amorphous semiconductor layer having a film thickness is formed. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

  In addition, the electrode is composed of an n-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 42, the entire two thickness reduction regions TD 1, 2 Two film thickness reduction regions TD2 may be disposed in contact with the entirety.

  As described above, the photoelectric conversion element 10 includes the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer having the film thickness reduction region TD (TD1, TD2). In the embodiment of the present invention, the film thickness reduction region is one of the film thickness reduction regions TD, TD1, and TD2.

  Accordingly, the first point is the point where the film thickness of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer is the maximum, and the in-plane of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer In the direction, a point at which the film thickness decrease rate changes from the first decrease rate to a second decrease rate larger than the first decrease rate, or a point at which the sign of the film thickness change rate changes from negative to positive. When the second point is taken, the film thickness reduction region is a region from the first point to the second point in the in-plane direction of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer.

  In the embodiment of the present invention, it is sufficient that at least one of n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5 has a film thickness reduction region.

  7 to 11 are first to fifth process diagrams showing a method for manufacturing the photoelectric conversion element 10 shown in FIG. 1, respectively.

  Referring to FIG. 7, when manufacturing of photoelectric conversion element 10 is started, a wafer having a thickness of 100 to 300 μm is cut out from bulk silicon by a wire saw. Then, etching for removing the damaged layer on the surface of the wafer and etching for adjusting the thickness are performed to prepare a semiconductor substrate 1 '(see step (a) in FIG. 7).

  Generally, a semiconductor substrate having a textured structure is manufactured by etching a semiconductor substrate obtained by slicing a silicon ingot with a wire saw or the like. The semiconductor substrate that forms the texture structure is mainly the sliced substrate by the free abrasive grain method, but there is also a cost reduction and the improvement of the slicing technique, and the same texture structure can be formed also by the sliced substrate by the fixed abrasive grain method. .

Etching of the semiconductor substrate 1 ′ can be performed by wet etching using an alkaline etchant. This etching proceeds by a reaction such as the following reaction formulas (1), (2), and (3) in a sodium hydroxide solution.
Si + 2NaOH + H ₂ O → Na ₂ SiO ₃ + 2H ₂ (1)
2Si + 2NaOH + 3H ₂ O → Na ₂ Si ₂ O ₅ + 4H ₂ (2)
3Si + 4NaOH + 4H ₂ O → Na ₄ Si ₃ O ₈ + 6H ₂ (3)
In order to form a texture structure on the surface of the semiconductor substrate 1 ′, anisotropic etching is performed by using, for example, an etching solution with a controlled etching rate. Formation of the texture structure on the surface of the semiconductor substrate 1 ′ is based on the following mechanism. The etching rate of the semiconductor substrate 1 ′ with the alkaline aqueous solution is the fastest on the (100) plane of silicon and the slowest on the (111) plane. Therefore, if the etching rate is suppressed by adding a specific additive (hereinafter also referred to as “etching inhibitor”) that can reduce the etching rate to the alkaline aqueous solution, etching of the (100) surface of silicon and the like A crystal plane that is easily etched is preferentially etched, and a (111) plane having a slow etching rate remains on the surface. Since the (111) plane has an inclination of about 54 degrees with respect to the (100) plane, a pyramidal uneven structure composed of the (111) plane and its equivalent plane is formed at the final stage of the process. Is done.

  However, depending on the etching conditions, a texture having an inclination of about 40-54 degrees may be formed, and the inclined surface of the texture is not necessarily formed by the (111) plane. That is, the texture inclined surface does not have to be the (111) surface, and for example, the texture may have a gentle structure.

  As the texture forming etching solution, an etching solution obtained by adding isopropyl alcohol as an etching inhibitor to an aqueous solution of sodium hydroxide (NaOH) can be used. Etching is performed by heating the etching solution to about 60 to 80 ° C. and immersing the (100) plane semiconductor substrate for 10 to 30 minutes.

  In addition, by using an etching solution containing sodium hydroxide or potassium hydroxide, a specific additive such as lignin, and sodium hydrogen carbonate or potassium hydrogen carbonate, the texture structure of the micro pyramid structure (the bottom of the uneven recess) To 1 μm or less). Thus, the texture size can be controlled by changing various conditions such as the temperature of the etching solution, the processing time, the type of etching inhibitor, the etching rate, and the type of substrate.

  As described above, the etching conditions were changed to form irregularities with different texture sizes on the surface of the semiconductor substrate.

  FIG. 12 is a view showing an SEM (Scanning Electron Microscopy) photograph of a semiconductor substrate on which texture structures having different sizes are formed. FIG. 12A shows an SEM photograph in the case where the length of the bottom side of the pyramid constituting the texture structure is 2 μm or less, and FIG. 12B shows the length of the bottom side of the pyramid is 10 μm or less. FIG. 12 (c) shows an SEM photograph in the case where the bottom side length of the pyramid is about 15 μm.

  After the step (a) of FIG. 7, the semiconductor substrate 1 'is etched using an alkaline solution such as NaOH and KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%). As a result, both sides of the semiconductor substrate 1 ′ are anisotropically etched, and the semiconductor substrate 1 in which the pyramid-shaped texture structure is formed on both sides is obtained (see step (b) in FIG. 7).

  Subsequently, the surface of the semiconductor substrate 1 is thermally oxidized to form an oxide film 11 on the light receiving surface of the semiconductor substrate 1, and a passivation film 3 is formed on the back surface of the semiconductor substrate 1 (see step (c) in FIG. 7). .

  The oxidation of the semiconductor substrate 1 may be either wet processing or thermal oxidation. In the case of wet oxidation, for example, the semiconductor substrate 1 is immersed in hydrogen peroxide, nitric acid, ozone water or the like, and then the semiconductor substrate 1 is heated at 800 to 1000 ° C. in a dry atmosphere. In the case of thermal oxidation, for example, the semiconductor substrate 1 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor.

  After the step (c) of FIG. 7, a silicon nitride film 12 is formed in contact with the oxide film 11 using a sputtering method, EB (Electron Beam) vapor deposition, a CVD method, or the like. Thereby, the antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1 (see step (d) in FIG. 8).

  After the step (d) of FIG. 8, the semiconductor substrate 1 is put into the reaction chamber of the plasma apparatus, and the shadow mask 30 is disposed on the passivation film 3 of the semiconductor substrate 1 (see step (e) of FIG. 8).

  The shadow mask 30 is made of, for example, a metal mask. The metal mask is made of, for example, stainless steel, has a thickness of 200 μm, an opening width of 850 μm, a masked width of 1050 μm, and a period of 1900 μm.

Then, the temperature of the semiconductor substrate 1 is set to 130 to 180 ° C., and 0 to 100 sccm of hydrogen (H ₂ ) gas, 40 sccm of SiH ₄ gas, and 40 sccm of phosphine (PH ₃ ) gas are allowed to flow into the reaction chamber. Is set to 40 to 120 Pa. Thereafter, high frequency power (13.56 MHz) having an RF power density of 5 to 15 mW / cm ² is applied to the parallel plate electrodes. Note that the PH ₃ gas is diluted with hydrogen, and the concentration of the PH ₃ gas is, for example, 1%.

  As a result, n-type amorphous silicon is deposited in the region of the passivation film 3 that is not covered by the shadow mask 30, and the n-type amorphous semiconductor layer 4 is formed on the passivation film 3 (step of FIG. f)).

When the shadow mask 30 is disposed on the passivation film 3, there is a gap between the shadow mask 30 and the passivation film 3. As a result, active species such as SiH and SiH ₂ decomposed by the plasma enter the gap between the shadow mask 30 and the passivation film 3, and an n-type amorphous material is also formed in a part of the region covered by the shadow mask 30. A semiconductor layer 4 is formed. Compared to the case where the film is formed on the semiconductor substrate on which the texture structure is not formed, when the film is formed on the semiconductor substrate 1 on which the texture structure is formed, the gap between the shadow mask 30 and the passivation film 3 is reduced. More wraparound. As a result, the n-type amorphous semiconductor layer 4 having the thickness reduction region TD is formed on the passivation film 3. An n-type amorphous silicon 31 is also deposited on the shadow mask 30.

  The width of the film thickness reduction region TD and the film thickness reduction rate in the n-type amorphous semiconductor layer 4 are the film formation pressure when the n-type amorphous semiconductor layer 4 is formed, the thickness of the shadow mask 30 and It is controlled by changing the opening width of the shadow mask 30. For example, when the thickness of the shadow mask 30 is increased, the width of the film thickness reduction region TD is increased.

  After the step (f) in FIG. 8, a shadow mask 40 is disposed on the passivation film 3 and the n-type amorphous semiconductor layer 4 instead of the shadow mask 30 (see step (g) in FIG. 9). The shadow mask 40 has the same material, thickness, and opening width as the shadow mask 30.

  In the step (g) of FIG. 9, the shadow mask 40 is illustrated as being separated from the passivation film 3, but the thickness of the n-type amorphous semiconductor layer 4 is 3 as described above. Since it is very thin as ˜50 nm, the shadow mask 40 is actually arranged close to the passivation film 3.

Then, the temperature of the semiconductor substrate 1 is set to 130 to 180 ° C., and 0 to 100 sccm of H ₂ gas, 40 sccm of SiH ₄ gas, and 40 sccm of diborane (B ₂ H ₆ ) gas are flowed into the reaction chamber. The pressure is set to 40 to 200 Pa. Thereafter, high frequency power (13.56 MHz) having an RF power density of 5 to 15 mW / cm ² is applied to the parallel plate electrodes. Note that B ₂ H ₆ gas is diluted with hydrogen, and the concentration of B ₂ H ₆ gas is, for example, 2%.

  As a result, p-type amorphous silicon is deposited in the region of the passivation film 3 not covered by the shadow mask 40, and the p-type amorphous semiconductor layer 5 is formed on the passivation film 3 (step of FIG. 9). h)).

When the shadow mask 40 is disposed on the passivation film 3 and the n-type amorphous semiconductor layer 4, there is a gap between the shadow mask 40 and the passivation film 3. As a result, active species such as SiH and SiH ₂ decomposed by the plasma wrap around the gap between the shadow mask 40 and the passivation film 3, and p-type amorphous is also formed in a part of the region covered by the shadow mask 40. A semiconductor layer 5 is formed. Compared to the case where the film is formed on the semiconductor substrate on which the texture structure is not formed, when the film is formed on the semiconductor substrate 1 on which the texture structure is formed, the gap between the shadow mask 40 and the passivation film 3 is reduced. More wraparound. Thereby, the p-type amorphous semiconductor layer 5 having the film thickness reduction region TD is formed on the passivation film 3. Also, the p-type amorphous silicon 32 is deposited on the shadow mask 40.

  The width of the film thickness reduction region TD and the film thickness reduction rate in the p-type amorphous semiconductor layer 5 are the film formation pressure when the p-type amorphous semiconductor layer 5 is formed, the thickness of the shadow mask 40, and It is controlled by changing the opening width of the shadow mask 40. For example, when the thickness of the shadow mask 40 is increased, the width of the film thickness reduction region TD is increased.

  When the n-type amorphous semiconductor layer 4 is not provided with the film thickness reduction region TD, for example, the n-type amorphous semiconductor layer 4 is not formed on the entire upper surface of the passivation film 3 without the shadow mask 30 being disposed. The semiconductor layer 4 is formed, and the n-type amorphous semiconductor layer 4 is formed in a predetermined region by etching. Even when the p-type amorphous semiconductor layer 5 is not provided with the film thickness reduction region TD, it can be formed by the same method.

  When the shadow mask 40 is removed after the p-type amorphous semiconductor layer 5 is deposited, the n-type amorphous semiconductor layers 4 and the p-type amorphous semiconductor layers 5 arranged alternately in the in-plane direction of the semiconductor substrate 1. Is formed on the passivation film 3 (see step (i) in FIG. 9).

  After the step (i) in FIG. 9, the shadow mask 50 is arranged so that the opening is located on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 (step (j) in FIG. 10). reference). The shadow mask 50 has the same material and thickness as the shadow mask 30. The opening width is set to the sum of the width of the flat region FT of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 and the width of the two film thickness reduction regions TD. The opening width may be slightly different from the above width.

  After step (j) in FIG. 10, conductive layers 6 a and 7 a and conductive layers 6 b and 7 b are sequentially deposited through a shadow mask 50. As a result, the electrodes 6 and 7 are deposited on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively (see step (k) in FIG. 10).

  The conductive layers 6a and 7a and the conductive layers 6b and 7b are formed by a sputtering method, a vapor deposition method, an ion plating method, a thermal CVD method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, a sol-gel method, or a method of spraying and heating a liquefied raw material. , And an inkjet method or the like.

  The conductive layers 6a and 7a are, for example, any one of ITO, IWO, and ZnO, and the conductive layers 6b and 7b have a two-layer structure of Ti (3 nm) / Al (500 nm).

ITO, for example, an ITO target doped with SnO ₂ in an amount of 0.5 to 4 wt% is supplied with an argon gas or a mixed gas of an argon gas and an oxygen gas, and a substrate temperature of 25 to 250 ° C., 0.1 to 1.5 Pa. It is formed by performing the sputtering process at a pressure of 0.01 to 2 kW.

  ZnO is formed by performing sputtering treatment under the same conditions using a ZnO target doped with 0.5 to 4 wt% of Al instead of the ITO target.

  A two-layer structure of Ti / Al is formed by EB vapor deposition.

  In addition, the electrodes 6 and 7 may be formed by forming the conductive layers 6b and 7b by plating film formation using the conductive layers 6a and 7a as seed electrodes, respectively. In this case, the conductive layers 6b and 7b are made of, for example, any one of Ni, W, Co, Ti, Cr, alloys thereof, and alloys of these alloys with P and B. Also, Cu, Al, Sn, etc. can be formed on the conductive layers 6b, 7b by plating.

  After step (k) in FIG. 10, a shadow mask 60 is placed on the electrodes 6 and 7 (see step (l) in FIG. 10). The shadow mask 60 has the same material and thickness as the shadow mask 30.

  Then, the protective film 8 is formed on the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7.

More specifically, an intrinsic amorphous semiconductor film and a silicon nitride film are formed from the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7 using plasma CVD. Deposit sequentially on top. In this case, for example, an intrinsic amorphous semiconductor film is formed using SiH ₄ gas as a material gas, and the thickness of the intrinsic amorphous semiconductor film is, for example, 10 nm. Further, for example, a silicon nitride film is formed using SiH ₄ gas and NH ₃ gas as material gases, and the thickness of the silicon nitride film is, for example, 120 nm. Thus, the photoelectric conversion element 10 is completed (see step (m) in FIG. 11).

  In the above description, stainless steel is given as an example of the material of the shadow masks 30, 40, 50, 60. However, the material is not limited to stainless steel. For example, copper, nickel, nickel alloy (42 alloy, Invar material) Etc.) or molybdenum.

  Further, the shadow masks 30, 40, 50, 60 need not be metal masks, and may be glass masks, ceramic masks, organic film masks, or the like.

  Alternatively, a semiconductor substrate made of the same material as the semiconductor substrate 1 may be processed by etching to form a shadow mask. In this case, since both the semiconductor substrate 1 and the shadow mask are made of the same material, the thermal expansion coefficients are the same, and no misalignment occurs due to the difference in thermal expansion coefficients.

  Considering the relationship with the thermal expansion coefficient of the semiconductor substrate 1 and the raw material cost, the material of the shadow masks 30, 40, 50, 60 is preferably 42 alloy. Focusing on the relationship with the thermal expansion coefficient of the semiconductor substrate 1, when the composition of nickel is about 36% and the composition of iron is about 64% as the material of the shadow masks 30, 40, 50, 60, It is closest to the thermal expansion coefficient, and the alignment error due to the difference in thermal expansion coefficient can be minimized.

  Moreover, regarding the thickness of the shadow mask 30, 40, 50, 60, it is preferable that it can be regenerated and used many times from the viewpoint of suppressing the running cost of production. In this case, the film deposited on the shadow mask 30, 40, 50, 60 can be removed using hydrofluoric acid or NaOH. Considering the number of times of reproduction, the thickness of the shadow masks 30, 40, 50, 60 is preferably 30 μm to 300 μm.

  Further, in the manufacturing method described above, it has been described that the intrinsic amorphous semiconductor film / silicon nitride film constituting the protective film 8 is continuously formed in one reaction chamber, but in the embodiment of the present invention, However, the present invention is not limited thereto, and after the intrinsic amorphous semiconductor layer is formed, the sample may be exposed to the atmosphere once so that a silicon nitride film is formed by a sputtering apparatus or another CVD apparatus.

  When the intrinsic amorphous semiconductor film / silicon nitride film constituting the protective film 8 is formed without being exposed to the atmosphere, it is preferable because contamination of organic substances or moisture in the atmosphere can be suppressed.

  Furthermore, the protective film 8 may be formed using EB vapor deposition, sputtering, laser ablation, CVD, and ion plating.

Furthermore, in the embodiment of the present invention, after the passivation film 3 is formed, the passivation film 3 may be nitrided by a plasma CVD method using nitrogen (N ₂ ) gas to form a passivation film made of SiON. . As a result, it is possible to suppress the diffusion of the dopant (B) in the p-type amorphous semiconductor layer 5 formed on the passivation film 3 into the semiconductor substrate 1. And even if it is a case where the passivation film 3 which has the film thickness which can flow a tunnel current is formed, since the spreading | diffusion of boron (B) can be suppressed effectively, it is preferable.

  As described above, since the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are deposited on the semiconductor substrate 1 using the shadow masks 30 and 40, adjacent n-type amorphous semiconductors are deposited. A gap region G is formed between the layer 4 and the p-type amorphous semiconductor layer 5. A protective film 8 is formed between the adjacent electrodes 6 and 7 on the electrodes 6 and 7 and the gap region G (passivation film 3, n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5). The

  As a result, even when conductive dust adheres between the adjacent electrodes 6 and 7, a short circuit is prevented.

  Therefore, the reliability of the photoelectric conversion element 10 can be improved.

  Further, the electrodes 6 and 7 are covered with a protective film 8 in a region of 5 μm or more from the end toward the inside. As a result, it is possible to effectively prevent moisture from entering from the opening end of the protective film 8, and to prevent the protective film 8 from peeling off, thereby preventing a decrease in yield due to misalignment during production.

  In addition, even when an electric material having poor adhesion between the electrodes 6 and 7 and the amorphous semiconductor layers 4 and 5 in contact with the electrodes 6 and 7 is used, by forming the protective film 8, Improves. For this reason, the range of electrode metal selection is widened, and it becomes easy to improve the characteristics.

  In a conventional heterojunction solar cell in which an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer and a TCO (transparent conductive film) are formed on almost the entire surface of a substrate surface, the amorphous semiconductor layer, the TCO, There is no break between. However, when a plurality of layers such as an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer, a TCO, and an electrode are alternately formed as in the backside heterojunction solar cell in this embodiment, FIG. As shown, a large number of end portions of each layer are generated. When a peel test or the like is performed with such a configuration, there is a possibility of peeling from the end. However, it is preferable to form a texture structure on the surface of the semiconductor substrate 1 because an anchor effect is generated and peeling and the like are easily suppressed. Further, it is more preferable that the electrode end portion that is most easily peeled off is covered with a protective film, whereby peeling can be more effectively suppressed.

  Furthermore, in the gap region G, the passivation film 3, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are covered with a protective film 8. As a result, an effect of long-term stability of the photoelectric conversion element 10 can be obtained.

  FIG. 13 is a plan view seen from the back side of the photoelectric conversion element 10 shown in FIG. Referring to (a) of FIG. 13, n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5 are alternately arranged at desired intervals in the in-plane direction of semiconductor substrate 1. Electrodes 6 and 7 are disposed on n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5, respectively. As a result, a gap region G is formed between the adjacent electrodes 6 and 7.

  Referring to FIG. 13B, the protective film 8 is disposed on the gap region G and the peripheral region of the semiconductor substrate 1. On the electrodes 6 and 7, an opening 8A having a width L is formed. The electrodes 6 and 7 are connected to the wiring sheet through the opening 8A.

  In FIG. 13B, a region that is not covered with the protective film 8 exists in the peripheral portion of the semiconductor substrate 1, but in the photoelectric conversion element 10, the entire back surface of the semiconductor substrate 1 is protected. Most preferably, the film is covered with a film and a part of the electrodes 6 and 7 is exposed.

  FIG. 14 is a plan view of the wiring sheet. Referring to FIG. 14, the wiring sheet 70 includes an insulating base 710 and wiring members 71 to 87.

  The insulating base material 710 may be an electrically insulating material and can be used without any particular limitation. The insulating base 710 is made of, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyvinyl fluoride (PVF), polyimide, and the like.

  The thickness of the insulating base 710 is not particularly limited, but is preferably 25 μm or more and 150 μm or less. The insulating base 710 may have a single layer structure or a multilayer structure of two or more layers.

  The wiring member 71 includes a bus bar portion 711 and finger portions 712. One end of the finger portion 712 is connected to the bus bar portion 711.

  The wiring member 72 includes a bus bar portion 721 and finger portions 722 and 723. One end of the finger portion 722 is connected to the bus bar portion 721. One end of the finger portion 723 is connected to the bus bar portion 721 on the opposite side of the connection portion between the bus bar portion 721 and the finger portion 722 with respect to the bus bar portion 721.

  The wiring member 73 includes a bus bar portion 731 and finger portions 732 and 733. One end of the finger portion 732 is connected to the bus bar portion 731. One end of the finger portion 733 is connected to the bus bar portion 731 on the opposite side of the connection portion between the bus bar portion 731 and the finger portion 732 with respect to the bus bar portion 731.

  The wiring member 74 includes a bus bar portion 741 and finger portions 742 and 743. One end of the finger portion 742 is connected to the bus bar portion 741. One end of the finger portion 743 is connected to the bus bar portion 741 on the opposite side of the connection portion between the bus bar portion 741 and the finger portion 742 with respect to the bus bar portion 741.

  The wiring member 75 includes a bus bar portion 751 and finger portions 752 and 753. The finger portions 752 and 753 are arranged adjacent to each other in the length direction of the bus bar portion 751, and one end thereof is connected to the bus bar portion 751 on the same side of the bus bar portion 751.

  The wiring member 76 includes a bus bar portion 761 and finger portions 762 and 763. One end of the finger portion 762 is connected to the bus bar portion 761. One end of the finger part 763 is connected to the bus bar part 761 on the opposite side of the connection part between the bus bar part 761 and the finger part 762 with respect to the bus bar part 761.

  The wiring member 77 has a bus bar portion 771 and finger portions 772 and 773. One end of finger portion 772 is connected to bus bar portion 771. One end of the finger portion 773 is connected to the bus bar portion 771 on the opposite side of the connection portion between the bus bar portion 771 and the finger portion 772 with respect to the bus bar portion 771.

  The wiring member 78 includes a bus bar portion 781 and finger portions 782 and 783. One end of the finger portion 782 is connected to the bus bar portion 781. One end of the finger portion 783 is connected to the bus bar portion 781 on the opposite side of the connection portion between the bus bar portion 781 and the finger portion 782 with respect to the bus bar portion 781.

  The wiring member 79 includes a bus bar portion 791 and finger portions 792 and 793. Finger portions 792 and 793 are arranged adjacent to each other in the length direction of bus bar portion 791, and one end thereof is connected to bus bar portion 791 on the same side of bus bar portion 791.

  The wiring member 80 includes a bus bar portion 801 and finger portions 802 and 803. One end of the finger portion 802 is connected to the bus bar portion 801. One end of the finger part 803 is connected to the bus bar part 801 on the opposite side of the connection part between the bus bar part 801 and the finger part 802 with respect to the bus bar part 801.

  The wiring member 81 has a bus bar portion 811 and finger portions 812 and 813. One end of the finger portion 812 is connected to the bus bar portion 811. One end of the finger portion 813 is connected to the bus bar portion 811 on the opposite side of the connection portion between the bus bar portion 811 and the finger portion 812 with respect to the bus bar portion 811.

  The wiring member 82 includes a bus bar portion 821 and finger portions 822 and 823. One end of the finger portion 822 is connected to the bus bar portion 821. One end of the finger part 823 is connected to the bus bar part 821 on the opposite side of the connection part between the bus bar part 821 and the finger part 822 with respect to the bus bar part 821.

  The wiring member 83 includes a bus bar portion 831 and finger portions 832 and 833. Finger portions 832 and 833 are arranged adjacent to each other in the length direction of bus bar portion 831, and one end thereof is connected to bus bar portion 831 on the same side of bus bar portion 831.

  The wiring member 84 includes a bus bar portion 841 and finger portions 842 and 843. One end of the finger portion 842 is connected to the bus bar portion 841. One end of the finger portion 843 is connected to the bus bar portion 841 on the opposite side of the connection portion between the bus bar portion 841 and the finger portion 842 with respect to the bus bar portion 841.

  The wiring member 85 has a bus bar portion 851 and finger portions 852 and 853. One end of the finger portion 852 is connected to the bus bar portion 851. One end of the finger portion 853 is connected to the bus bar portion 851 on the opposite side of the connection portion between the bus bar portion 851 and the finger portion 852 with respect to the bus bar portion 851.

  The wiring member 86 has a bus bar portion 861 and finger portions 862 and 863. One end of the finger portion 862 is connected to the bus bar portion 861. One end of the finger portion 863 is connected to the bus bar portion 861 on the opposite side of the connection portion between the bus bar portion 861 and the finger portion 862 with respect to the bus bar portion 861.

  The wiring member 87 has a bus bar portion 871 and finger portions 872. One end of the finger portion 872 is connected to the bus bar portion 871.

  The wiring member 71 is disposed on the insulating base 710 so that the finger portion 712 meshes with the finger portion 722 of the wiring member 72.

  The wiring member 72 is disposed on the insulating base 710 such that the finger portion 722 is engaged with the finger portion 712 of the wiring member 71 and the finger portion 723 is engaged with the finger portion 732 of the wiring member 73.

  The wiring member 73 is disposed on the insulating base 710 so that the finger portion 732 engages with the finger portion 723 of the wiring member 72 and the finger portion 733 engages with the finger portion 742 of the wiring member 74.

  The wiring member 74 is disposed on the insulating base 710 so that the finger portion 742 engages with the finger portion 733 of the wiring member 73 and the finger portion 743 engages with the finger portion 752 of the wiring member 75.

  The wiring member 75 is disposed on the insulating base 710 so that the finger portions 752 are engaged with the finger portions 743 of the wiring member 74 and the finger portions 753 are engaged with the finger portions 762 of the wiring member 76.

  The wiring member 76 is disposed on the insulating base 710 so that the finger portion 762 engages with the finger portion 753 of the wiring member 75 and the finger portion 763 engages with the finger portion 772 of the wiring member 77.

  The wiring member 77 is disposed on the insulating substrate 710 so that the finger portions 772 mesh with the finger portions 763 of the wiring material 76 and the finger portions 773 mesh with the finger portions 782 of the wiring material 78.

  The wiring member 78 is disposed on the insulating base 710 such that the finger portions 782 mesh with the finger portions 773 of the wiring material 77 and the finger portions 783 mesh with the finger portions 792 of the wiring material 79.

  The wiring member 79 is disposed on the insulating base 710 so that the finger portions 792 mesh with the finger portions 783 of the wiring material 78 and the finger portions 793 mesh with the finger portions 802 of the wiring material 80.

  The wiring member 80 is disposed on the insulating base 710 so that the finger portion 802 is engaged with the finger portion 793 of the wiring member 79 and the finger portion 803 is engaged with the finger portion 812 of the wiring member 81.

  The wiring member 81 is disposed on the insulating base 710 so that the finger portion 812 is engaged with the finger portion 803 of the wiring member 80 and the finger portion 813 is engaged with the finger portion 822 of the wiring member 82.

  The wiring member 82 is disposed on the insulating base 710 so that the finger portion 822 is engaged with the finger portion 813 of the wiring member 81 and the finger portion 823 is engaged with the finger portion 832 of the wiring member 83.

  The wiring member 83 is disposed on the insulating base 710 so that the finger portion 832 is engaged with the finger portion 823 of the wiring member 82 and the finger portion 833 is engaged with the finger portion 842 of the wiring member 84.

  The wiring member 84 is disposed on the insulating base 710 so that the finger portion 842 is engaged with the finger portion 833 of the wiring member 83 and the finger portion 843 is engaged with the finger portion 852 of the wiring member 85.

  The wiring member 85 is disposed on the insulating base 710 such that the finger portion 852 is engaged with the finger portion 843 of the wiring member 84 and the finger portion 853 is engaged with the finger portion 862 of the wiring member 86.

  The wiring member 86 is disposed on the insulating substrate 710 so that the finger portion 862 is engaged with the finger portion 853 of the wiring member 85 and the finger portion 863 is engaged with the finger portion 872 of the wiring member 87.

  The wiring member 87 is disposed on the insulating base 710 so that the finger portion 872 meshes with the finger portion 863 of the wiring member 86.

  Each of the wiring members 71 to 87 is not particularly limited as long as it is electrically conductive. Each of the wiring members 71 to 87 is made of, for example, Cu, Al, Ag, and an alloy containing these as main components.

  In addition, the thickness of the wiring members 71 to 87 is not particularly limited, but is preferably 10 μm or more and 80 μm or less, for example. If it is less than 10 μm, the wiring resistance becomes high, and if it exceeds 80 μm, the silicon substrate is warped due to the difference in thermal expansion coefficient between the wiring material and the silicon substrate due to the heat applied when the photoelectric conversion element 10 is bonded. Occur.

  The shape of the insulating substrate 710 is not limited to the shape shown in FIG. 14 and can be changed as appropriate. Moreover, you may form electroconductive materials, such as Ni, Au, Pt, Pd, Sn, In, and ITO, in a part of surface of the wiring materials 71-87. As described above, the conductive material such as Ni is formed on a part of the surface of the wiring members 71 to 87 because the electrical connection between the wiring members 71 to 87 and the electrodes 6 and 7 of the photoelectric conversion element 10 is good. This is to improve the weather resistance of the wiring members 71 to 87. Furthermore, the wiring members 71 to 87 may have a single layer structure or a multilayer structure.

  The photoelectric conversion element 10 is arranged on the region REG1 so that the electrode 6 is connected to the finger part 712 of the wiring member 71 and the electrode 7 is connected to the finger part 722 of the wiring member 72, and the electrode 6 is a finger of the wiring member 72. The photoelectric conversion element 10 is disposed on the region REG <b> 2 so that the electrode 7 is connected to the finger portion 732 of the wiring member 73. Hereinafter, the photoelectric conversion element 10 is similarly arranged on the wiring members 73 to 87. Thereby, the 16 photoelectric conversion elements 10 are connected in series.

  The electrodes 6 and 7 of the photoelectric conversion element 10 are connected to the wiring members 71 to 87 by an adhesive. Examples of the adhesive include solder resin, solder, conductive adhesive, thermosetting Ag paste, low temperature curing copper paste, anisotropic conductive film (ACF), anisotropic conductive paste (ACP). It consists of 1 or more types of adhesives selected from the group which consists of Conductive Paste) and an insulating adhesive agent (NCP: Non Conductive Paste).

  For example, TCAP-5401-27 manufactured by Tamura Kaken Co., Ltd. can be used as the solder resin.

  As the insulating adhesive, an epoxy resin, an acrylic resin, a urethane resin, or the like can be used, and a thermosetting resin or a photocurable resin can be used.

  As the conductive adhesive, solder particles containing at least one of tin and bismuth can be used. More preferably, the conductive adhesive is an alloy of tin and bismuth, indium, silver or the like. As a result, the melting point of the solder can be suppressed, and an adhesion process at a low temperature becomes possible.

  When using the photoelectric conversion element 10 in which the protective film 8 is formed on the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6, 7, the inorganic insulating film on the electrodes 6, 7 , There are inorganic insulating films on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and these two inorganic insulating films have different bases. And in the photoelectric conversion element 10, the inorganic insulating film from which a foundation | substrate differs is formed continuously. In such a situation, when a thermal history is applied to an inorganic insulating film having a different base, peeling of the inorganic insulating film may occur due to a difference in thermal expansion coefficient of the base.

  Therefore, a low temperature, particularly a heat process of 200 ° C. or lower is preferable, and as a result, a thermosetting Ag paste, a low temperature curable copper paste, an anisotropic conductive film and an anisotropic conductive film that can be cured and electrically bonded at a low temperature. A paste is particularly preferred.

  As described above, the photoelectric conversion element 10 disposed on the wiring sheet 70 is disposed between the ethylene vinyl acetate resin (EVA resin) disposed on the glass substrate and the EVA resin disposed on the PET film. . Then, the EVA resin on the glass substrate side is pressure-bonded to the photoelectric conversion element 10 by vacuum pressure bonding using a laminator device, and the EVA resin on the PET film side is pressure-bonded to the photoelectric conversion element 10 and heated to 125 ° C. to be cured. I let you. Thereby, a solar cell module can be produced by sealing the photoelectric conversion element 10 with the wiring sheet 70 in the EVA resin cured between the glass substrate and the PET film.

[Insulation]
In the photoelectric conversion element 10, the solar cell module provided with the photoelectric conversion element 10 when changing the width | variety of the gap area | region G, the pitch X between the adjacent opening parts 8A, and the opening width L of the opening part 8A was created. When the protective film 8 is not provided, a fine conductor such as dust adheres to the gap region G when the wiring sheet and the photoelectric conversion element are bonded, and the electrode connected to the n-type amorphous semiconductor layer 4 6 and the electrode 7 connected to the p-type amorphous semiconductor layer 5 were short-circuited, and the yield was found to be as low as 70%.

  Thus, when the width of the gap region G between the electrode 6 and the electrode 7 is narrowed, the yield is reduced due to a short circuit. The decrease in the yield after modularizing the photoelectric conversion element is a final step in the process process, so that the loss in money increases, which is a problem.

  On the other hand, when the photoelectric conversion element 10 in which the protective film 8 is formed is used, the yield of the solar cell module exceeds 90%, and the decrease in the yield due to the short circuit between the electrodes, which is the problem described above, I couldn't see it. And it turned out that the short circuit between electrodes can be suppressed by having the protective film 8. FIG.

  In view of ensuring insulation, the thickness of the inorganic insulating film is preferably 20 nm or more, and more preferably 40 nm or more. A thick film of 1 μm or more is not preferable because the inorganic insulating film may be peeled off due to the internal stress of the inorganic insulating film on the electrode.

  In the opening 8A of the protective film 8, the underlying electrodes 6 and 7 are exposed, and the electrodes 6 and 7 are connected to the wiring material by the adhesive described above. For this reason, when the opening 8A is narrow, the contact resistance increases, so the width L of the opening 8A needs to be 20 μm or more, and more preferably 100 μm or more. Usually, the electrodes 6 and 7 shown in FIG. 1 have a width of 200 μm or more. The width L of the opening 8A is smaller than the width of the electrodes 6 and 7. In consideration of the connection between the electrodes 6 and 7 and the wiring material, the opening 8A is preferably on the electrodes 6 and 7. That is, the width L of the opening 8A is 20 μm or more, preferably narrower than the width of the electrodes 6 and 7, and the opening 8A is preferably on the electrodes 6 and 7.

  Furthermore, when the width of the electrode 6 is compared with the width of the electrode 7, it is preferable that the width of the opening 8A on the narrow electrode (any one of the electrodes 6 and 7) is wide. By setting in this way, an increase in contact resistance can be suppressed.

[Moisture resistance]
FIG. 15 is a diagram showing the results of a moisture-proof resistance test. Referring to FIG. 15, i represents intrinsic amorphous silicon, i / n represents a laminated film of intrinsic amorphous silicon and n-type amorphous silicon, and i / SiN represents intrinsic amorphous silicon. It represents a laminated film of silicon and silicon nitride.

I / n / SiN represents a laminated film of intrinsic amorphous silicon, n-type amorphous silicon and silicon nitride, and i / SiON represents a laminated film of intrinsic amorphous silicon and silicon oxynitride. I / SiO ₂ represents a laminated film of intrinsic amorphous silicon and silicon dioxide, and i / TiO ₂ represents a laminated film of intrinsic amorphous silicon and titanium dioxide.

In addition, an i layer such as n / SiN, n / SiON, n / SiO ₂ , or n / TiO ₂ may be replaced with an n layer.

Note that the concentration of P in the n-type amorphous silicon is 1 × 10 ²⁰ cm ⁻³ .

  An amorphous semiconductor film shown in FIG. 15 was formed on a silicon substrate, and immediately after the film formation, the minority carrier lifetime of the sample was measured using a μPCD (microwave Photo Conductivity Decay) method. In the μPCD method, a state in which carriers are induced in the semiconductor layer by irradiating the surface of the semiconductor layer with laser light and a state in which the induced carriers disappear by irradiating the laser light are created. Measure time. In order to measure the amount of carriers, the surface of the semiconductor layer is irradiated with microwaves, and the reflectance of the microwaves is measured.

  Thereafter, after 3 days and 8 days, the lifetime of minority carriers was measured under the same conditions as described above.

  In FIG. 15, the lifetime normalized by the lifetime immediately after film formation is shown.

As shown in FIG. 15, in an amorphous semiconductor film such as amorphous silicon, moisture (H ₂ O, OH group, etc.) from the atmosphere is diffused, so that the lifetime after 3 days and after 8 days is as follows. Compared to immediately after the film, it is greatly reduced by about 30 to 50% (see Sample 1 to Sample 4).

  This is due to the following reason. An amorphous film has a lower film density than a single crystal film having the same composition, and includes many voids in the film. The reason why the refractive index of the amorphous film is lower than that of the crystal is that there are many voids, and the existence of voids is related to moisture resistance, and it is difficult to obtain an effect when the film thickness is thin. it is conceivable that. When the film thickness is about several nanometers to 30 nm, it is considered that moisture from the outside is absorbed by the amorphous semiconductor layer and the passivation property of the crystalline silicon interface is lowered.

On the other hand, when any one of SiN, SiON, and SiO ₂ is formed on the amorphous semiconductor layer, the lifetime after 3 days and after 8 days is maintained as the lifetime immediately after the film formation. When TiO ₂ is formed thereon, the lifetime after 3 days and after 8 days is only about 10% lower than the lifetime immediately after film formation (see Sample 5 to Sample 9).

  Thus, it was found that by forming an inorganic insulating film (SiN or the like) on the amorphous semiconductor layer, the above moisture absorption can be suppressed and the lifetime can be prevented from decreasing.

  When a thermal oxide film (2 nm) is formed on the silicon substrate, the lifetime is about 40% lower than that immediately after the film formation after 8 days. Therefore, it was found that covering the surface of the silicon substrate with intrinsic amorphous silicon is important for suppressing the decrease in lifetime (see Sample 5 to Sample 10).

  As described above, it has been found that by forming an inorganic insulating film on the amorphous semiconductor layer, moisture resistance can be ensured and a change in the passivation property with time can be suppressed.

  From such knowledge, electrical insulation and moisture resistance can be realized by adopting a structure in which an inorganic insulating film is formed on an amorphous semiconductor layer.

  Therefore, by adopting an inorganic insulating film as the protective film 8, the formation of the protective film 8 in the combination with the passivation film 3, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is performed on the electrode 6. , 7 can be prevented, the moisture resistance in the gap region G can be improved, and the passivation can be improved at the same time.

  In addition, it is preferable to form the protective film 8 with a two-layer structure in which an inorganic insulating film is formed on an amorphous semiconductor layer, since electrical insulation and moisture resistance can be realized.

  The thickness of the inorganic insulating film is preferably 20 nm or more in consideration of moisture resistance, and is preferably 10 nm or more for a silicon nitride film or silicon oxynitride film having high moisture resistance.

  Since the metal electrodes and / or the TCO electrodes are formed in the regions where the electrodes 6 and 7 are formed, these ensure moisture resistance, so that the openings of the protective film 8 on the metal electrodes or the TCO electrodes Moisture resistance can be secured for 8A.

  Since the protective film 8 is formed so as to cover a part of the electrodes 6 and 7 similarly to the gap region G, the surface of the electrodes 6 and 7 below the protective film 8 is covered by the protective film 8. It is protected and can prevent oxidation and discoloration of the surface. As a result, the long-term reliability of the electrodes 6 and 7 can be secured, which is preferable.

  Thus, it is preferable that the protective film 8 is formed on the electrodes 6 and 7 and the gap region G in order to improve insulation and moisture resistance. The protective film on the electrodes 6 and 7 and the protective film on the gap region G do not necessarily have to be continuous films, but forming them as continuous films can reduce the number of process steps and the film quality is also constant. And more uniform.

  It has been found that the moisture-proof effect described above can also be obtained on the surface of the semiconductor substrate 1 on which the texture is formed.

[Heat-resistant]
As described above, when the photoelectric conversion element 10 is modularized, there is a step of bonding the photoelectric conversion element 10 and the wiring sheet 70 using a conductive adhesive or an insulating adhesive, which is about 180 ° C. for about 20 minutes. There is a heating process.

  When the thermal history at 180 ° C. for 20 minutes is entered, the gap region G and the gap region G when the protective film 8 is present on the amorphous semiconductor layer around the wafer and when the protective film 8 is not present. , And the lifetime of minority carriers in the periphery of the wafer.

  When the protective film 8 does not exist on the amorphous semiconductor layer, the lifetime of minority carriers, which is usually about 2400 μs, decreased to 700 μs.

  On the other hand, when the protective film 8 is present on the amorphous semiconductor layer, the lifetime of minority carriers has been reduced to 2000 μs.

  Thus, it has been found that the presence of the protective film 8 also in the gap region G and the wafer peripheral portion can suppress a decrease in the minority carrier lifetime of the entire wafer.

  In addition, since an inorganic insulating film (protective film 8) is also present on the electrodes 6 and 7, and the electrodes 6 and 7 help to dissipate heat from the inorganic insulating film, a more favorable effect is obtained with respect to heat resistance. .

  It has been found that the heat resistance effect described above can be obtained even on the surface of the semiconductor substrate 1 on which the texture is formed.

[Adhesion of protective film]
When the protective film 8 was formed on the surface of the semiconductor substrate 1 on which the texture was formed, the effect of improving the adhesion of the protective film 8 was confirmed. The protective film 8 includes a portion formed on the electrodes 6 and 7 and a portion formed in the gap region G, and peeling may occur depending on the selection and combination of the underlying material. However, when the protective film 8 is formed on the surface on which the texture is formed, the effect of significantly improving the adhesion is seen even with a combination with a base that peels off. In a simple peel test, even if the surface is peeled off on a flat surface on which no texture is formed, the protective film 8 is formed on the surface on which the texture is formed. These contribute to the long-term reliability of the photoelectric conversion element 10.

[Electrode floating]
Compared to the photoelectric conversion element 10 of the present embodiment in which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are patterned on the textured surface, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed on the semiconductor substrate on which no texture is formed. A comparative photoelectric conversion element in which the amorphous semiconductor layer and the p-type amorphous semiconductor layer were patterned was produced. About these two photoelectric conversion elements, the temperature was raised to 150 ° C., 170 ° C., 190 ° C., and 210 ° C. and heated at the respective temperatures for 10 minutes in each atmosphere, and the lifting of the electrodes was observed.

  In the observation of the electrode lifting, a photoelectric conversion element in which a silver electrode was directly formed on the amorphous semiconductor layer was used as the electrodes 6 and 7. In the photoelectric conversion element of the comparative example patterned on the flat surface where the texture was not formed, the electrode 7 was lifted when heated at 190 ° C., but this embodiment provided with the semiconductor substrate 1 on which the texture was formed In the photoelectric conversion element 10 of the form, no lifting of the electrode was observed. The film formation conditions of the amorphous semiconductor layer are the same in any of the photoelectric conversion elements, but the (111) plane or a surface with a plane orientation close thereto is formed on the textured surface of the semiconductor substrate 1. It is thought that the results are different due to the change in the film quality.

  On the (100) plane of the semiconductor substrate, two dangling bonds of silicon appear on the outermost surface, whereas on the (111) plane where the texture is formed, there is one dangling bond. Due to the difference in the number of dangling bonds, the passivation property of the semiconductor substrate surface and the film quality of the formed amorphous semiconductor layer, such as the amount of hydrogen, oxygen and nitrogen in the film, also change. It is thought that the state of changes.

  Even in the configuration of the photoelectric conversion element of the comparative example, it is considered that there is no problem with electrode floating. However, according to the configuration of the photoelectric conversion element 10 in the present embodiment, the electrode floating can be suppressed even when heated at a high temperature. Therefore, in consideration of the yield and the like, the configuration in which the texture is formed on the semiconductor substrate is more preferable.

  This electrode floating was found to correlate with the texture inclination angle for the above reason. As shown in FIG. 16, the texture inclination angle is, for example, an angle θ formed between the (100) plane surface and the texture inclination plane (111) plane in the case of a (100) plane semiconductor substrate. It becomes.

  The angle θ may deviate from a theoretical value of 54.7 degrees to a smaller angle depending on etching conditions and the like. It has been found that the yield of electrode floating is improved when the angle θ is 30 degrees or more. The angle θ is preferably 40 degrees or more. When the electrode floats, the contact resistance increases, leading to peeling of the electrode and lowering the reliability. According to the configuration in which the texture is formed on the semiconductor substrate like the photoelectric conversion element 10 of the present embodiment, since the electrode floating can be suppressed even when heated at a high temperature, the degree of freedom of the process in the modularization process is increased. More preferred.

[Influence of wraparound]
FIG. 17 is a diagram for explaining that when the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are patterned, the semiconductor layer and the dopant wrap around under the shadow mask. FIG. 17A is a view when the amorphous semiconductor layer 161 is patterned on the semiconductor substrate 1 on which the texture is formed, and FIG. 17B is a flat semiconductor substrate on which the texture is not formed. It is a figure at the time of patterning the amorphous semiconductor layer 161a.

  In both cases where the texture is formed on the semiconductor substrate and when the texture is not formed, the amorphous semiconductor is formed by Δd inward in the in-plane direction from the end Z of the shadow mask 160 below the shadow mask 160. It was found that the layer 161 and the dopant wrap around.

  When the semiconductor substrate 1a shown in FIG. 17B is a flat surface, the flatness of the surface is high and there are only 1 nm irregularities, so that the gap between the shadow mask 160a and the semiconductor substrate 1a can be very narrow. This makes it difficult for the source gas and the dopant gas to flow between the shadow mask 160a and the semiconductor substrate 1a, so that the wraparound width Δd is greatly suppressed.

  On the other hand, in the semiconductor substrate 1 on which the texture shown in FIG. 17A is formed, since the surface is uneven, the gap between the shadow mask 160 and the surface of the semiconductor substrate 1 is larger than the flat surface. . In particular, as described above, when a pyramid-like texture is formed by anisotropic etching using an alkali solution on a semiconductor substrate, there are many voids near the top of the pyramid, and it is difficult to suppress the wraparound of the source gas and the dopant gas. It has a shape. Since the source gas and the dopant gas flow into the increased gap, the wraparound width Δd increases.

  FIG. 18A is a diagram showing a texture formed on the semiconductor substrate 1, and FIG. 18B is a diagram illustrating a void area between the semiconductor substrate 1 on which the texture is formed and the shadow mask 170. FIG. It is a figure for doing. As shown in FIG. 18A, when the texture size increases, the difference in size of one pyramid increases. For example, in the region B, a large pyramid having a texture size of about 40 μm exists, whereas in the region A, a plurality of small pyramids having a texture size of about 15 μm exist. Therefore, the difference in texture size between the pyramids in the region A and the region B is as large as 25 μm.

  When irregularities having a large texture size are formed, as described above, due to the large difference in texture size and the presence of a region where a plurality of small textures are gathered, as shown schematically in FIG. And a large void region 171 is formed between the surface of the semiconductor substrate. Since the source gas and the dopant gas wrap around the void region 171, the wraparound width Δd increases.

  FIG. 19 is a diagram for explaining that boron, which is a p-type dopant, wraps around the edge of shadow mask 160 in the in-plane direction. (A) of FIG. 19 shows the boron concentration characteristic of the surface measured by TOF-SIMS (time-of-flight secondary ion mass spectrometry). FIG. 19B shows the positional relationship between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. An intrinsic (i-type) amorphous semiconductor layer is formed on the entire surface of the semiconductor substrate 1, and then an n-type amorphous semiconductor layer 4 is formed using a shadow mask, and then a p-type amorphous semiconductor layer 5 is formed. Once formed, the boron concentration characteristics were measured. As shown by the arrow in FIG. 19B, the boron concentration characteristic in the X-axis direction was measured from the p-type amorphous semiconductor layer 5 toward the i-type amorphous semiconductor layer. FIG. 19C shows the magnitude of the wraparound width of boron in the Y-axis direction shown in FIG.

  In FIG. 19A, the shadow mask 150 of the photoelectric conversion element 10 of the present embodiment in which the texture is formed on the semiconductor substrate 1 and the photoelectric conversion element of the comparative example in which the texture is not formed on the semiconductor substrate are shown. The relationship between the inward in-plane distance and the boron concentration is shown. However, the region from 0 to 180 μm is a region where the p-type amorphous semiconductor layer 5 is formed. The size of the texture formed on the semiconductor substrate was 1.5 μm.

  When the texture size is increased, a region having a large gap and a region having a small gap are formed in the plane. Therefore, when the shadow mask is arranged, as shown in FIG. In the Y-axis direction, it was found that the wraparound width of boron differs depending on the location. The variation in the wraparound width of boron is preferably smaller in consideration of the stability of the characteristics of the photoelectric conversion element and the yield. In a place where the gap is large, the wraparound width increases as Δd1 and Δd3 in FIG. 19C, and in a region where the texture size is relatively the same, the wraparound width decreases as Δd2. Therefore, it is necessary to suppress the region where the wraparound width of boron is as large as possible, such as Δd1 and Δd3.

  When the texture size is reduced, the generation of a large void area as shown in FIG. 18B can be suppressed. Thereby, the wraparound width Δd of boron is relatively uniform in the Y-axis direction and can be reduced.

  FIG. 20 is a diagram for explaining that the wraparound width of boron varies depending on the texture size. (A) of FIG. 20 shows the area | region which analyzed the density | concentration of boron. However, the upper view of FIG. 20A is a top view, and the lower view is a side view. 20B shows the boron density characteristics when the texture size is 35 μm, and FIG. 20C shows the boron density characteristics when the texture size is 3 μm.

  Here, an i-type intrinsic amorphous semiconductor layer was first formed to 8 nm on the surface of the semiconductor substrate, and a p-type amorphous semiconductor layer 5 was formed thereon using a shadow mask. Then, the in-plane distribution of the boron concentration on the outermost surface was measured using TOF-SIMS. When the texture size is 35 μm, boron wraps around at a very high concentration in the region of about 300 μm in the i-layer region. On the other hand, when the texture size is 3 μm, the boron concentration in the region of about 300 μm is lower than the boron concentration when the texture size is 35 μm.

[Difference in wraparound by dopant type]
It has been found that the wraparound of the dopant gas has different characteristics depending on the dopant gas type. It has been found that when a dopant gas containing boron is used as the dopant gas of the p-type amorphous semiconductor layer 5, a very special wraparound occurs. Here, although the result when diborane (B ₂ H ₆ ) is used will be described, other dopant gas containing boron may be used.

  In FIG. 19A, the region from 0 to 180 μm is a region where the p-type amorphous semiconductor layer 5 is formed. When the texture is formed on the semiconductor substrate 1, as shown in FIG. 19A, the vicinity of the boundary between the region where the p-type amorphous semiconductor layer 5 is formed and the region where the p-type amorphous semiconductor layer 5 is not formed (about 180 μm). In the region), the boron concentration has a peak, which is about four times the region where the p-type amorphous semiconductor layer 5 is formed. A boron diffusion region is seen from about 180 μm to 300 μm from the vicinity of this boundary toward the region where the p-type amorphous semiconductor layer 5 is not formed. The width of the boron diffusion region is a wraparound width Δd (Δd = 300 μm−180 μm = 120 μm). Here, a region having a higher boron concentration than the boron concentration in the region where the p-type amorphous semiconductor layer 5 is formed is referred to as a “high boron concentration region”.

  Even on a flat surface where no texture is formed on the semiconductor substrate, there is a region where the boron concentration is at a peak. The boron concentration in this region is boron in the region where the p-type amorphous semiconductor layer 5 is formed. The density is about twice or less. For this reason, there is a correlation between the uneven surface of the semiconductor substrate 1 and the boron concentration in the high-concentration region of boron. It can be seen that the boron concentration increases as the unevenness of the texture formed on the semiconductor substrate 1 increases.

  For this reason, when forming the p-type amorphous semiconductor layer 5 using boron as a dopant, it is preferable to form the n-type amorphous semiconductor layer 4 so as not to overlap the high concentration region of boron. This is because when the n-type amorphous semiconductor layer 4 is formed later, the i-type amorphous semiconductor layer 4 and the n-type amorphous semiconductor layer 4 are formed. A high-concentration region of boron is formed at the interface, and a phenomenon in which the lifetime of minority carriers decreases is observed in this region, which is not preferable. For example, in the region where the n-type amorphous semiconductor layer 4 shown in FIG. 4A is formed, a region having a width of (L + 2H) may be formed out of the high concentration region of boron. Further, in FIG. 5, it is sufficient that the region sandwiched between the two B points is formed away from the high-concentration region of boron. In FIG. In (b) of 6, it is only necessary that the region sandwiched between the two F points is formed away from the high concentration region of boron.

  For the same reason, the n-type electrode 6 may be formed out of the high concentration region of boron. It is preferable that the region of (L + 2H) width in FIG. 4A is formed away from the high concentration region of boron.

As a dopant of the n-type amorphous semiconductor layer 4, film formation was performed using a dopant gas containing phosphorus. In the present embodiment, phosphine (PH ₃ ) is used as a dopant gas containing phosphorus. When a dopant gas containing phosphorus was used, no special wraparound such as boron was caused. In boron, the wraparound width Δd was about 120 μm, but the wraparound width of phosphorus was about 20-30 μm even when using the texture size and shadow mask under the same conditions. Thus, it turned out that the amount of wraparound by a dopant seed | species differs.

  When p-type amorphous semiconductor layer 5 or n-type amorphous semiconductor layer 4 is patterned using a shadow mask, it is preferable to first form an amorphous semiconductor layer containing a dopant having a small wraparound width. The interface between the passivation film 3 and the p-type amorphous semiconductor layer 5 or the n-type amorphous semiconductor layer 4 is particularly important, and it is not preferable that a dopant of a different conductive layer enters here. When an amorphous semiconductor layer containing a dopant having a large wraparound width is formed first after the passivation film 3 is formed, the wraparound width is large in a region on the passivation film of the amorphous semiconductor layer having a small wraparound width to be formed later. It is highly possible that the dopant diffuses and the characteristics are deteriorated.

  That is, in the case of the above boron and phosphorus, the n-type amorphous semiconductor layer 4 containing phosphorus with a small wraparound width is formed first, and then the p-type amorphous semiconductor layer containing boron with a large wraparound width. 5 is preferably formed.

[Embodiment 2]
FIG. 21 is a cross-sectional view showing the configuration of the photoelectric conversion element according to Embodiment 2 of the present invention. Referring to FIG. 21, the photoelectric conversion element 200 according to the second embodiment is obtained by replacing the antireflection film 2 of the photoelectric conversion element 10 shown in FIG. 1 with the antireflection film 201 and replacing the passivation film 3 with the passivation film 202. Other configurations are the same as those of the photoelectric conversion element 10.

  The antireflection film 201 is disposed in contact with the light receiving surface of the semiconductor substrate 1.

  The antireflection film 201 has a three-layer structure of i-type amorphous silicon / n-type amorphous silicon / silicon nitride film. In this case, the film thickness of i-type amorphous silicon is, for example, 5 nm, the film thickness of n-type amorphous silicon is, for example, 8 nm, and the film thickness of the silicon nitride film is, for example, 60 nm.

  The passivation film 202 is formed between the semiconductor substrate 1, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor layer 5, the semiconductor substrate 1, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor. The semiconductor layer 5 and the protective film 8 are disposed in contact with each other.

  The passivation film 202 is made of an i-type amorphous semiconductor layer. The i-type amorphous semiconductor layer is an amorphous semiconductor layer that is substantially intrinsic and contains hydrogen. The i-type amorphous semiconductor layer includes, for example, i-type amorphous silicon, i-type amorphous silicon germanium, i-type amorphous germanium, i-type amorphous silicon carbide, i-type amorphous silicon carbide, i-type It consists of amorphous silicon nitride, i-type amorphous silicon oxynitride, i-type amorphous silicon oxide, i-type amorphous silicon carbon oxide, and the like.

  The thickness of the passivation film 202 is, for example, 1 nm to 15 nm, preferably 3 nm to 12 nm.

  As described above, the passivation film 202 is formed of i-type amorphous silicon oxynitride or i-type amorphous silicon nitride, so that it is included in the p-type amorphous semiconductor layer 5 formed on the passivation film 202. It is possible to suppress diffusion of a dopant such as boron into the semiconductor substrate 1.

  The i-type amorphous semiconductor layer constituting the passivation film 202 has defects at the interface between the semiconductor substrate 1 and the n-type amorphous semiconductor layer 4 and at the interface between the semiconductor substrate 1 and the p-type amorphous semiconductor layer 5. To reduce.

  In the photoelectric conversion element 200, in the manufacturing steps shown in FIGS. 7 to 11, the step of forming the antireflection film 2 (FIG. 8D) is replaced with the step of forming the antireflection film 201. The manufacturing process is performed according to a manufacturing process in which the forming process (FIG. 7C) is replaced with the process of forming the passivation film 202.

The antireflection film 201 is formed by sequentially depositing i-type amorphous silicon, n-type amorphous silicon, and a silicon nitride film on the light receiving surface of the semiconductor substrate 1 by plasma CVD. More specifically, a plasma CVD method under conditions of a substrate temperature: 130 to 180 ° C., a hydrogen gas flow rate: 0 to 100 sccm, a silane gas flow rate: 40 sccm, a pressure: 40 to 120 Pa, and an RF power density: 5 to 15 mW / cm ^2. To deposit i-type amorphous silicon.

Further, the n-type amorphous silicon is formed by plasma CVD with further flowing PH ₃ gas under the above conditions, and the silicon nitride film is formed by plasma CVD with further flowing NH ₃ gas under the above conditions. The

  After forming the antireflection film 201, a passivation film 202 is formed on the back surface of the semiconductor substrate 1. More specifically, the passivation film 202 is formed by depositing i-type amorphous silicon on the back surface of the semiconductor substrate 1 by plasma CVD using the same conditions as the i-type amorphous silicon of the antireflection film 201. Form.

  And after forming the passivation film 202, the photoelectric conversion element 200 is completed by performing the process (e) of FIG. 8-the process (m) of FIG. 11 one by one.

  In this case, Ag / Ni = 100 nm / 350 nm was formed as electrodes 6 and 7 in step (l) of FIG.

  In the step (m) of FIG. 11, a protective film 8 having a three-layer structure made of 4 nm i-type amorphous silicon, 8 nm n-type amorphous silicon, and 60 nm silicon nitride film (SiN) was formed.

  As described above, in the second embodiment, the i-type amorphous silicon that is the passivation film 202 is formed on the entire surface of the semiconductor substrate 1 by a single film formation. For this reason, the semiconductor substrate 1 can be passivated by covering the surface of the semiconductor substrate 1 with a substantially uniform film thickness. In this embodiment, the film thickness is 9 nm.

  Then, on the uniform passivation film 202, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 having a film thickness reduction region were formed 100 μm apart using a shadow mask. Therefore, both passivation properties and low resistance can be achieved.

  In addition, as described above, the n-type amorphous semiconductor layer 4 containing phosphorus with a small wraparound width was formed first, and then the p-type amorphous semiconductor layer 5 containing boron with a large wraparound width was formed.

The silicon nitride film is formed by a plasma CVD method by additionally flowing NH ₃ gas in the same plasma apparatus as the plasma apparatus in which i-type amorphous silicon is formed. Further, the n-type amorphous silicon is formed by plasma CVD by additionally flowing PH ₃ gas in the same plasma apparatus as the plasma apparatus in which i-type amorphous silicon is formed. Therefore, a three-layer structure of i-type amorphous silicon / n-type amorphous silicon / silicon nitride film constituting the antireflection film 201 can be continuously formed in a vacuum atmosphere.

  In addition, after the antireflection film 201 is formed, the semiconductor substrate 1 is inverted by a manipulator in the plasma apparatus, and i-type amorphous silicon is deposited on the back surface of the semiconductor substrate 1 by a plasma CVD method to form a passivation film 202. .

  Further, the shadow mask is aligned at an appropriate position, and then the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the conductive layers of the electrodes 6 and 7 are formed under the conditions described in the first embodiment. By forming the film, the structures of the light receiving surface and the back surface of the photoelectric conversion element 200 can be manufactured in a vacuum atmosphere without being exposed to the air, and the photoelectric conversion element 200 can be manufactured.

  In the second embodiment, as described above, the antireflection film 201 is formed by continuously forming a three-layer structure of i-type amorphous silicon / n-type amorphous silicon / silicon nitride film, and then Then, the semiconductor substrate 1 is inverted to form a passivation film 202 on the back surface, and the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed using a shadow mask (in this embodiment, a metal mask). It is preferable to form a film. In particular, before forming the i-type amorphous silicon (passivation film 202) on the back surface, if a silicon nitride film is formed on the amorphous silicon layer on the light receiving surface, the i-type amorphous material is formed on the back surface. The thermal history when silicon (passivation film 202) is formed may cause the light-receiving surface to have a lower passivation property. However, a silicon nitride film is preferable because it suppresses the deterioration of the passivation property.

  Further, as described above, the protective film 8 has a three-layer structure, but the protective film 8 is formed on the electrodes 6 and 7 and the gap region G even when the protective film 8 having a three-layer structure is formed. It is preferable to improve the insulation and moisture resistance. The protective film on the electrodes 6 and 7 and the protective film on the gap region G do not necessarily have to be continuous, but forming them continuously can reduce the number of process steps and make the film quality uniform. More preferable.

  Furthermore, in the photoelectric conversion element 200, it turned out that the effect similar to the effect in Embodiment 1 is acquired regarding heat resistance and an electrode floating suppression effect.

  Moreover, in the photoelectric conversion element 200, it turned out that the same effect is acquired also by suppression of the wraparound width by making a texture size less than 30 micrometers, and suppression of the reverse direction saturation current accompanying it. Further, in this embodiment, since the passivation film is different, the same effect can be obtained as the effect relating to the conductive layer and the insulating film described in Embodiment 1.

  Since the passivation film 3 of the photoelectric conversion element 10 is made of a thermal oxide film, it is difficult to form all of the amorphous silicon on the light receiving surface and the back surface in a vacuum atmosphere in the first embodiment.

  However, in this embodiment mode, the photoelectric conversion element 200 is manufactured using a cluster-type CVD apparatus as illustrated in FIG. All the chambers 222 to 227 and the transfer chamber 220 illustrated in FIG. 22 are in a vacuum, and the photoelectric conversion element to be manufactured can move between the chambers using the arm 220a of the transfer chamber 220 without being exposed to the atmosphere. . Hereinafter, a manufacturing procedure of the photoelectric conversion element 200 will be described.

  The semiconductor substrate 1 having the texture formed on both sides after the RCA cleaning was set in the load lock unit 211, and the inside of the chamber was evacuated.

  Thereafter, the semiconductor substrate 1 is sent to the i layer forming chamber 225 via the transfer chamber 220, and an i-type amorphous semiconductor layer is formed on the light receiving surface side of the semiconductor substrate 1. Thereafter, the semiconductor substrate 1 is sent to the n-layer formation chamber 222, and an n-type amorphous semiconductor layer is formed in contact with the i-type amorphous semiconductor layer. Thereafter, the semiconductor substrate 1 is sent to the SiN formation chamber 226, and a silicon nitride film is formed in contact with the n-type amorphous semiconductor layer. Thereby, the antireflection film 201 is formed on the light receiving surface of the semiconductor substrate 1 without being exposed to the atmosphere.

  Next, the semiconductor substrate 1 is sent to the vacuum alignment & wafer inversion chamber 224 to invert the semiconductor substrate 1. Then, the semiconductor substrate 1 is sent to the i layer forming chamber 225, and an i-type amorphous semiconductor layer is formed on the entire textured surface on the back surface of the semiconductor substrate 1.

  Next, the semiconductor substrate 1 is sent to the vacuum alignment & wafer inversion chamber 224, and a shadow mask (metal mask) for forming an n-type amorphous semiconductor layer is aligned with a predetermined position of the semiconductor substrate 1, and then the n layer Then, the n-type amorphous semiconductor layer 4 is deposited on the i-layer amorphous semiconductor layer.

  Subsequently, in the vacuum alignment & wafer inversion chamber 224, a shadow mask (metal mask) for forming the p-type amorphous semiconductor layer is placed at a predetermined position (position for forming the p-type amorphous semiconductor layer). The p-type amorphous semiconductor layer 5 is formed in the p-layer formation chamber 223 again.

  Next, in the vacuum alignment & wafer inversion chamber 224, the shadow mask (metal mask) for forming the p-type amorphous semiconductor layer is replaced with a shadow mask (metal mask) for electrode formation, and a predetermined mask on the semiconductor substrate 1 is formed. Align to position. Thereafter, in the electrode formation chamber 227, the electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 by a single film formation.

  Thereafter, in the vacuum alignment & wafer inversion chamber 224, the shadow mask for electrode formation is removed and replaced with a shadow mask for the electrode protective film SiN, and alignment is performed at a predetermined position. Finally, by forming the protective film 8 in the SiN formation chamber 226, a back junction solar cell can be manufactured without exposure to the atmosphere. By performing such a process, a back junction solar cell can be manufactured in a very short process time.

  In addition, i-type (intrinsic), p-type, and n-type amorphous semiconductor layers are easily oxidized when exposed to the atmosphere, and when oxidized, the series resistance component may increase. However, it is preferable to fabricate through the above process because oxidation at the interface and the like can be suppressed and a low-resistance solar cell can be fabricated.

  In the process described above, the amorphous semiconductor layer on the light receiving surface, the amorphous semiconductor layer on the back surface, the electrode on the back surface, and the protective film on the back surface are all formed without exposure to the atmosphere. However, after film formation on the light-receiving surface side, or before the formation of the back surface electrode or before the formation of the back surface protective film, exposure to the atmosphere may be performed to perform the process in another apparatus. Preferably, the film formation of the amorphous semiconductor layer on the back surface (film formation of the intrinsic amorphous semiconductor layer, film formation of the n-type amorphous semiconductor layer, film formation of the p-type amorphous semiconductor layer) is exposed to the atmosphere. Without performing alignment of the shadow mask in a vacuum, it is preferable because the interface oxidation can be suppressed and a low-resistance solar cell can be manufactured.

  From the viewpoint described above, the second embodiment is more preferable than the first embodiment. It is preferable to deposit all the amorphous silicon on the light-receiving surface and the back surface in a vacuum atmosphere, because production variations can be suppressed and the yield can be improved.

  In the above description, the manufacturing process in the cluster type PECVD apparatus has been described. However, there is no problem even if the process apparatus is arranged in an inline type in a line in a line.

  Furthermore, it is more preferable to form the electrodes 6 and 7 and the protective film 8 without exposing to the atmosphere, and effects such as prevention of oxidation of the electrode surface and improvement in adhesion to the protective film 8 can be obtained.

  Other explanations in the second embodiment are the same as those in the first embodiment.

Further, in the above description, the amorphous semiconductor layer has been described as being formed by the plasma CVD method. However, the amorphous semiconductor layer is not limited to the plasma CVD method, and is formed by another method such as a CatCVD (catalytic CVD) method. May be. When the CatCVD method is used, film formation conditions are, for example, substrate temperature: 100 to 300 ° C., pressure: 10 to 500 Pa, catalyst medium temperature (when tungsten is used as the thermal catalyst): 1500 to 2000 ° C., RF power density: a 0.01 to 1 / cm ^2. Thereby, an amorphous semiconductor layer with high quality can be formed at a relatively low temperature and in a short time.

[Embodiment 3]
FIG. 23 is a schematic diagram illustrating a configuration of a photoelectric conversion module including the photoelectric conversion element according to the third embodiment. Referring to FIG. 23, photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.

  The plurality of photoelectric conversion elements 1001 are arranged in an array and are connected in series. Note that the plurality of photoelectric conversion elements 1001 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel.

  Each of the plurality of photoelectric conversion elements 1001 includes one of the photoelectric conversion elements 10 and 200.

  The cover 1002 is formed of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001. The cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material (on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001). For example, glass, a resin sheet etc.) and the sealing material (for example, EVA etc.) which fills the clearance gap between a transparent base material and a back surface base material are included.

  The output terminal 1003 is connected to the photoelectric conversion element 1001 arranged at one end of the plurality of photoelectric conversion elements 1001 connected in series.

  The output terminal 1004 is connected to the photoelectric conversion element 1001 arranged at the other end of the plurality of photoelectric conversion elements 1001 connected in series.

  As described above, the photoelectric conversion elements 10 and 200 are excellent in insulation, moisture resistance, and heat resistance.

  Therefore, the insulation property, moisture resistance, and heat resistance of the photoelectric conversion module 1000 can be improved.

  Note that the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 is an arbitrary integer of 2 or more.

  Further, the photoelectric conversion module according to Embodiment 3 is not limited to the configuration illustrated in FIG. 23, and may have any configuration as long as any one of the photoelectric conversion elements 10 and 200 is used.

[Embodiment 4]
FIG. 24 is a schematic diagram showing a configuration of a photovoltaic power generation system including a photoelectric conversion element according to this embodiment.

  Referring to FIG. 24, the photovoltaic power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105.

  The connection box 1102 is connected to the photoelectric conversion module array 1101. The power conditioner 1103 is connected to the connection box 1102. Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110. The power meter 1105 is connected to the distribution board 1104 and the grid connection.

  The photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the connection box 1102.

  The connection box 1102 receives DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.

  The power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104.

  Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electric equipment 1110, the distribution board 1104 supplies the surplus AC power to the grid interconnection via the power meter 1105.

  The power meter 1105 measures the power in the direction from the grid connection to the distribution board 1104 and measures the power in the direction from the distribution board 1104 to the grid connection.

  FIG. 25 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG.

  Referring to FIG. 25, photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.

  The plurality of photoelectric conversion modules 1120 are arranged in an array and are connected in series. Note that the plurality of photoelectric conversion modules 1120 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.

  The output terminal 1121 is connected to the photoelectric conversion module 1120 located at one end of the plurality of photoelectric conversion modules 1120 connected in series.

  The output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.

  Note that the number of photoelectric conversion modules 1120 included in the photoelectric conversion module array 1101 is an arbitrary integer of 2 or more.

  The operation in the solar power generation system 1100 will be described. The photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.

  The power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.

  The distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the grid connection via the power meter 1105.

  Further, when the AC power received from the power conditioner 1103 is less than the power consumption of the electric device 1110, the distribution board 1104 receives the AC power received from the grid connection and the AC power received from the power conditioner 1103 to the electric device 1110. Supply.

  As described above, the solar power generation system 1100 includes any one of the photoelectric conversion elements 10 and 200 that are excellent in insulation, moisture resistance, and heat resistance.

  Therefore, the insulation, moisture proof, and heat resistance of the photovoltaic power generation system 1100 can be improved.

  FIG. 26 is a schematic diagram showing a configuration of another photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

  The photovoltaic power generation system including the photoelectric conversion element according to this embodiment may be a photovoltaic power generation system 1100A shown in FIG.

  Referring to FIG. 26, solar power generation system 1100A is the same as solar power generation system 1100 except that storage battery 1106 is added to solar power generation system 1100 shown in FIG.

  The storage battery 1106 is connected to the power conditioner 1103.

  In solar power generation system 1100A, power conditioner 1103 appropriately converts part or all of the DC power received from connection box 1102 and stores it in storage battery 1106.

  In addition, the power conditioner 1103 performs the same operation as that of the photovoltaic power generation system 1100.

  Storage battery 1106 stores the DC power received from power conditioner 1103. The storage battery 1106 supplies the stored power to the power conditioner 1103 as appropriate according to the amount of power generated by the photoelectric conversion module array 1101 and / or the power consumption of the electric device 1110.

  Thus, since the solar power generation system 1100A includes the storage battery 1106, it can suppress output fluctuations due to fluctuations in the amount of sunshine, and can use the electric power stored in the storage battery 1106 even in a time zone without sunlight. The device 1110 can be supplied.

  Note that the storage battery 1106 may be built in the power conditioner 1103.

  Further, the photovoltaic power generation system according to Embodiment 4 is not limited to the configuration shown in FIGS. 24 and 25 or the configuration shown in FIGS. 25 and 26, and may have any configuration as long as one of photoelectric conversion elements 10 and 200 is used. May be.

[Embodiment 5]
FIG. 27 is a schematic diagram illustrating a configuration of a photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

  Referring to FIG. 27, solar power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221. The photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation systems 1100 and 1100A shown in FIGS.

  The power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.

  The transformer 1221 is connected to the power conditioners 1211 to 121n and the grid connection.

  Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).

  Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.

  Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.

  The connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.

  The current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.

  The i photoelectric conversion module arrays 1301 to 130i of the module system 1231 convert sunlight into electricity to generate DC power, and the generated DC power is supplied to the current collecting box 1321 through the connection boxes 1311 to 131i, respectively. Supply. The i photoelectric conversion module arrays 1301 to 130i of the module system 1232 convert sunlight into electricity to generate DC power, and the generated DC power is supplied to the current collecting box 1321 through the connection boxes 1311 to 131i, respectively. Supply. Hereinafter, similarly, the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To supply box 1321.

  Then, the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.

  The j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.

  In the same manner, the j current collection boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.

  Each of the power conditioners 1211 to 121n converts the DC power received from the subsystems 1201 to 120n into AC power, and supplies the converted AC power to the transformer 1221.

  The transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the grid interconnection.

  As described above, the photovoltaic power generation system 1200 includes any one of the photoelectric conversion elements 10 and 200 that are excellent in insulation, moisture resistance, and heat resistance.

  Therefore, the insulation, moisture resistance, and heat resistance of the photovoltaic power generation system 1200 can be improved.

  FIG. 28 is a schematic diagram showing the configuration of another photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

  The photovoltaic power generation system including the photoelectric conversion element according to this embodiment may be a photovoltaic power generation system 1200A illustrated in FIG.

  Referring to FIG. 28, a photovoltaic power generation system 1200 </ b> A is obtained by adding storage batteries 1241 to 124 n to the photovoltaic power generation system 1200 shown in FIG. 27, and is otherwise the same as the photovoltaic power generation system 1200.

  The storage batteries 1241 to 124n are connected to the power conditioners 1211 to 121n, respectively.

  In photovoltaic power generation system 1200A, power conditioners 1211 to 121n convert the DC power received from subsystems 1201 to 120n into AC power, and supply the converted AC power to transformer 1221. In addition, power conditioners 1211 to 121n appropriately convert DC power received from subsystems 1201 to 120n, respectively, and store the converted DC power in storage batteries 1241 to 124n, respectively.

  The storage batteries 1241 to 124n supply the stored power to the power conditioners 1211 to 121n, respectively, according to the amount of DC power from the subsystems 1201 to 120n.

  Thus, since the photovoltaic power generation system 1200A includes the storage batteries 1241 to 124n, it is possible to suppress output fluctuations due to fluctuations in the amount of sunlight, and power is stored in the storage batteries 1241 to 124n even in a time zone without sunlight. Power can be supplied to the transformer 1221.

  The storage batteries 1241 to 124n may be incorporated in the power conditioners 1211 to 121n, respectively.

  Moreover, the solar power generation system according to Embodiment 5 is not limited to the configuration shown in FIGS.

  Furthermore, in Embodiment 5, it is not necessary that all the photoelectric conversion elements included in the photovoltaic power generation systems 1200 and 1200A are the photoelectric conversion elements 10 and 200 according to Embodiments 1 and 2.

  For example, all of the photoelectric conversion elements included in a certain subsystem (any one of the subsystems 1201 to 120n) are any one of the photoelectric conversion elements 10 and 200 according to the first to second embodiments, and another subsystem. It is possible that some or all of the photoelectric conversion elements included in any one of the subsystems 1201 to 120n are photoelectric conversion elements other than the photoelectric conversion elements 10 and 200.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  In each of the above-described embodiments, the configuration in which the texture structure is formed on both surfaces of the semiconductor substrate 1 has been described. However, a configuration in which the texture structure is not provided on the light receiving surface may be employed.

  In addition, the configuration in which the passivation film 3 (or the passivation film 202) is disposed in contact with the back surface of the semiconductor substrate 1 has been described, but a configuration in which the passivation film 3 (or the passivation film 202) is not disposed may be employed.

  In each of the above-described embodiments, the configuration in which the protective film 8 is provided has been described.

  Therefore, the photoelectric conversion element according to the embodiment of the present invention is formed on a semiconductor substrate having a texture formed on at least one surface and a surface on which the texture of the semiconductor substrate is formed, and has a first conductivity type. Formed on the surface of the semiconductor substrate on which the texture of the semiconductor substrate is formed and formed adjacent to the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate. A second amorphous semiconductor layer having a second conductivity type opposite to the mold, and when the texture is viewed in plan, if the average value of the diameter of the circumscribed circle of the convex portion of the texture is less than 30 μm, Quality can be improved.

[Embodiment 6]
As described in the first embodiment, when the p-type amorphous semiconductor layer 5 containing boron as a dopant is formed first and the n-type amorphous semiconductor layer 4 containing phosphorus as a dopant is formed later, boron is used. There is a possibility that the n-type amorphous semiconductor layer 4 is formed on the high concentration region. In this case, in the region where the n-type amorphous semiconductor layer 4 is formed overlying the high-concentration region of boron, a phenomenon in which electrical characteristics deteriorate is observed, which is not preferable.

Therefore, in the photoelectric conversion element 600 according to Embodiment 6, the p-type amorphous semiconductor layer 5 containing boron as a dopant is formed first, and the n-type amorphous semiconductor layer 4 containing phosphorus as a dopant is formed later. The n-type amorphous semiconductor layer 4 is formed so as not to overlap the high concentration region of boron. That is, a high-concentration region of boron is not included between n-type amorphous semiconductor layer 4 and semiconductor substrate 1. FIG. 30 is a cross-sectional view showing a configuration of photoelectric conversion element 600 in the sixth embodiment. . FIG. 30 also shows an enlarged view near the boundary between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. In the enlarged view, the boron concentration in the region is superimposed and displayed with a one-dot chain line. As shown in FIG. 30, the n-type amorphous semiconductor layer 4 is formed on a boron high-concentration region whose boron concentration is higher than the boron concentration in the region where the p-type amorphous semiconductor layer 5 is formed. It has not been.

  For example, referring to FIG. 4A, the n-type amorphous semiconductor layer 4 may be formed so that the region of (L + 2H) width is out of the high-concentration region of boron. Further, in the configuration shown in FIG. 5, it is sufficient that the region sandwiched between the two B points is formed away from the high concentration region of boron. In the configuration shown in FIG. In the configuration shown in FIG. 6B, the sandwiched region may be formed so that the region sandwiched between the two F points deviates from the boron high concentration region.

  For the same reason, the n-type electrode 6 may be formed out of the high concentration region of boron. The region having a width of (L + 2H) in FIG. 4A only needs to be formed out of the high concentration region of boron.

  The manufacturing method of the photoelectric conversion element 600 in the present embodiment is different from the manufacturing method of the photoelectric conversion element 10 in the first embodiment in the order of forming the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. In other words, the n-type amorphous semiconductor layer 4 is formed so as not to overlap the high concentration region of boron.

  In the method of manufacturing the photoelectric conversion element 10 shown in FIGS. 7 to 11, the n-type amorphous semiconductor layer 4 is formed first (FIGS. 8E and 8F), and the p-type amorphous semiconductor layer 5 is formed. Was formed later ((g) and (h) of FIG. 9). In the photoelectric conversion element 600 in the present embodiment, the p-type amorphous semiconductor layer 5 is formed first, and the n-type amorphous semiconductor layer 4 is formed later. The method for forming the p-type amorphous semiconductor layer 5 and the n-type amorphous semiconductor layer 4 is the same as that in the first embodiment. However, when the n-type amorphous semiconductor layer 4 is formed, a mask having a width that does not overlap the high concentration region of boron is used.

  FIGS. 31A to 31C are views for explaining a manufacturing method when the n-type amorphous semiconductor layer 4 is formed after the p-type amorphous semiconductor layer 5 is formed. After the p-type amorphous semiconductor layer 5 is formed, a shadow mask 50 is disposed on the passivation film 3 and the p-type amorphous semiconductor layer 5 (see step (a) in FIG. 31).

  As described with reference to FIG. 19 and the like, the boron concentration has a peak near the boundary between the region where the p-type amorphous semiconductor layer 5 is formed and the region where the p-type amorphous semiconductor layer 5 is not formed, and includes a position where the boron concentration peaks. It has been found that a high concentration region of boron is formed. Therefore, when the n-type amorphous semiconductor layer 4 is formed, a mask 50 having such a width that the n-type amorphous semiconductor layer 4 does not overlap with the boron high-concentration region is used.

  After disposing the mask 50, the n-type amorphous semiconductor layer 4 is formed by the method described in Embodiment 1 (see step (b) in FIG. 31).

  When the shadow mask 50 is removed after the n-type amorphous semiconductor layer 4 is formed, the n-type amorphous semiconductor layers 4 and the p-type amorphous semiconductor layers 5 that are alternately arranged in the in-plane direction of the semiconductor substrate 1. Is formed on the passivation film 3 (see step (c) in FIG. 31).

  In the photoelectric conversion element 600 according to Embodiment 6, a texture structure may be formed on the back surface of the semiconductor substrate 1 as in the photoelectric conversion element 10 shown in FIG. 1, but the texture size may not be less than 30 μm. Good. However, if the texture size is less than 30 μm, the reverse saturation current density can be reduced as described in Embodiment 1, so that the quality of the photoelectric conversion element 600 can be improved.

  In the photoelectric conversion element 600 according to the sixth embodiment, unlike the structure illustrated in FIG. 1, the texture structure may not be formed on the back surface of the semiconductor substrate 1.

  FIG. 32 is a cross-sectional view showing the configuration of the photoelectric conversion element 600A according to the sixth embodiment when no texture is formed on the back surface of the semiconductor substrate 1. However, not only the back surface of the semiconductor substrate 1 but also the light receiving surface may be provided with no texture structure.

  When the n-type amorphous semiconductor layer 4 containing phosphorus as a dopant is formed first and the p-type amorphous semiconductor layer 5 containing boron as a dopant is formed later, the semiconductor substrate 1 and the n-type amorphous semiconductor layer 5 are formed. A high-concentration region of boron is not formed between the high-quality semiconductor layer 4. Therefore, in photoelectric conversion element 600 in Embodiment 6, n-type amorphous semiconductor layer 4 containing phosphorus as a dopant is formed first, and p-type amorphous semiconductor layer 5 containing boron as a dopant is formed later. A configuration is also included.

  The photoelectric conversion element 200 according to the second embodiment described above has a configuration in which the antireflection film 2 of the photoelectric conversion element 10 according to the first embodiment is replaced with the antireflection film 201 and the passivation film 3 is replaced with the passivation film 202 ( 21), the photoelectric conversion element 600 in Embodiment 6 can be similarly modified.

  The photoelectric conversion module according to Embodiment 3 may be configured using the photoelectric conversion element 600 described in Embodiment 6.

  The photovoltaic power generation system according to Embodiment 4 may be configured using the photoelectric conversion element 600 described in Embodiment 6.

  The photovoltaic power generation system according to Embodiment 5 may be configured using the photoelectric conversion element 600 described in Embodiment 6.

  The present invention is applied to a photoelectric conversion element, a solar cell module including the photoelectric conversion element, and a solar power generation system.

Claims (7)

A semiconductor substrate having a texture formed on at least one surface;
A first amorphous semiconductor layer having a first conductivity type formed on a surface of the semiconductor substrate on which the texture is formed;
Formed on a surface of the semiconductor substrate on which the texture is formed and formed adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate, opposite to the first conductivity type A second amorphous semiconductor layer having a second conductivity type;
With
When the texture is viewed in plan, the average value of the diameters of the circumscribed circles of the convex portions of the texture is less than 30 μm.   An intrinsic amorphous semiconductor layer formed between the textured surface of the semiconductor substrate and the first amorphous semiconductor layer and the second amorphous semiconductor layer; The photoelectric conversion element according to claim 1. A first electrode formed on the first amorphous semiconductor layer;
A second electrode formed on the second amorphous semiconductor layer;
The photoelectric conversion element according to claim 1, further comprising: a protective film formed so as to cover at least a part of the first electrode and the second electrode. In the one thin film formed on the semiconductor substrate, the point where the film thickness is the maximum is the first point, and the reduction rate of the film thickness in the in-plane direction of the one thin film is the first decrease. The sign of the change rate of the thickness of the one thin film changes from negative to positive in the in-plane direction of the one thin film at a point where the rate changes to a second reduction rate larger than the first reduction rate. When the point is the second point and the region from the first point to the second point in the in-plane direction of the one thin film is defined as a film thickness reduction region,
4. The photoelectric conversion according to claim 1, wherein at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer has the film thickness reduction region. 5. element. A semiconductor substrate;
An n-type amorphous semiconductor layer formed on the semiconductor substrate and containing phosphorus as a dopant;
A p-type amorphous semiconductor layer formed on the semiconductor substrate adjacent to the n-type amorphous semiconductor layer in an in-plane direction of the semiconductor substrate and containing boron as a dopant;
With
Between the n-type amorphous semiconductor layer and the semiconductor substrate, a high concentration region of boron having a boron concentration higher than the boron concentration in the region where the p-type amorphous semiconductor layer is formed is not included. , Photoelectric conversion element.   The photoelectric conversion element according to claim 5, wherein a texture is formed on a surface of the semiconductor substrate on which the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer are formed.   The photoelectric conversion element according to claim 6, wherein an average value of diameters of circumscribed circles of the convex portions of the texture is less than 30 μm when the texture is viewed in plan.