JP6613252B2 - Photoelectric conversion element - Google Patents

Description

  The present invention relates to a photoelectric conversion element.

  Conventionally, intrinsic (i-type) amorphous silicon is interposed between an n-type crystalline silicon substrate and a p-type amorphous silicon layer to reduce defects at the interface, and characteristics at the heterojunction interface. There is known a photoelectric conversion device that improves the above (see Patent Document 1 below).

JP 2010-10620 A

  When manufacturing a back junction photoelectric conversion element in which intrinsic amorphous silicon is formed at the interface between the crystalline silicon and the p-type amorphous silicon layer, a shadow mask such as a metal mask is used to form a back surface of the crystalline silicon substrate. When the n-type semiconductor layer and the p-type semiconductor layer are separately patterned, a semiconductor layer to be formed later must be formed at an appropriate position according to the position of the semiconductor layer to be formed first. However, if the position of the previously formed semiconductor layer cannot be reliably recognized due to non-uniform reflected light due to dimples on the crystalline silicon substrate, an n-type semiconductor layer and a p-type semiconductor layer are formed at appropriate positions. In some cases, the n-type semiconductor layer and the p-type semiconductor layer overlap with each other, resulting in a decrease in photoelectric conversion efficiency.

  An object of the present invention is to provide a photoelectric conversion element capable of reducing a decrease in photoelectric conversion efficiency caused by overlapping an n-type semiconductor layer and a p-type semiconductor layer, and a solar cell module and a photovoltaic power generation system including the photoelectric conversion element. And

  A photoelectric conversion element according to the present invention is formed on a semiconductor substrate, a first amorphous semiconductor layer having a first conductivity type, formed on one surface of the semiconductor substrate, and on one surface of the semiconductor substrate. And a second amorphous semiconductor layer formed adjacent to the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type; A texture structure formed on at least a part of one surface of the semiconductor substrate, and an amorphous material of at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer on the texture structure A light scattering layer including a semiconductor layer.

  ADVANTAGE OF THE INVENTION According to this invention, the fall of the photoelectric conversion efficiency by an n-type semiconductor layer and a p-type semiconductor layer overlapping can be reduced.

FIG. 1A is a schematic view of the photoelectric conversion element according to Embodiment 1 as viewed from above. 1B is a cross-sectional view of the photoelectric conversion element shown in FIG. 1A cut along line AA. FIG. 2 is a diagram showing a texture structure in which a plurality of pyramidal irregularities having various sizes and shapes are formed. FIG. 3 is an enlarged view of the electrode and the protective film shown in FIG. FIG. 4 is a cross-sectional view showing a detailed structure of the n-type amorphous semiconductor layer shown in FIG. FIG. 5 is a cross-sectional view showing another detailed structure of the n-type amorphous semiconductor layer shown in FIG. FIG. 6 is a first process diagram showing a method of manufacturing the photoelectric conversion element shown in FIG. FIG. 7 is a second process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 8 is a third process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 9 is a fourth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 10 is a fifth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1. FIG. 11A is a schematic view of the shadow mask used when forming the n-type amorphous semiconductor layer in the first embodiment as viewed from above. FIG. 11B is a schematic view of the shadow mask used when forming the p-type amorphous semiconductor layer in Embodiment 1 as viewed from above. FIG. 11C is a schematic diagram for explaining alignment of the shadow mask shown in FIG. 11B. (A)-(d) of FIG. 12 is a figure which shows the comparative example of the optical microscope image of the alignment mark at the time of forming the alignment mark in the semiconductor substrate from which the state of a back surface differs, respectively. FIG. 13A is a plan view seen from the back side of the photoelectric conversion element shown in FIG. 1. FIG. 13B is a plan view of the wiring sheet. FIG. 14A is a schematic view of the photoelectric conversion element according to Embodiment 2 as viewed from above. FIG. 14B is a process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 14A. FIG. 14C is a schematic view of another example semiconductor substrate according to Embodiment 2 as viewed from above. FIG. 15A is a schematic view of a shadow mask used when forming an n-type amorphous semiconductor layer in Embodiment 3 as viewed from above. FIG. 15B is a schematic view of the shadow mask used when forming the p-type amorphous semiconductor layer in the third embodiment as viewed from above. FIG. 16 is a schematic view of the semiconductor substrate according to the third embodiment as viewed from above. FIG. 17 is a cross-sectional view illustrating a configuration of a photoelectric conversion element according to Embodiment 4. FIG. 18 is a process diagram showing a method of manufacturing the photoelectric conversion element shown in FIG. FIG. 19 is a process diagram showing a method of manufacturing the photoelectric conversion element shown in FIG. FIG. 20 is a process diagram showing a method for manufacturing the photoelectric conversion element shown in FIG. 17. FIG. 21 is a process diagram showing a method of manufacturing the photoelectric conversion element shown in FIG. FIG. 22 is a schematic diagram illustrating a configuration of a photoelectric conversion module including the photoelectric conversion element according to the fifth embodiment. FIG. 23 is a schematic diagram illustrating a configuration of a photovoltaic power generation system including the photoelectric conversion element according to the sixth embodiment. 24 is a schematic diagram showing the configuration of the photoelectric conversion module array shown in FIG. FIG. 25 is a schematic diagram illustrating a configuration of another photovoltaic power generation system including the photoelectric conversion element according to the sixth embodiment. FIG. 26 is a schematic diagram illustrating a configuration of a photovoltaic power generation system including the photoelectric conversion element according to the seventh embodiment. FIG. 27 is a schematic diagram illustrating a configuration of another photovoltaic power generation system including the photoelectric conversion element according to the seventh embodiment.

  A photoelectric conversion element according to an embodiment of the present invention includes a semiconductor substrate, a first amorphous semiconductor layer having a first conductivity type formed on one surface of the semiconductor substrate, and one of the semiconductor substrates. A second amorphous layer formed on the surface and adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type A semiconductor layer; a texture structure formed on at least a part of one surface of the semiconductor substrate; and at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer on the texture structure. A light scattering layer including the amorphous semiconductor layer (first configuration).

  According to the first configuration, a texture structure is formed on at least a part of one surface of the semiconductor substrate, and at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer is formed on the texture structure. A light scattering layer including an amorphous semiconductor layer is included. Since the reflectance of the light scattering layer becomes substantially uniform due to the texture structure in the light scattering layer, the position of the light scattering layer can be easily specified. Therefore, the position of at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer in the light scattering layer can be specified, and the first amorphous semiconductor layer and the second amorphous semiconductor layer are The first amorphous semiconductor layer and the second amorphous semiconductor layer can be formed so as not to overlap.

  According to a second configuration, in the first configuration, the light scattering layer includes a region where the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed on one surface of the semiconductor substrate. It is good also as being an alignment part formed in a different region and used for adjusting the position when forming one of the first amorphous semiconductor layer and the second amorphous semiconductor layer.

  According to the second configuration, the alignment unit is formed in a region different from a region where the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed, and the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed. It is used to adjust the position when forming one of the amorphous semiconductor layers. Therefore, compared with the case where the alignment part is formed in the region where the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed, the position of the alignment part can be easily specified, The first amorphous semiconductor layer and the second amorphous semiconductor layer can be formed at more appropriate positions so as not to overlap with the second amorphous semiconductor layer.

  According to a third configuration, in the second configuration, the alignment unit may include identification information for identifying the photoelectric conversion element.

  According to the third configuration, the photoelectric conversion element can be identified by the identification information of the alignment unit.

  According to a fourth configuration, in the first configuration, the light scattering layer is formed in a region where at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer is formed. It may be an alignment part for use in adjusting the position when forming one of the amorphous semiconductor layer and the second amorphous semiconductor layer.

  According to the fourth configuration, as compared with the case where the alignment portion is formed in a region different from the region where the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed, the first portion on one surface of the semiconductor substrate is formed. A region where the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed can be enlarged.

  According to a fifth configuration, in the first configuration, the light scattering layer is formed in a region where at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer is formed. It may be an inspection part for use in inspection of the position where the amorphous semiconductor layer and the second amorphous semiconductor layer are formed.

  According to the fifth configuration, it is easy to specify the position where at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer is formed by the texture structure in the inspection unit. It can be inspected whether the semiconductor layer and the second amorphous semiconductor layer are formed at appropriate positions.

  According to a sixth configuration, in any one of the first to fifth configurations, the light scattering layer further includes an intrinsic amorphous semiconductor layer between the one semiconductor layer and one surface of the semiconductor substrate. It may be included.

  According to the sixth configuration, when the amorphous semiconductor layer in the light scattering layer is formed first, the thickness of the light scattering layer is thicker than the region where the amorphous semiconductor layer is not formed. The contrast of the light scattering layer is increased. As a result, the position where the light scattering layer is formed can be more easily specified, and an amorphous semiconductor layer formed later can be formed at a more appropriate position.

  According to a seventh configuration, in any one of the first to sixth configurations, when the texture structure is viewed in plan, an average diameter of circumscribed circles of the convex portions of the texture structure is less than 15 μm. Also good.

  According to the sixth configuration, since the amount of reflected light from one surface of the semiconductor substrate is reduced, the position of the alignment unit can be easily specified.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. Further, in order to make the explanation easy to understand, in the drawings referred to below, the configuration is shown in a simplified or schematic manner, or some components are omitted. Further, the dimensional ratio between the constituent members shown in each drawing does not necessarily indicate an actual dimensional ratio.

  In this specification, the amorphous semiconductor layer may include a microcrystalline phase. The microcrystalline phase includes crystals having an average particle diameter of 1 to 50 nm.

[Embodiment 1]
FIG. 1A is a schematic view of the photoelectric conversion element according to Embodiment 1 as viewed from above. Moreover, FIG. 1B is sectional drawing which shows the structure of the photoelectric conversion element 10 which cut | disconnected the photoelectric conversion element 10 shown to FIG. 1A by the AA line. Referring to FIG. 1A, in photoelectric conversion element 10, n-type amorphous semiconductor layers 4 and p-type amorphous semiconductor layers 5 are alternately arranged in the in-plane direction of one surface of semiconductor substrate 1. .
An alignment mark 4M is formed on one surface of the semiconductor substrate 1 in a region different from the region where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed. Hereinafter, a specific configuration of the photoelectric conversion element 10 will be described.

  1A and 1B, the photoelectric conversion element 10 includes a semiconductor substrate 1, an antireflection film 2, a passivation film 3, an n-type amorphous semiconductor layer 4, and a p-type amorphous semiconductor layer 5. Electrodes 6 and 7, a protective film 8, and an alignment mark 4M.

  Sunlight is incident from the surface of the semiconductor substrate 1 on which the antireflection film 2 is formed. Hereinafter, the surface on which the antireflection film 2 is formed is referred to as a “light-receiving surface”, and the surface on which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed is referred to as a “back surface”.

  The semiconductor substrate 1 is made of, for example, an n-type single crystal silicon substrate. The semiconductor substrate 1 has a thickness of 100 to 150 μm, for example. The semiconductor substrate 1 has texture structures formed on both sides of the substrate as shown in FIG. The size of the texture in this embodiment is less than 15 μm. Details of the texture size will be described later.

  The antireflection film 2 is disposed in contact with the light receiving surface of the semiconductor substrate 1.

  The passivation film 3 is disposed in contact with the back surface of the semiconductor substrate 1.

  The n-type amorphous semiconductor layer 4 is disposed in contact with the passivation film 3.

  The p-type amorphous semiconductor layer 5 is in contact with the passivation film 3 and is disposed adjacent to the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1. More specifically, the p-type amorphous semiconductor layer 5 is arranged at a desired distance from the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1.

  The n-type amorphous semiconductor layers 4 and the p-type amorphous semiconductor layers 5 are alternately arranged in the in-plane direction of the semiconductor substrate 1.

  Although alignment mark 4M is not shown in FIG. 1B, alignment mark 4M includes the same semiconductor layer as n-type amorphous semiconductor layer 4, and is the same as p-type amorphous semiconductor layer 5 above alignment mark 4M. A semiconductor layer is deposited. Although a specific method for manufacturing the photoelectric conversion element 10 will be described later, in this embodiment, after the n-type amorphous semiconductor layer 4 is formed, the p-type amorphous semiconductor layer 5 is formed. The alignment mark 4M is used for adjusting the position of a shadow mask used when the p-type amorphous semiconductor layer 5 is formed.

  In the present embodiment, alignment mark 4M is an example of a light scattering layer. The light scattering layer includes a texture structure formed on at least a part of the back surface of the semiconductor substrate 1 and the same amorphous semiconductor layer as at least one of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. Including. In the present embodiment, the alignment mark 4M functions as an alignment unit used for adjusting the position of the shadow mask when the p-type amorphous semiconductor layer 5 is formed.

  The electrode 6 is disposed on the n-type amorphous semiconductor layer 4 in contact with the n-type amorphous semiconductor layer 4.

  The electrode 7 is disposed on the p-type amorphous semiconductor layer 5 in contact with the p-type amorphous semiconductor layer 5.

  The protective film 8 is disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7. More specifically, the protective film 8 includes the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrode between the adjacent n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5. 6 and 7 and a portion of the passivation film 3 disposed between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. . The protective film 8 has an opening 8A on the electrodes 6 and 7, and is formed in a region of 5 μm or more from the ends of the electrodes 6 and 7 toward the inside of the electrodes 6 and 7.

  The antireflection film 2 is made of, for example, a silicon nitride film and has a film thickness of, for example, 60 nm. An intrinsic amorphous semiconductor layer or an n-type or p-type conductive amorphous semiconductor layer may be inserted between the antireflection layer 2 and the light receiving surface. In this case, it is preferable because the passivation property of the light receiving surface can be improved.

  The passivation film 3 is made of, for example, any of amorphous silicon, amorphous silicon oxide, amorphous silicon nitride, amorphous silicon oxynitride, and polycrystalline silicon.

  In the case where the passivation film 3 is made of an oxide of amorphous silicon, the passivation film 3 may be made of a silicon thermal oxide film or formed by a vapor phase film forming method such as a plasma CVD (Chemical Vapor Deposition) method. It may be made of a silicon oxide.

  The passivation film 3 has a thickness of 1 to 20 nm, for example, and preferably has a thickness of 3 to 8 nm. When the passivation film 3 is made of a silicon insulating film, the passivation film 3 has a film thickness that allows carriers (electrons and holes) to tunnel. In the first embodiment, the passivation film 3 is made of a silicon thermal oxide film, and the thickness of the passivation film 3 is set to 2 nm.

  The n-type amorphous semiconductor layer 4 is an amorphous semiconductor layer having n-type conductivity and containing hydrogen. The n-type amorphous semiconductor layer 4 includes, for example, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, and n-type amorphous silicon nitride. N-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide, and the like. The n-type amorphous semiconductor layer 4 includes, for example, phosphorus (P) as an n-type dopant. The n-type amorphous semiconductor layer 4 has a thickness of 5 to 50 nm, for example.

  The p-type amorphous semiconductor layer 5 is an amorphous semiconductor layer having p-type conductivity and containing hydrogen. The p-type amorphous semiconductor layer 5 includes, for example, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, and p-type amorphous silicon nitride. , P-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, and the like. The p-type amorphous semiconductor layer 5 includes, for example, boron (B) as a p-type dopant. The p-type amorphous semiconductor layer 5 has a thickness of 5 to 50 nm, for example.

[Definition of texture size]
Here, the texture size will be described. In the present specification, the texture size means a size in a state in which the main surface of the semiconductor substrate 1 is viewed in a plane, that is, in a state viewed from vertically above the main surface of the semiconductor substrate 1. As a specific example of the texture, there is a pyramidal (quadrangular pyramid or quadrangular frustum-shaped) uneven structure obtained by performing anisotropic etching on an n-type single crystal silicon substrate having a (100) principal surface. is there. As shown in FIG. 2, the actual texture has a plurality of pyramidal irregularities of various sizes and shapes. This unevenness includes overlapping and deformed ones.

  In the present embodiment, when the texture is viewed in plan, the average value of the diameter of the circumscribed circle of the texture convex portion is defined as the texture size. Here, the size of the texture was obtained by the following method.

  A region having a size of 100 μm × 100 μm is extracted from the main surface of the semiconductor substrate 1, and the oblique line length r is long among the oblique line lengths (the oblique line length in plan view) r of the side surface of the pyramidal unevenness included in the extracted region. Twenty (r1, r2,..., R20) are detected in order from the one. Then, the size of the texture structure is set to twice the average value rave of the detected 20 oblique line lengths r (r1, r2,..., R20). This is because, in a region of 100 μm × 100 μm in the main surface of the semiconductor substrate 1, when the texture is viewed in plan, the diameter R of the circumscribed circle of the pyramid-shaped convex portion is 20 in order from the longest ( R1, R2,..., R20) are detected and equal to the average length of the diameters R of the 20 circumscribed circles detected.

  The size of the texture may be defined based on the length of one side of the bottom surface of the pyramidal unevenness, or the size of the texture may be defined based on the height of the pyramidal unevenness. For example, when the shape of the pyramidal irregularities is a quadrangular pyramid having a square bottom surface, the length a of one side of the bottom surface has a relationship of a diagonal line length r of the side surface in a plan view and a = 2 × r / √2. is there. When the angle θ formed between the bottom surface and the oblique side of the side surface is the texture inclination angle, the height b has a relationship of b = r × tan θ.

  Next, specific structures of the electrodes 6 and 7 and the protective film 8 will be described. FIG. 3 is an enlarged view of the electrodes 6 and 7 and the protective film 8 shown in FIG. 3A is an enlarged view of a portion where the electrode 6 is formed, and FIG. 3B is an enlarged view of a portion where the electrode 7 is formed. In FIG. 3, in order to make the structures of the electrodes 6, 7 and the protective film 8 easy to understand, the back surface of the semiconductor substrate 1 is flat, and the n-type amorphous semiconductor layer 4 and the flat passivation film 3 are formed on the flat passivation film 3. The structure in which the p-type amorphous semiconductor layer 5 is formed is illustrated. Actually, the passivation film 3 is formed on the back surface of the textured semiconductor substrate 1, and the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed on the passivation film 3 having an uneven shape. Is formed.

  As shown in FIG. 3A, the electrode 6 includes conductive layers 6a and 6b. Conductive layer 6 a is disposed in contact with n-type amorphous semiconductor layer 4. The conductive layer 6b is disposed in contact with the conductive layer 6a. When the width of the opening 8A of the protective film 8 is L and the distance from the ends of the electrodes 6 and 7 to the opening 8A is H, the conductive layers 6a and 6b are in-plane with the n-type amorphous semiconductor layer 4. In the direction, the n-type amorphous semiconductor layer 4 is formed in a range of H + L / 2 on both sides from the center. The width L is, for example, 20 μm or more, and preferably 100 μm or more. By setting the width L to such a value, the adhesion between the external wiring and the electrodes 6 and 7 can be secured, and the contact resistance can be lowered. The distance H is, for example, 5 μm or more in consideration of the adhesion between the electrodes 6 and 7 and the protective film 8.

  As shown in FIG. 3B, the electrode 7 includes conductive layers 7a and 7b. Conductive layer 7 a is disposed in contact with p-type amorphous semiconductor layer 5. The conductive layer 7b is disposed in contact with the conductive layer 7a. The conductive layers 7 a and 7 b are formed in a range of H + L / 2 on both sides from the center of the p-type amorphous semiconductor layer 5 in the in-plane direction of the p-type amorphous semiconductor layer 5.

  As a result, each of the electrodes 6 and 7 has a length of 2H + L in the in-plane direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

  As shown in FIGS. 3A and 3B, the protective film 8 has, for example, a two-layer structure of protective layers 8a and 8b. When the protective film 8 is formed on the n-type amorphous semiconductor layer 4, the protective layer 8 a is disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4 and the electrode 6. The protective layer 8b is disposed in contact with the protective layer 8a. When the protective film 8 is formed on the p-type amorphous semiconductor layer 5, the protective layer 8 a is disposed in contact with the passivation film 3, the p-type amorphous semiconductor layer 5 and the electrode 7. The protective layer 8b is disposed in contact with the protective layer 8a.

  In the in-plane direction of the n-type amorphous semiconductor layer 4, a region outside the n-type amorphous semiconductor layer 4 from the end of the electrode 6 is referred to as a gap region G 1, and the p-type amorphous semiconductor layer 5 A region outside the end of the electrode 7 in the in-plane direction of the p-type amorphous semiconductor layer 5 is referred to as a gap region G2. As a result, the gap region G1 exists on both sides of the n-type amorphous semiconductor layer 4 in the in-plane direction of the n-type amorphous semiconductor layer 4. In addition, a gap region G <b> 2 exists on both sides of the p-type amorphous semiconductor layer 5 in the in-plane direction of the p-type amorphous semiconductor layer 5.

  As a result of the protective film 8 being disposed in contact with the passivation film 3, the n-type amorphous semiconductor layer 4 and the electrode 6, and being disposed in contact with the passivation film 3, the p-type amorphous semiconductor layer 5 and the electrode 7, the semiconductor In the region of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 adjacent in the in-plane direction of the substrate 1, there is a gap region G (= G1 + G2), and the protective film 8 is shown in FIG. Thus, the electrodes 6 and 7 and the gap region G are formed. The gap region G is a region where the passivation film 3, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are exposed, and has a width of 20 μm to 500 μm, for example.

  When the electrodes 6 and 7 are made of, for example, silver (Ag) or aluminum (Al), the reflectance of the electrodes 6 and 7 is 90% or more. Light on a long wavelength region of about 800 to 1200 nm reaches the back surface of the semiconductor substrate 1. When light incident from the light receiving surface of the semiconductor substrate 1 enters the regions n and p where the electrodes 6 and 7 are provided, the light is reflected by the electrodes 6 and 7 and returns to the semiconductor substrate 1 to be absorbed by the semiconductor substrate 1. Is done. However, when light is incident on the gap region G where the electrodes 6 and 7 are not provided (see FIG. 1), there is no reflection by the electrodes 6 and 7, so that the light passes through the back side of the semiconductor substrate 1 and the incident light is transmitted. It may not be used effectively. If the width of the gap region G increases, light that is not reflected by the electrodes 6 and 7 increases, which is not preferable. For this reason, the width of the gap region G is preferably 500 μm or less, and more preferably 300 μm or less.

  Each of the conductive layers 6a and 7a is made of a transparent conductive film. The transparent conductive film is made of, for example, ITO (Indium Tin Oxide), ZnO, and IWO (Indium Tungsten Oxide).

  Each of the conductive layers 6b and 7b is made of metal. Examples of the metal include silver (Ag), nickel (Ni), aluminum (Al), copper (Cu), tin (Sn), platinum (Pt), gold (Au), chromium (Cr), tungsten (W), It consists of a laminated film of two or more layers of any of cobalt (Co) and titanium (Ti), or alloys thereof, or these metals.

  As the conductive layers 6a and 7a, it is preferable to use transparent conductive films having good adhesion to the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively. As the conductive layers 6b and 7b, conductive films It is preferable to use a metal having a high rate.

  The film thickness of each of the conductive layers 6a and 7a is, for example, 3 to 100 nm. The film thickness of each of the conductive layers 6b and 7b is preferably 50 nm or more. In Embodiment 1, for example, the film thickness is 0.8 μm.

  In the first embodiment, the electrode 6 may be composed only of the conductive layer 6b, and the electrode 7 may be composed only of the conductive layer 7b. In this case, there are no conductive layers 6a and 7a, and the conductive layers 6b and 7b are in contact with the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively.

  In the case where the conductive layers 6a and 7a are not provided, the conductive layers 6b and 7b are formed of metal films and have adhesiveness with the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 which are the base layers, respectively. A high metal is preferred. For example, the conductive layers 6b and 7b are made of Ti, Ni, Al, Cr, etc., and are a laminate of an adhesion layer having a film thickness of about 1 to 10 nm and a light reflecting metal mainly composed of Al, Ag, or the like. Consists of structure.

  Further, since the conductive layers 6 b and 7 b are in contact with the protective film 8, it is necessary to consider the adhesion with the protective film 8. When an oxide film such as silicon, aluminum, titanium and zirconia, a nitride film of silicon and aluminum, an oxynitride film of silicon and aluminum, or the like is used as the protective film 8, the surface of the conductive layers 6b and 7b on the protective film 8 side is , Al, indium (In), Ti, Ni, Cu, Cr, W, Co, palladium (Pd), and Sn are preferable.

  Furthermore, each of the electrodes 6 and 7 may consist of a single film of a transparent conductive film. In this case, the transparent conductive film is made of the above-described ITO or the like.

  Each of the protective layers 8a and 8b is made of an inorganic insulating film. The inorganic insulating film is made of an oxide film, a nitride film, an oxynitride film, or the like.

  The oxide film is made of an oxide film such as silicon, aluminum, titanium, zirconia, hafnium, zinc, tantalum, and yttrium.

  The nitride film is made of a nitride film such as silicon and aluminum.

  The oxynitride film is made of an oxynitride film such as silicon and aluminum.

  The protective layer 8b is made of an inorganic insulating film different from the protective layer 8a. That is, two types of films are selected from the above-described inorganic insulating films to form the protective layers 8a and 8b.

  Moreover, the protective layer 8a may consist of a semiconductor layer, and the protective layer 8b may consist of the inorganic insulating film mentioned above.

  In this case, the semiconductor layer is an amorphous semiconductor layer. The amorphous semiconductor layer is made of amorphous silicon, amorphous silicon germanium, amorphous germanium, amorphous silicon carbide, amorphous silicon nitride, amorphous silicon oxide, amorphous silicon oxynite. It consists of a ride and amorphous silicon carbon oxide. Since the higher insulation can suppress the leakage between the electrodes 6 and 7, the protective layer 8a is preferably made of an intrinsic amorphous semiconductor layer. For example, the protective layer 8a is made of intrinsic amorphous silicon, and the protective layer 8b is made of a silicon nitride film.

  However, when the protective layer 8b is made of an insulating film, the protective layer 8a may be made of an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer.

  The protective layer 8b is preferably made of a dielectric film having a positive fixed charge. The dielectric film having a positive fixed charge is, for example, a silicon nitride film and a silicon oxynitride film.

  Since the semiconductor substrate 1 is made of n-type single crystal silicon, when the protective layer 8b is made of a dielectric film having a positive fixed charge, the protective layer 8b applies an electric field to holes that are minority carriers, and the gap The lifetime of minority carriers (holes) in the region G can be maintained long.

  The protective film 8 is not limited to a two-layer structure, and may be a single layer or a multilayer structure of two or more layers.

  When the protective film 8 is composed of a single layer, the protective film 8 is composed of one kind of film selected from the inorganic insulating films described above.

  When the protective film 8 has a multilayer structure, the protective film 8 includes the protective layers 8a and 8b described above in the multilayer structure.

  As described above, when the protective film 8 has a two-layer structure, the protective layer 8a is formed of an amorphous semiconductor layer, and the protective layer 8b is formed of an insulating film, whereby the n-type amorphous semiconductor layer 4 and This is preferable because the passivation property for the p-type amorphous semiconductor layer 5 and the insulation between the electrodes 6 and 7 can be compatible.

  When the semiconductor substrate 1 is made of an n-type silicon substrate, the protective layer 8b is formed of a dielectric film having a positive fixed charge, so that an electric field is applied to the gap region, and minority carriers (holes) in the gap region are formed. Since lifetime can be lengthened, it is further preferable.

  Further, when the above-described inorganic insulating film is included in the multilayer structure of the protective film 8, it diffuses into the amorphous semiconductor layers (n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5). Since the moisture-proof effect which prevents a water | moisture content etc. can be acquired, it is preferable. Among the inorganic insulating films described above, a silicon nitride film and a silicon oxynitride film are particularly preferable because they have a particularly high moisture resistance as compared with other inorganic insulating films. When an n-type silicon substrate is used, moisture resistance and the electric field effect due to positive fixed charges can be obtained together, so that both long-term reliability and high efficiency of the photoelectric conversion element 10 are achieved. can do.

  For example, when the protective film 8 is a multilayer film having a two-layer structure or more, for example, a three-layer structure, one protective layer (a protective layer in contact with the n-type amorphous semiconductor layer 4 or the p-type amorphous semiconductor layer 5). Is made of an amorphous semiconductor layer, and the remaining two protective layers are made of two types of films selected from inorganic insulating films.

  Further, when the protective film 8 is composed of a single layer or multiple layers, the protective film 8 may have a structure in which an organic insulating film or the like is formed on the inorganic insulating film described above.

  The organic substance includes, for example, an imide resin, an epoxy resin, a fluororesin, a polycarbonate, a liquid crystal polymer, and the like.

  The imide resin is, for example, polyimide. The fluororesin is, for example, polytetrafluoroethylene (PTFE). The organic substance may be a resist formed by screen printing.

  FIG. 4 is a sectional view showing a detailed structure of the n-type amorphous semiconductor layer 4 shown in FIG. This figure shows a structure in which the back surface of the semiconductor substrate 1 is flat and an n-type amorphous semiconductor layer 4 is formed on the flat passivation film 3. A texture structure is formed on the back surface of the substrate 1.

  Referring to FIG. 4, n-type amorphous semiconductor layer 4 has a flat region FT and a film thickness reduction region TD in the in-plane direction of n-type amorphous semiconductor layer 4. The flat region FT is a portion of the n-type amorphous semiconductor layer 4 that has the thickest film thickness and is substantially constant.

  When the point at both ends of the flat region FT is A, and the point at which the film thickness decrease rate changes from the first decrease rate to the second decrease rate larger than the first decrease rate is B point, the film thickness The decrease region TD is a region from point A to point B in the in-plane direction of the n-type amorphous semiconductor layer 4.

  The film thickness reduction region TD is disposed on both sides of the flat region FT in the in-plane direction of the n-type amorphous semiconductor layer 4.

  The n-type amorphous semiconductor layer 4 has the reduced thickness region TD because the n-type amorphous semiconductor layer 4 is formed by plasma CVD using a shadow mask, as will be described later. Since the film thickness reduction region TD has a thinner film thickness than the flat region FT, the dopant concentration of the film thickness reduction region TD is higher than the dopant concentration of the flat region FT.

  The electrode 6 is disposed in contact with the entire flat region FT of the n-type amorphous semiconductor layer 4 and a part of the film thickness reduction region TD.

  The p-type amorphous semiconductor layer 5 also has the same structure as the n-type amorphous semiconductor layer 4 shown in FIG. The electrode 7 is disposed in contact with the entire flat region FT of the p-type amorphous semiconductor layer 5 and a part of the film thickness reduction region TD.

  As a result, the resistance when carriers (electrons) reach the electrode 6 through the n-type amorphous semiconductor layer 4 is n-type amorphous semiconductor layer having a constant film thickness in the in-plane direction of the passivation film 3. As compared with the case where is formed, the resistance becomes low. The resistance when carriers (holes) reach the electrode 7 through the p-type amorphous semiconductor layer 5 is a p-type amorphous semiconductor layer having a constant film thickness in the in-plane direction of the passivation film 3. As compared with the case where is formed, the resistance becomes low. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

  The electrode 6 may be in contact with the entire thickness reducing region TD of the n-type amorphous semiconductor layer 4, and the electrode 7 may be in contact with the entire thickness reducing region TD of the p-type amorphous semiconductor layer 5. You may touch.

  FIG. 5 is a cross-sectional view showing another detailed structure of the n-type amorphous semiconductor layer 4 shown in FIG. Referring to FIG. 5A, the photoelectric conversion element 10 includes an n-type amorphous semiconductor layer 41 instead of the n-type amorphous semiconductor layer 4, and includes an electrode 61 instead of the electrode 6. Also good.

  In the n-type amorphous semiconductor layer 41, the point at which the film thickness is maximum is C point, and the film thickness decrease rate changes from the first decrease rate to the second decrease rate larger than the first decrease rate. Let the point be point D. As a result, the film thickness reduction region TD is a region from the point C to the point D in the in-plane direction of the n-type amorphous semiconductor layer 41.

  The n-type amorphous semiconductor layer 41 has two thickness reduction regions TD in the in-plane direction of the n-type amorphous semiconductor layer 41. The two film thickness reduction regions TD are arranged in contact with each other in the in-plane direction of the n-type amorphous semiconductor layer 41.

  The electrode 61 is disposed in contact with a part of one film thickness reduction region TD and a part of the other film thickness reduction region TD among the two film thickness reduction regions TD.

  The photoelectric conversion element 10 includes a p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 41 shown in FIG. 5A instead of the p-type amorphous semiconductor layer 5. Also good.

  As a result, the resistance when carriers (electrons) reach the electrode 61 via the n-type amorphous semiconductor layer 41 is an n-type amorphous semiconductor layer having a constant film thickness in the in-plane direction of the passivation film 3. As compared with the case where is formed, the resistance becomes low. The resistance when carriers (holes) reach the electrode through the p-type amorphous semiconductor layer having the same structure as that of the n-type amorphous semiconductor layer 41 is constant in the in-plane direction of the passivation film 3. The resistance is lower than when a p-type amorphous semiconductor layer having a film thickness is formed. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

  Note that the electrode 61 is in contact with the entire two thickness reduction regions TD in the n-type amorphous semiconductor layer 41 and the p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 41. May be arranged.

  Referring to FIG. 5B, the photoelectric conversion element 10 includes an n-type amorphous semiconductor layer 42 instead of the n-type amorphous semiconductor layer 4, and includes an electrode 62 instead of the electrode 6. Also good.

  In the n-type amorphous semiconductor layer 42, the point at which the film thickness is maximum is taken as point E, and the film thickness decrease rate changes from the first rate of decrease to a second rate of decrease that is greater than the first rate of decrease. Let the point be the F point, and let the point where the sign of the rate of change of the film thickness changes from negative to positive.

  As a result, the film thickness reduction region TD1 is a region from the point E to the point F in the in-plane direction of the n-type amorphous semiconductor layer 42, and the film thickness reduction region TD2 is the region of the n-type amorphous semiconductor layer 42. This is the region from point E to point G in the in-plane direction.

  The n-type amorphous semiconductor layer 42 has two film thickness reduction regions TD1 and two film thickness reduction regions TD2 in the in-plane direction of the n-type amorphous semiconductor layer 42.

  The two film thickness reduction regions TD2 are arranged so that the film thickness distribution in the in-plane direction of the n-type amorphous semiconductor layer 42 is symmetric with respect to a line passing through the G point. The two film thickness reduction regions TD1 are arranged on both sides of the two film thickness reduction regions TD2 in the in-plane direction of the n-type amorphous semiconductor layer 42.

  The electrode 62 is disposed in contact with the entire two film thickness reduction regions TD2, a part of one film thickness reduction region TD1, and a part of the other film thickness reduction region TD1.

  The photoelectric conversion element 10 includes a p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 42 shown in FIG. 5B instead of the p-type amorphous semiconductor layer 5. Also good.

  As a result, the resistance when carriers (electrons) reach the electrode 62 via the n-type amorphous semiconductor layer 42 is an n-type amorphous semiconductor layer having a constant thickness in the in-plane direction of the passivation film 3. As compared with the case where is formed, the resistance becomes low. The resistance when carriers (holes) reach the electrode through the p-type amorphous semiconductor layer having the same structure as that of the n-type amorphous semiconductor layer 42 is constant in the in-plane direction of the passivation film 3. The resistance is lower than when a p-type amorphous semiconductor layer having a film thickness is formed. Therefore, the conversion efficiency of the photoelectric conversion element 10 can be improved.

  Note that the electrode 62 includes an n-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer having the same structure as the n-type amorphous semiconductor layer 42. You may arrange | position in contact with the whole of two film thickness reduction area | regions TD2.

  As described above, the photoelectric conversion element 10 includes the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer having the film thickness reduction region TD (TD1, TD2). In the embodiment of the present invention, the film thickness reduction region is one of the film thickness reduction regions TD, TD1, and TD2.

  Accordingly, the first point is the point where the film thickness of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer is the maximum, and the in-plane of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer In the direction, a point at which the film thickness decrease rate changes from the first decrease rate to a second decrease rate larger than the first decrease rate, or a point at which the sign of the film thickness change rate changes from negative to positive. When the second point is taken, the film thickness reduction region is a region from the first point to the second point in the in-plane direction of the n-type amorphous semiconductor layer or the p-type amorphous semiconductor layer.

  In the embodiment of the present invention, it is sufficient that at least one of n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5 has a film thickness reduction region.

  Next, a method for manufacturing the photoelectric conversion element 10 will be described. 6 to 10 are first to fifth process diagrams showing a method for manufacturing the photoelectric conversion element 10 shown in FIG. 1, respectively.

  Referring to FIG. 6, when manufacturing of photoelectric conversion element 10 is started, a wafer having a thickness of 100 to 300 μm is cut out from bulk silicon by a wire saw. Then, etching for removing the damaged layer on the surface of the wafer and etching for adjusting the thickness are performed to prepare the semiconductor substrate 1 '(see step (a) in FIG. 6).

  In general, a silicon substrate having a texture structure is manufactured by etching a silicon substrate obtained by slicing a silicon ingot with a wire saw or the like. As the substrate for forming the texture, single crystal silicon using a loose abrasive slice substrate is mainly used. However, the same texture can be formed even on the fixed abrasive slice substrate because of cost reduction and improvement of the slicing technique.

Etching of the semiconductor substrate 1 ′ can be performed by wet etching using an alkaline etchant. In the case of a sodium hydroxide solution, this etching proceeds by a reaction such as the following reaction formulas (1), (2), and (3).
Si + 2NaOH + H ₂ O → Na ₂ SiO ₃ + 2H ₂ (1)
2Si + 2NaOH + 3H ₂ O → Na ₂ Si ₂ O ₅ + 4H ₂ (2)
3Si + 4NaOH + 4H ₂ O → Na ₄ Si ₃ O ₈ + 6H ₂ (3)

  In order to form a texture structure on the surface of the semiconductor substrate 1 ′, anisotropic etching is performed by using, for example, an etching solution with a controlled etching rate. Formation of the texture structure on the surface of the semiconductor substrate 1 'is based on the following mechanism. The etching rate of the semiconductor substrate 1 ′ with the alkaline aqueous solution is the fastest on the (100) plane of silicon and the slowest on the (111) plane. Therefore, when the rate of texture etching is suppressed by adding a specific additive (hereinafter, also referred to as “etching inhibitor”) that can reduce the etching rate to the alkaline aqueous solution, the (100) surface of silicon. A crystal plane that is easily etched is preferentially etched, and a (111) plane having a slow etching rate remains on the surface. Since the (111) plane has an inclination of about 54 degrees with respect to the (100) plane, a pyramidal uneven structure composed of the (111) plane and its equivalent plane is formed at the final stage of the process. .

  However, depending on the etching conditions, a texture having an inclination of about 40-54 degrees may be formed, and (111) is not necessarily formed on the texture surface. Even in the present invention, the inclined surface of the texture does not have to be the (111) surface, and the inclination may be gentle.

  Alternatively, an etching solution obtained by adding isopropyl alcohol (hereinafter sometimes referred to as “IPA”) as an etching inhibitor to an aqueous solution of sodium hydroxide (NaOH) as an etching solution for texture formation may be used. This etching solution is heated to about 60 to 80 ° C., and the (100) plane silicon substrate is immersed for 10 to 30 minutes for etching.

  Also, by using an etching solution containing sodium hydroxide or potassium hydroxide, a specific additive such as lignin as an additive, and sodium bicarbonate or potassium bicarbonate, A texture structure having a height up to the top of the part of 1 μm or less can be formed. Thus, the texture size can be controlled by changing various conditions such as the temperature of the etching solution, the processing time, the type of etching inhibitor, the etching rate, and the type of substrate. Here, the etching conditions are set so that the texture size is 15 μm or less.

  In the present embodiment, after step (a) in FIG. 6, an alkali solution such as NaOH and KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%) is used for the semiconductor substrate 1 ′. And etch. As a result, both surfaces of the semiconductor substrate 1 ′ are anisotropically etched to form a texture structure having a texture size of 15 μm or less. (See step (b) in FIG. 6).

  Subsequently, the surface of the semiconductor substrate 1 is thermally oxidized to form an oxide film 11 on the light receiving surface of the semiconductor substrate 1 and a passivation film 3 is formed on the back surface (surface opposite to the light receiving surface) of the semiconductor substrate 1 (FIG. Step 6 (c)).

  The oxidation of the semiconductor substrate 1 may be either wet processing or thermal oxidation. In the case of wet oxidation, for example, the semiconductor substrate 1 is immersed in hydrogen peroxide, nitric acid, ozone water or the like, and then the semiconductor substrate 1 is heated at 800 to 1000 ° C. in a dry atmosphere. In the case of thermal oxidation, for example, the semiconductor substrate 1 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor.

  After the step (c) of FIG. 6, a silicon nitride film 12 is formed in contact with the oxide film 11 using sputtering, EB (Electron Beam) evaporation, TEOS, or the like. Thereby, the antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1 (see step (d) in FIG. 7).

  After the step (d) of FIG. 7, the semiconductor substrate 1 is put into the reaction chamber of the plasma apparatus, and the shadow mask 30 is disposed on the passivation film 3 of the semiconductor substrate 1 (see step (e) of FIG. 7).

  Here, the shadow mask 30 will be described. FIG. 11A is a schematic view of the shadow mask 30 as viewed from above. The shadow mask 30 has a plurality of openings 30a and openings 30b. The opening 30a is an opening for forming the n-type amorphous semiconductor layer 4 on the passivation film 3, and is formed at a certain distance from the adjacent opening 30a. The opening 30b is an opening for forming an alignment mark serving as a reference when the p-type amorphous semiconductor layer 5 is formed.

  The shadow mask 30 is made of, for example, stainless steel and is made of a metal mask having a thickness of 200 μm. The opening 30a has a substantially rectangular shape, and the opening 30b has a substantially square shape. The opening width w of the opening 30a is about 400 μm. Moreover, although the opening part 30b has a magnitude | size of 1.0 mm x 1.0 mm, the magnitude | size of 0.4 mm x 0.4 mm is more preferable.

The temperature of the semiconductor substrate 1 is set to 130 to 180 ° C., 0 to 100 sccm of hydrogen (H ₂ ) gas, 40 sccm of SiH ₄ gas, and 40 sccm of phosphine (PH ₃ ) gas are flowed into the reaction chamber, and the pressure in the reaction chamber Is set to 40 to 120 Pa. Thereafter, high frequency power (13.56 MHz) having an RF power density of 5 to 15 mW / cm ² is applied to the parallel plate electrodes. Note that the PH ₃ gas is diluted with hydrogen, and the concentration of the PH ₃ gas is, for example, 1%.

  As a result, n-type amorphous silicon is deposited in the region of the passivation film 3 that is not covered by the shadow mask 30, and the n-type amorphous semiconductor layer 4 and the alignment mark 4M are formed on the passivation film 3 (see FIG. Step (f) in FIG. 7).

When the shadow mask 30 is disposed on the passivation film 3, there is a gap between the shadow mask 30 and the passivation film 3. As a result, active species such as SiH and SiH ₂ decomposed by the plasma enter the gap between the shadow mask 30 and the passivation film 3, and an n-type amorphous material is also formed in a part of the region covered by the shadow mask 30. A semiconductor layer 4 is formed. Compared to the case where a shadow mask 30 is used to form a film on a semiconductor substrate on which no texture structure is formed, the number of wraparounds between the shadow mask 30 and the passivation film 3 increases. As a result, the n-type amorphous semiconductor layer 4 having the thickness reduction region TD is formed on the passivation film 3. An n-type amorphous silicon 31 is also deposited on the shadow mask 30.

  The width of the film thickness reduction region TD and the film thickness reduction rate in the n-type amorphous semiconductor layer 4 are the film formation pressure when the n-type amorphous semiconductor layer 4 is formed, the thickness of the shadow mask 30 and It is controlled by changing the opening width of the shadow mask 30. For example, when the thickness of the shadow mask 30 is increased, the width of the film thickness reduction region TD is increased.

  After the step (f) in FIG. 7, a shadow mask 40 is disposed on the passivation film 3, the n-type amorphous semiconductor layer 4 and the alignment mark 4M instead of the shadow mask 30 (see step (g) in FIG. 8). ).

  Here, the shadow mask 40 will be described. FIG. 11B is a schematic view of the shadow mask 40 as viewed from above. The shadow mask 40 includes a plurality of openings 40a for forming the p-type amorphous semiconductor layer 5 on the passivation film 3, and an alignment mark 4M formed on the passivation film 3 (FIG. 7F). And an alignment opening 40b for alignment.

  The opening 40a has a substantially rectangular shape, like the opening 30a of the shadow mask 30, and has an opening width w of about 400 μm. The inside of the alignment opening 40b is open, and four protrusions projecting inside the alignment opening 40b at positions that contact each side of the broken line frame 401b having the same size as the opening 30b of the shadow mask 30. 402b to 405b. The material and thickness of the shadow mask 40 are the same as those of the shadow mask 30.

  When the shadow mask 40 is arranged, the alignment mark 4M formed on the passivation film 3 is observed with an optical microscope, and the position of the alignment mark 4M is specified. In the present embodiment, a texture structure having a texture size of less than 15 μm is formed on the entire back surface of the semiconductor substrate 1. Therefore, the reflectance of the portion of the semiconductor substrate 1 under the alignment mark 4M is substantially uniform, and the position of the alignment mark 4M can be reliably specified with an optical microscope.

  After specifying the position of the alignment mark 4M, as shown in FIG. 11C, the shadow mask 40 is arranged so that the projections 402b to 405b of the alignment opening 40b of the shadow mask 40 are in contact with each side of the alignment mark 4M. . Thereby, the opening 40a of the shadow mask 40 is arranged at a position spaced apart from the n-type amorphous semiconductor layer 4 by a certain distance.

  In the step (g) of FIG. 8, the shadow mask 40 is illustrated as being separated from the passivation film 3, but the film thickness of the n-type amorphous semiconductor layer 4 is 5 as described above. Since it is very thin as ˜50 nm, the shadow mask 40 is actually arranged close to the passivation film 3.

Then, the temperature of the semiconductor substrate 1 is set to 130 to 180 ° C., and 0 to 100 sccm of H ₂ gas, 40 sccm of SiH ₄ gas, and 40 sccm of diborane (B ₂ H ₆ ) gas are allowed to flow into the reaction chamber. The pressure is set to 40 to 200 Pa. Thereafter, high frequency power (13.56 MHz) having an RF power density of 5 to 15 mW / cm ² is applied to the parallel plate electrodes. Note that B ₂ H ₆ gas is diluted with hydrogen, and the concentration of B ₂ H ₆ gas is, for example, 2%.

  As a result, p-type amorphous silicon is deposited in the region of the passivation film 3 not covered with the shadow mask 40. As a result, on the passivation film 3, p-type amorphous silicon 5M is deposited on the alignment mark 4M, and at a suitable position spaced apart from the n-type amorphous semiconductor layer 4, the p-type non-crystalline silicon 5M is deposited. A crystalline semiconductor layer 5 is formed (see step (h) in FIG. 8).

When the shadow mask 40 is disposed on the passivation film 3 and the n-type amorphous semiconductor layer 4, there is a gap between the shadow mask 40 and the passivation film 3. As a result, active species such as SiH and SiH ₂ decomposed by the plasma wrap around the gap between the shadow mask 40 and the passivation film 3, and the p-type amorphous material is also partly covered by the shadow mask 40. A semiconductor layer 5 is formed. Therefore, the p-type amorphous semiconductor layer 5 having the film thickness reduction region TD is formed on the passivation film 3. Also, the p-type amorphous silicon 32 is deposited on the shadow mask 40.

  The width of the film thickness reduction region TD and the film thickness reduction rate in the p-type amorphous semiconductor layer 5 are the film formation pressure when the p-type amorphous semiconductor layer 5 is formed, the thickness of the shadow mask 40, and It is controlled by changing the opening width of the shadow mask 40. For example, when the thickness of the shadow mask 40 is increased, the width of the film thickness reduction region TD is increased.

  When the shadow mask 40 is removed after the p-type amorphous silicon is deposited, the n-type amorphous semiconductor layers 4 and the p-type amorphous semiconductor layers 5 alternately arranged in the in-plane direction of the semiconductor substrate 1 are passivated. The p-type amorphous silicon 5M is formed on the alignment mark 4M while being formed on the film 3 (see step (i) in FIG. 8).

  After the step (i) in FIG. 8, the shadow mask 50 is arranged so that the opening is located on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 (step (j) in FIG. 9). reference). The shadow mask 50 has the same material and thickness as the shadow mask 30. The opening width is the sum of the width of the flat region FT of the n-type amorphous semiconductor layer 4 or the p-type amorphous semiconductor layer 5 and the width of the two film thickness reduction regions TD in the amorphous semiconductor layer. Set to

  After the step (j) of FIG. 9, conductive layers 6a and 7a and conductive layers 6b and 7b are sequentially deposited through a shadow mask 50. As a result, the electrodes 6 and 7 are deposited on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively (see step (k) in FIG. 9).

  The conductive layers 6a and 7a and the conductive layers 6b and 7b are formed by a sputtering method, a vapor deposition method, an ion plating method, a thermal CVD method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, a sol-gel method, or a method of spraying and heating a liquefied raw material. , And an inkjet method or the like.

  The conductive layers 6a and 7a are, for example, any one of ITO, IWO, and ZnO, and the conductive layers 6b and 7b have a two-layer structure of Ti (3 nm) / Al (500 nm).

ITO, for example, an ITO target doped with 0.5 to 4 wt% of SnO ₂ is supplied with argon gas or a mixed gas of argon gas and oxygen gas, and a substrate temperature of 25 to 250 ° C., 0.1 to 1.5 Pa. It is formed by performing the sputtering process at a pressure of 0.01 to 2 kW.

  ZnO is formed by performing sputtering treatment under the same conditions using a ZnO target doped with 0.5 to 4 wt% of Al instead of the ITO target.

  A two-layer structure of Ti / Al is formed by EB vapor deposition.

  In addition, the electrodes 6 and 7 may be formed by the plating film forming method using the conductive layers 6a and 7a as seed electrodes, respectively. In this case, the conductive layers 6b and 7b are made of, for example, any one of Ni, W, Co, Ti, Cr, alloys thereof, and alloys of these alloys with P and B. Also, Cu, Al, Sn, etc. can be formed on the conductive layers 6b, 7b by plating.

  After step (k) in FIG. 9, a shadow mask 60 is disposed on the electrodes 6 and 7 (see step (l) in FIG. 9). The shadow mask 60 has the same material and thickness as the shadow mask 30.

  Then, the protective film 8 is formed on the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7.

More specifically, an intrinsic amorphous semiconductor film and a silicon nitride film are formed from the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7 using plasma CVD. Deposit sequentially on top. In this case, for example, an intrinsic amorphous semiconductor film is formed using SiH ₄ gas as a material gas, and the thickness of the intrinsic amorphous semiconductor film is, for example, 10 nm. Further, for example, a silicon nitride film is formed using SiH ₄ gas and NH ₃ gas as material gases, and the thickness of the silicon nitride film is, for example, 120 nm. Thus, the photoelectric conversion element 10 is completed (see step (m) in FIG. 10).

  In the above-mentioned example, stainless steel is exemplified as the material of the shadow mask 30, 40, 50, 60. However, the material is not limited to stainless steel. For example, copper, nickel, nickel alloy (42 alloy, invar material, etc.) and molybdenum Etc. may be used. The shadow masks 30, 40, 50, 60 are not limited to metal masks, and may be any of glass masks, ceramic masks, organic film masks, and the like. Alternatively, a semiconductor substrate made of the same material as the semiconductor substrate 1 may be processed by etching to form a shadow mask. In this case, since the semiconductor substrate and the shadow mask are made of the same material, the thermal expansion coefficients are the same, and no shift occurs due to the difference in the thermal expansion coefficients. In consideration of the relationship with the thermal expansion coefficient of the semiconductor substrate 1 and the raw material cost, the material of the shadow masks 30, 40, 50, 60 is preferably 42 alloy. From the relationship of the thermal expansion coefficient with the semiconductor substrate 1, the material of the shadow mask 30, 40, 50, 60 has a thermal expansion coefficient of the semiconductor substrate 1 when the nickel composition is about 36% and the iron composition is 64%. The alignment error due to the difference in thermal expansion coefficient can be minimized.

  Moreover, regarding the thickness of the shadow mask 30, 40, 50, 60, it is preferable that it can be regenerated and used many times from the viewpoint of suppressing the running cost of production. In this case, the film deposited on the shadow mask 30, 40, 50, 60 can be removed using hydrofluoric acid or NaOH. Considering the number of times of reproduction, the thickness of the shadow masks 30, 40, 50, 60 is preferably 30 μm to 300 μm.

  Further, in the manufacturing method described above, it has been described that the intrinsic amorphous semiconductor film / silicon nitride film constituting the protective film 8 is continuously formed in one reaction chamber, but in the embodiment of the present invention, However, the present invention is not limited thereto, and after the intrinsic amorphous semiconductor layer is formed, the sample may be exposed to the atmosphere once so that a silicon nitride film is formed by a sputtering apparatus or another CVD apparatus.

  When the intrinsic amorphous semiconductor film / silicon nitride film constituting the protective film 8 is formed without being exposed to the atmosphere, it is preferable because contamination of organic substances or moisture in the atmosphere can be suppressed.

  Furthermore, the protective film 8 may be formed using EB vapor deposition, sputtering, laser ablation, CVD, and ion plating.

Further, in the embodiment of the present invention, after the passivation film 3 is formed, the passivation film 3 may be nitrided by a plasma CVD method using nitrogen (N ₂ ) gas to form a passivation film made of SiON. . As a result, diffusion of the dopant (B) in the p-type amorphous semiconductor layer 5 formed on the passivation film into the semiconductor substrate 1 can be suppressed. Even when a passivation film having a thickness that allows a tunnel current to flow is formed, it is preferable because diffusion of boron (B) can be effectively suppressed.

  As described above, a texture structure having a texture size of less than 15 μm is formed on the entire back surface of the semiconductor substrate 1. Since the reflectance of the back surface of the semiconductor substrate 1 becomes substantially uniform due to this texture structure, the alignment mark 4M formed together with the n-type amorphous semiconductor layer 4 on the passivation film 3 is observed with an optical microscope. The position of 4M can be specified reliably. Therefore, the positions of the protrusions 402b to 405b of the alignment opening 40b of the shadow mask 40 can be aligned with the alignment mark 4M as a reference, and the shadow mask 40 can be arranged at an appropriate position. As a result, the p-type amorphous semiconductor layer 5 can be formed at a certain distance from the n-type amorphous semiconductor layer 4, and the adjacent n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor can be formed. A gap region G can be formed between the quality semiconductor layers 5. In particular, n-type amorphous silicon has a lower contrast than that of p-type amorphous silicon when observed with an optical microscope. Therefore, after n-type amorphous semiconductor layer 4 is formed, p-type amorphous silicon is used. The above-described configuration is particularly effective when the quality semiconductor layer 5 is formed.

  In addition, when the film thickness difference between the alignment mark 4M and the other region is, for example, only the film thickness of the n-type amorphous semiconductor layer, it is difficult to recognize the boundary between the alignment mark 4M and the other region. However, the texture structure is formed under the boundary (outer edge) portion of the region where the n-type amorphous silicon is formed in the alignment mark 4M, so that the boundary portion of the n-type amorphous silicon in the alignment mark 4M is visually recognized. And the recognition accuracy of the alignment mark 4M is improved. As a result, the thickness of the n-type amorphous semiconductor layer 4 can be made thinner, the series resistance in the n-type amorphous semiconductor layer 4 can be reduced, and higher conversion efficiency can be realized. .

  Further, the sharpness of the texture edge when the back surface of the semiconductor substrate 1 is observed with an optical microscope differs depending on the texture size. This is because the greater the texture size, the greater the amount of film wrapping around the shadow mask. In the above example, the size of the texture formed on the back surface of the semiconductor substrate 1 is less than 15 μm. If the texture size is less than 15 μm, the amount of light reflected from the back surface of the semiconductor substrate 1 becomes small and the reflectance of the back surface becomes substantially uniform, so that the alignment mark 4M is easily recognized.

  Here, FIGS. 12A to 12D show optical microscope images of the alignment marks when the alignment marks are formed on the semiconductor substrates having different back surface states. (A) of FIG. 12 is an optical microscope image of the alignment mark when the back surface of the semiconductor substrate is a mirror surface. (B) of FIG. 12 is an optical microscope image of the alignment mark in the case of a flat surface on which the texture structure is not formed on the back surface of the semiconductor substrate. FIG. 12C is an optical microscope image of the alignment mark when a texture structure having a texture size of 1 μm is formed on the back surface of the semiconductor substrate. FIG. 12D is an optical microscope image of the alignment mark when a texture structure having a texture size of 15 μm is formed on the back surface of the semiconductor substrate. 12A to 12D, the image portion of the region A is a region where an alignment mark is formed, and the image portion of the region B is a region where the passivation film 3 is formed.

  In the case of FIG. 12A, since the back surface of the semiconductor substrate is a flat mirror surface at the atomic level, the reflectance of the semiconductor substrate is substantially uniform in the surface. Further, it becomes difficult for n-type amorphous silicon to enter the back side of the shadow mask when the n-type amorphous semiconductor layer 4 is formed, and as shown in FIG. And the alignment mark is easy to recognize.

  In the case of FIG. 12B, since the large optical contrast due to the dimples on the semiconductor substrate becomes a noise source, and since the back surface of the semiconductor substrate is a flat surface, the amount of reflected light from the semiconductor substrate is large. It is difficult to optically recognize this part.

  In FIG. 12C, the brightest region C indicated by the broken line frame is a mask alignment mark for a shadow mask when the p-type amorphous semiconductor layer 5 is formed. Since the texture structure is formed at the boundary portion of the region A where the alignment mark is formed, the amount of reflected light from the back surface of the semiconductor substrate is smaller than in the case of FIG. Becomes substantially uniform. As a result, it becomes easier to optically recognize the alignment mark than in the case of FIG.

  In the case of FIG. 12D, the texture size of the texture structure formed on the back surface of the semiconductor substrate is larger than in FIG. 12C, and the boundary of the region A where the alignment mark is formed is difficult to recognize. ing. This is because as the texture size increases, n-type amorphous silicon tends to wrap around the shadow mask when the n-type amorphous semiconductor layer 4 is formed. Therefore, it is found that the texture size of the texture structure formed on the back surface of the semiconductor substrate is preferably less than 15 μm, and when it is 15 μm or more, it is difficult to recognize the boundary portion of the alignment mark.

  Furthermore, the smaller the texture inclination angle θ, the closer the surface of the semiconductor substrate becomes to a flat surface and the higher the reflectance, so that the visibility of the alignment mark 4M decreases. Therefore, for example, by setting the texture inclination angle θ to 40 ° or more, the contrast ratio of the boundary of the alignment mark 4M is increased, and the alignment mark 4M is more easily recognized.

  A protective film 8 is formed between the adjacent electrodes 6 and 7 on the electrodes 6 and 7 and the gap region G (passivation film 3, n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5). The As a result, even when conductive dust adheres between the adjacent electrodes 6 and 7, a short circuit is prevented. Therefore, the reliability of the photoelectric conversion element 10 can be improved.

  Further, the electrodes 6 and 7 are covered with a protective film 8 in a region of 5 μm or more from the end toward the inside. As a result, it is possible to effectively prevent moisture from entering from the opening end of the protective film 8, and to prevent the protective film 8 from peeling off, thereby preventing a decrease in yield due to misalignment during production.

  Further, even when the adhesion between the semiconductor layer in contact with the electrodes 6 and 7 and the electrodes 6 and 7 is relatively weak, by covering the electrodes 6 and 7 with the protective film 8, the electrode peeling is effectively suppressed. This is preferable. That is, even an electrode material having poor adhesion to an amorphous semiconductor can be used by forming the protective film 8, and the metal selection range for the electrode is widened, so that the characteristics can be easily improved. Therefore, it is preferable. In a conventional heterojunction solar cell in which an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer and a TCO (transparent conductive film) are formed almost entirely on one surface of a semiconductor substrate, There is no break in TCO.

  However, when a plurality of layers such as an n-type amorphous semiconductor layer or a p-type amorphous semiconductor layer, a TCO, and an electrode are alternately formed as in the backside heterojunction solar cell in this embodiment, FIG. As shown, a large number of end portions of each layer are generated. When a peel test or the like is performed with such a configuration, there is a possibility of peeling from the end. However, it is preferable to form a texture structure on the surface of the semiconductor substrate 1 because an anchor effect is generated and peeling and the like are easily suppressed. Further, it is more preferable that the electrode end portion that is most easily peeled off is covered with a protective film, whereby peeling can be more effectively suppressed.

  Furthermore, in the gap region G, the passivation film 3, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are covered with a protective film 8. As a result, an effect of long-term stability of the photoelectric conversion element 10 can be obtained.

  FIG. 13A is a plan view seen from the back side of the photoelectric conversion element 10 shown in FIG. Referring to (a) of FIG. 13A, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are alternately arranged in the in-plane direction of the semiconductor substrate 1 at a desired interval. Electrodes 6 and 7 are disposed on n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5, respectively. As a result, a gap region G is formed between the adjacent electrodes 6 and 7.

  Referring to (b) of FIG. 13A, the protective film 8 is disposed on the gap region G and the peripheral region of the semiconductor substrate 1. On the electrodes 6 and 7, an opening 8A having a width L is formed. The electrodes 6 and 7 are connected to the wiring sheet through the opening 8A.

  In FIG. 13A (b), there is a region that is not covered with the protective film 8 in the peripheral portion of the semiconductor substrate 1, but in the photoelectric conversion element 10, the entire back surface of the semiconductor substrate 1 is protected. Most preferably, the film is covered with a film and a part of the electrodes 6 and 7 is exposed.

  FIG. 13B is a plan view of the wiring sheet. With reference to FIG. 13B, the wiring sheet 70 includes an insulating base 710 and wiring members 71 to 87.

  The insulating base material 710 may be an electrically insulating material and can be used without any particular limitation. The insulating base 710 is made of, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyvinyl fluoride (PVF), polyimide, and the like.

  The thickness of the insulating base 710 is not particularly limited, but is preferably 25 μm or more and 150 μm or less. The insulating base 710 may have a single layer structure or a multilayer structure of two or more layers.

  The wiring member 71 includes a bus bar portion 711 and finger portions 712. One end of the finger portion 712 is connected to the bus bar portion 711.

  The wiring member 72 includes a bus bar portion 721 and finger portions 722 and 723. One end of the finger portion 722 is connected to the bus bar portion 721. One end of the finger portion 723 is connected to the bus bar portion 721 on the opposite side of the connection portion between the bus bar portion 721 and the finger portion 722 with respect to the bus bar portion 721.

  The wiring member 73 includes a bus bar portion 731 and finger portions 732 and 733. One end of the finger portion 732 is connected to the bus bar portion 731. One end of the finger portion 733 is connected to the bus bar portion 731 on the opposite side of the connection portion between the bus bar portion 731 and the finger portion 732 with respect to the bus bar portion 731.

  The wiring member 74 includes a bus bar portion 741 and finger portions 742 and 743. One end of the finger portion 742 is connected to the bus bar portion 741. One end of the finger portion 743 is connected to the bus bar portion 741 on the opposite side of the connection portion between the bus bar portion 741 and the finger portion 742 with respect to the bus bar portion 741.

  The wiring member 75 includes a bus bar portion 751 and finger portions 752 and 753. The finger portions 752 and 753 are arranged adjacent to each other in the length direction of the bus bar portion 751, and one end thereof is connected to the bus bar portion 751 on the same side of the bus bar portion 751.

  The wiring member 76 includes a bus bar portion 761 and finger portions 762 and 763. One end of the finger portion 762 is connected to the bus bar portion 761. One end of the finger part 763 is connected to the bus bar part 761 on the opposite side of the connection part between the bus bar part 761 and the finger part 762 with respect to the bus bar part 761.

  The wiring member 77 has a bus bar portion 771 and finger portions 772 and 773. One end of finger portion 772 is connected to bus bar portion 771. One end of the finger portion 773 is connected to the bus bar portion 771 on the opposite side of the connection portion between the bus bar portion 771 and the finger portion 772 with respect to the bus bar portion 771.

  The wiring member 78 includes a bus bar portion 781 and finger portions 782 and 783. One end of the finger portion 782 is connected to the bus bar portion 781. One end of the finger portion 783 is connected to the bus bar portion 781 on the opposite side of the connection portion between the bus bar portion 781 and the finger portion 782 with respect to the bus bar portion 781.

  The wiring member 79 includes a bus bar portion 791 and finger portions 792 and 793. Finger portions 792 and 793 are arranged adjacent to each other in the length direction of bus bar portion 791, and one end thereof is connected to bus bar portion 791 on the same side of bus bar portion 791.

  The wiring member 80 includes a bus bar portion 801 and finger portions 802 and 803. One end of the finger portion 802 is connected to the bus bar portion 801. One end of the finger part 803 is connected to the bus bar part 801 on the opposite side of the connection part between the bus bar part 801 and the finger part 802 with respect to the bus bar part 801.

  The wiring member 81 has a bus bar portion 811 and finger portions 812 and 813. One end of the finger portion 812 is connected to the bus bar portion 811. One end of the finger portion 813 is connected to the bus bar portion 811 on the opposite side of the connection portion between the bus bar portion 811 and the finger portion 812 with respect to the bus bar portion 811.

  The wiring member 82 includes a bus bar portion 821 and finger portions 822 and 823. One end of the finger portion 822 is connected to the bus bar portion 821. One end of the finger part 823 is connected to the bus bar part 821 on the opposite side of the connection part between the bus bar part 821 and the finger part 822 with respect to the bus bar part 821.

  The wiring member 83 includes a bus bar portion 831 and finger portions 832 and 833. Finger portions 832 and 833 are arranged adjacent to each other in the length direction of bus bar portion 831, and one end thereof is connected to bus bar portion 831 on the same side of bus bar portion 831.

  The wiring member 84 includes a bus bar portion 841 and finger portions 842 and 843. One end of the finger portion 842 is connected to the bus bar portion 841. One end of the finger portion 843 is connected to the bus bar portion 841 on the opposite side of the connection portion between the bus bar portion 841 and the finger portion 842 with respect to the bus bar portion 841.

  The wiring member 85 has a bus bar portion 851 and finger portions 852 and 853. One end of the finger portion 852 is connected to the bus bar portion 851. One end of the finger portion 853 is connected to the bus bar portion 851 on the opposite side of the connection portion between the bus bar portion 851 and the finger portion 852 with respect to the bus bar portion 851.

  The wiring member 86 has a bus bar portion 861 and finger portions 862 and 863. One end of the finger portion 862 is connected to the bus bar portion 861. One end of the finger portion 863 is connected to the bus bar portion 861 on the opposite side of the connection portion between the bus bar portion 861 and the finger portion 862 with respect to the bus bar portion 861.

  The wiring member 87 has a bus bar portion 871 and finger portions 872. One end of the finger portion 872 is connected to the bus bar portion 871.

  The wiring member 71 is disposed on the insulating base 710 so that the finger portion 712 meshes with the finger portion 722 of the wiring member 72.

  The wiring member 72 is disposed on the insulating base 710 such that the finger portion 722 is engaged with the finger portion 712 of the wiring member 71 and the finger portion 723 is engaged with the finger portion 732 of the wiring member 73.

  The wiring member 73 is disposed on the insulating base 710 so that the finger portion 732 engages with the finger portion 723 of the wiring member 72 and the finger portion 733 engages with the finger portion 742 of the wiring member 74.

  The wiring member 74 is disposed on the insulating base 710 so that the finger portion 742 engages with the finger portion 733 of the wiring member 73 and the finger portion 743 engages with the finger portion 752 of the wiring member 75.

  The wiring member 75 is disposed on the insulating base 710 so that the finger portions 752 are engaged with the finger portions 743 of the wiring member 74 and the finger portions 753 are engaged with the finger portions 762 of the wiring member 76.

  The wiring member 76 is disposed on the insulating base 710 so that the finger portion 762 engages with the finger portion 753 of the wiring member 75 and the finger portion 763 engages with the finger portion 772 of the wiring member 77.

  The wiring member 77 is disposed on the insulating substrate 710 so that the finger portions 772 mesh with the finger portions 763 of the wiring material 76 and the finger portions 773 mesh with the finger portions 782 of the wiring material 78.

  The wiring member 78 is disposed on the insulating base 710 such that the finger portions 782 mesh with the finger portions 773 of the wiring material 77 and the finger portions 783 mesh with the finger portions 792 of the wiring material 79.

  The wiring member 79 is disposed on the insulating base 710 so that the finger portions 792 mesh with the finger portions 783 of the wiring material 78 and the finger portions 793 mesh with the finger portions 802 of the wiring material 80.

  The wiring member 80 is disposed on the insulating base 710 so that the finger portion 802 is engaged with the finger portion 793 of the wiring member 79 and the finger portion 803 is engaged with the finger portion 812 of the wiring member 81.

  The wiring member 81 is disposed on the insulating base 710 so that the finger portion 812 is engaged with the finger portion 803 of the wiring member 80 and the finger portion 813 is engaged with the finger portion 822 of the wiring member 82.

  The wiring member 82 is disposed on the insulating base 710 so that the finger portion 822 is engaged with the finger portion 813 of the wiring member 81 and the finger portion 823 is engaged with the finger portion 832 of the wiring member 83.

  The wiring member 83 is disposed on the insulating base 710 so that the finger portion 832 is engaged with the finger portion 823 of the wiring member 82 and the finger portion 833 is engaged with the finger portion 842 of the wiring member 84.

  The wiring member 84 is disposed on the insulating base 710 so that the finger portion 842 is engaged with the finger portion 833 of the wiring member 83 and the finger portion 843 is engaged with the finger portion 852 of the wiring member 85.

  The wiring member 85 is disposed on the insulating base 710 such that the finger portion 852 is engaged with the finger portion 843 of the wiring member 84 and the finger portion 853 is engaged with the finger portion 862 of the wiring member 86.

  The wiring member 86 is disposed on the insulating substrate 710 so that the finger portion 862 is engaged with the finger portion 853 of the wiring member 85 and the finger portion 863 is engaged with the finger portion 872 of the wiring member 87.

  The wiring member 87 is disposed on the insulating base 710 so that the finger portion 872 meshes with the finger portion 863 of the wiring member 86.

  Each of the wiring members 71 to 87 is not particularly limited as long as it is electrically conductive. Each of the wiring members 71 to 87 is made of, for example, Cu, Al, Ag, and an alloy containing these as main components.

  In addition, the thickness of the wiring members 71 to 87 is not particularly limited, but is preferably 10 μm or more and 80 μm or less, for example. If it is less than 10 μm, the wiring resistance becomes high, and if it exceeds 80 μm, the silicon substrate is warped due to the difference in thermal expansion coefficient between the wiring material and the silicon substrate due to the heat applied when the photoelectric conversion element 10 is bonded. Occur.

  The shape of the insulating substrate 710 is not limited to the shape shown in FIG. 13B and can be changed as appropriate. Moreover, you may form electroconductive materials, such as Ni, Au, Pt, Pd, Sn, In, and ITO, in a part of surface of the wiring materials 71-87. As described above, the conductive material such as Ni is formed on a part of the surface of the wiring members 71 to 87 because the electrical connection between the wiring members 71 to 87 and the electrodes 6 and 7 of the photoelectric conversion element 10 is good. This is to improve the weather resistance of the wiring members 71 to 87. Furthermore, the wiring members 71 to 87 may have a single layer structure or a multilayer structure.

The photoelectric conversion element 10 is arranged on the region REG1 so that the electrode 6 is connected to the finger part 712 of the wiring member 71 and the electrode 7 is connected to the finger part 722 of the wiring member 72, and the electrode 6 is a finger of the wiring member 72. The photoelectric conversion element 10 is arranged on the region REG <b> 2 such that the electrode 7 is connected to the finger portion 732 of the wiring member 73. Hereinafter, the photoelectric conversion element 10 is similarly arranged on the wiring members 73 to 87. Thereby, the 16 photoelectric conversion elements 10 are connected in series.

  The electrodes 6 and 7 of the photoelectric conversion element 10 are connected to the wiring members 71 to 87 by an adhesive. Examples of the adhesive include solder resin, solder, conductive adhesive, thermosetting Ag paste, low temperature curing copper paste, anisotropic conductive film (ACF), and anisotropic conductive paste (ACP). It consists of 1 or more types of adhesives selected from the group which consists of Conductive Paste) and an insulating adhesive agent (NCP: Non Conductive Paste).

  For example, TCAP-5401-27 manufactured by Tamura Kaken Co., Ltd. can be used as the solder resin.

  As the insulating adhesive, an epoxy resin, an acrylic resin, a urethane resin, or the like can be used, and a thermosetting resin or a photocurable resin can be used.

  As the conductive adhesive, solder particles containing at least one of tin and bismuth can be used. More preferably, the conductive adhesive is an alloy of tin and bismuth, indium, silver or the like. As a result, the melting point of the solder can be suppressed, and an adhesion process at a low temperature becomes possible.

  When using the photoelectric conversion element 10 in which the protective film 8 is formed on the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6, 7, the inorganic insulating film on the electrodes 6, 7 , There are inorganic insulating films on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and these two inorganic insulating films have different bases. And in the photoelectric conversion element 10, the inorganic insulating film from which a foundation | substrate differs is formed continuously. In such a situation, when a thermal history is applied to an inorganic insulating film having a different base, peeling of the inorganic insulating film may occur due to a difference in thermal expansion coefficient of the base.

  Therefore, a low temperature, particularly a heat process of 200 ° C. or lower is preferable, and as a result, a thermosetting Ag paste, a low temperature curable copper paste, an anisotropic conductive film and an anisotropic conductive film that can be cured and electrically bonded at a low temperature. A paste is particularly preferred.

  As described above, the photoelectric conversion element 10 disposed on the wiring sheet 70 is disposed between the ethylene vinyl acetate resin (EVA resin) disposed on the glass substrate and the EVA resin disposed on the PET film. . Then, the EVA resin on the glass substrate side is pressure-bonded to the photoelectric conversion element 10 by vacuum pressure bonding using a laminator device, and the EVA resin on the PET film side is pressure-bonded to the photoelectric conversion element 10 and heated to 125 ° C. to be cured. I let you. Thereby, a solar cell module can be produced by sealing the photoelectric conversion element 10 with the wiring sheet 70 in the EVA resin cured between the glass substrate and the PET film.

  In the first embodiment, the example in which the p-type amorphous semiconductor layer 5 is formed after the n-type amorphous semiconductor layer 4 is formed has been described. However, the p-type amorphous semiconductor layer 5 is formed. After that, the n-type amorphous semiconductor layer 4 may be formed. In this case, the alignment mark includes the same semiconductor layer as the p-type amorphous semiconductor layer 5, and the same semiconductor layer as the n-type amorphous semiconductor layer 4 is deposited on the alignment mark.

  In the first embodiment described above, an example in which the texture structure is formed on the entire back surface of the semiconductor substrate 1 has been described. However, the boundary (outer edge portion) of the region where the n-type amorphous silicon is formed in the alignment mark 4M. It is only necessary that at least a texture structure is formed under (). Even in such a configuration, the reflectance of the boundary portion of the n-type amorphous silicon in the alignment mark 4M becomes substantially uniform, so that the position of the alignment mark 4M can be reliably recognized by an optical microscope. .

  Further, the smaller the film thickness difference between the alignment mark 4M and the other region, the more difficult it is to recognize the boundary between the alignment mark 4M and the other region, but the region of the alignment mark 4M where the n-type amorphous silicon is formed. By forming the texture structure under the boundary (outer edge) portion, the visibility of the boundary portion of the n-type amorphous silicon in the alignment mark 4M is increased, and the recognition accuracy of the alignment mark 4M is improved. Thereby, the thickness of the n-type amorphous semiconductor layer 4 can be made thinner, the series resistance in the n-type amorphous semiconductor layer 4 can be reduced, and higher conversion efficiency can be realized. It becomes possible.

[Embodiment 2]
The present embodiment is different from the first embodiment in that a texture structure is formed on a part of the back surface of the semiconductor substrate 1 and the alignment mark 4M is not formed. Hereinafter, a configuration different from that of the first embodiment will be described.

  As shown in FIG. 14A, an n-type amorphous semiconductor layer 4 and a p-type amorphous semiconductor layer 5 are formed on the back surface of the semiconductor substrate 1A in the present embodiment. The alignment mark 4M is not formed in a region different from the region where the p-type amorphous semiconductor layer 5 is formed. In the present embodiment, in FIG. 14A, a texture structure similar to that of the above-described first embodiment is formed in portions (hereinafter referred to as texture regions) indicated by broken line frames P1 and P2 on the back surface of the semiconductor substrate 1A. . Then, a part of each boundary of a pair of adjacent n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5 overlaps with each other on texture regions P1 and P2. A broken line portion 41M of the n-type amorphous semiconductor layer 4 formed on the texture regions P1 and P2 is an example of a light scattering layer and functions as an alignment portion.

In the present embodiment, each process shown in (b1) to (b5) of FIG. 14B is performed in place of the process of FIG. 6 (b) of the first embodiment described above. Specifically, in step (b1) of FIG. 14B, a protective film 90 made of SiO _{2 is} formed on the entire back surface of the semiconductor substrate 1 ′ by sputtering. Then, a resist 91 is applied and patterned on the protective film 90, the resist 91 in a predetermined region is removed, and an opening 91a is formed (step (b2) in FIG. 14).

  Subsequently, the protective film 90 in the opening 91a is etched with hydrofluoric acid using the resist 91 as a mask to form an opening 90'a, and the resist 91 is removed (step (b3) in FIG. 14). Then, anisotropic etching similar to that in the first embodiment is performed on the portion of the opening 90′a on the back surface side of the semiconductor substrate 1 ′ and the light receiving surface side of the semiconductor substrate 1 ′ to form a texture structure. (Step (b4) in FIG. 14). Subsequently, the protective film 90 'on the back surface side of the semiconductor substrate 1' is etched using hydrofluoric acid to form the semiconductor substrate 1A (step (b5) in FIG. 14). As a result, a texture structure is formed on the entire light-receiving surface side of the semiconductor substrate 1A and a part of the regions P1 and P2 on the back surface side. Thereafter, as in the first embodiment, the processes of FIG. 6C to FIG. 10M are performed.

  In the present embodiment, in the step (e) of FIG. 7, a shadow mask (only a shadow mask having an opening 30a similar to the shadow mask 30) is used as a shadow mask for forming the n-type amorphous semiconductor layer 4. (Not shown) is used. In the present embodiment, the n-type amorphous semiconductor layer 4 is arranged so that a part of one long side of one opening 30a in the shadow mask overlaps with the portions of the broken line frames P1 and P2 in FIG. 14A. Form. Thereby, the alignment mark 41M which consists of a part of n-type amorphous semiconductor layer 4 is formed on the texture structure formed in the broken line frames P1 and P2.

  In the present embodiment, in the step (g) of FIG. 8, a shadow mask (only a shadow mask having an opening 40 a similar to the shadow mask 40) is used as a shadow mask for forming the p-type amorphous semiconductor layer 5. (Not shown) is used. Since the texture structure is formed under the alignment mark 41M, the reflectance of the portion of the alignment mark 41M becomes substantially uniform, and the position of the alignment mark 41M can be specified with an optical microscope. Therefore, in the present embodiment, after the shadow mask is arranged on the n-type amorphous semiconductor layer 4 so as to overlap the opening 40a based on the alignment mark 41M, the n-type amorphous semiconductor layer 4 The shadow mask is shifted by the width of the gap region G along the arrangement direction.

  As a result, the p-type amorphous semiconductor layer 5 is formed at a position separated from the n-type amorphous semiconductor layer 4 by a certain distance, and a set of adjacent n-types is provided in each of the texture regions P1 and P2. A part of each boundary between the amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is disposed. Note that after the formation of the p-type amorphous semiconductor layer 5, the steps of (h) in FIG. 8 to (m) of FIG. 10 are performed as in the first embodiment.

  The reflectance of the texture regions P1 and P2 in the semiconductor substrate 1A is substantially uniform. Therefore, the boundary between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 can be recognized by observing the texture regions P1 and P2 with an optical microscope. Thereby, after the formation of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, the position where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed is confirmed. It is possible to inspect whether the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed at appropriate positions.

  That is, a portion where the boundary between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is formed in the texture regions P1 and P2 is a light scattering layer, and the n-type amorphous semiconductor layer 4 and the p-type are formed. It functions as an inspection unit for inspecting the position where the amorphous semiconductor layer 5 is formed.

  In addition, although it is preferable from the viewpoint of inspection accuracy that there are a plurality of texture regions on the back surface of the semiconductor substrate 1A, it is sufficient that at least one texture region exists. When a plurality of texture regions are formed, each shadow for forming each of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is compared with a case where one texture region is formed. It is possible to more accurately recognize a positional shift when placing the mask. In the present embodiment, the alignment mark 41M is a part of the n-type amorphous semiconductor layer 4, and therefore, compared with the first embodiment, the n-type amorphous semiconductor layer 4 and the p-type in the semiconductor substrate 1A. Since the ratio occupied by the amorphous semiconductor layer 5 can be increased, the conversion efficiency of the photoelectric conversion element is improved.

  In FIG. 14A, an example in which a texture region is formed under each boundary portion between a pair of adjacent n-type amorphous semiconductor layer 4 and p-type amorphous semiconductor layer 5 on the back surface of semiconductor substrate 1A. However, as shown in FIG. 14C, a texture region may be formed in a region P3 indicated by a broken-line frame that overlaps one long side of at least one n-type amorphous semiconductor layer 4. Alternatively, a texture region may be formed in a region overlapping with a part of one long side of the n-type amorphous semiconductor layer 4. In short, a texture region may be formed in the entire region where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are formed on the back surface of the semiconductor substrate 1A, or at least one n-type amorphous semiconductor layer 5 may be formed. A texture region may be formed at a position overlapping at least a part of one long side of the type amorphous semiconductor layer 4. In the example of FIG. 14C, the broken line portion 42M of the n-type amorphous semiconductor layer 4 formed in the texture region P3 functions as an alignment portion and also as an inspection portion.

  The above example is an example in which the p-type amorphous semiconductor layer 5 is formed after the n-type amorphous semiconductor layer 4 is formed. The crystalline semiconductor layer 4 may be formed. In this case, it is sufficient that the texture structure is formed in a region that overlaps one long side of at least one p-type amorphous semiconductor layer 5 or a part of the long side.

[Embodiment 3]
In the present embodiment, a texture structure is formed on a part of the semiconductor substrate 1 and a shadow mask different from the shadow mask 30 is used to identify the n-type amorphous semiconductor layer 4 and the photoelectric conversion element 10. The first embodiment is different from the first embodiment in that identification information is formed.

  FIG. 15A is a schematic diagram showing a shadow mask 3100 in the present embodiment for forming the n-type amorphous semiconductor layer 4. As shown in FIG. 15A, the shadow mask 3100 includes a plurality of openings 30a for forming the n-type amorphous semiconductor layer 4 and a plurality of openings for forming individual identification information of the photoelectric conversion element 10. An opening region 30c made of 3001 is provided. The individual identification information is, for example, information indicating the manufacturing time or manufacturing location of the photoelectric conversion element 10, and the arrangement and number of the openings 3001 in the shadow mask 3100 differ depending on the manufactured photoelectric conversion element 10.

  In the present embodiment, instead of the process of FIG. 6A of the first embodiment, the semiconductor substrate 1 is manufactured by the same processes as the processes (b1) to (b5) of FIG. 14B of the second embodiment described above. A texture structure is formed on a part of the back surface of 'and a texture structure is formed on the entire light receiving surface of the semiconductor substrate 1'. Thereafter, as in the first embodiment, the processes of FIG. 6C to FIG. 10M are performed.

  In the present embodiment, a shadow mask 3100 is disposed on the passivation film 3 in place of the shadow mask 30 in the step shown in FIG. Specifically, the shadow mask 3100 is disposed so that the opening region 30c of the shadow mask 3100 is disposed on the region where the texture structure is formed, and n-type amorphous silicon is formed. As a result, n-type amorphous silicon is deposited on the opening 30a and the opening region 30c in the shadow mask 3100, and the n-type amorphous semiconductor layer 4 and the individual identification information are formed.

  After the formation of the n-type amorphous semiconductor layer 4 and the individual identification information, a shadow mask 3200 shown in FIG. 15B is arranged in place of the shadow mask 40 in the step shown in FIG. The semiconductor layer 5 is formed. The shadow mask 3200 has an opening 40a similar to the shadow mask 40 and a mask alignment mark 40c. The mask alignment mark 40c is not opened inside, and has four convex portions 402c to 405c at positions in contact with broken line frames 401c corresponding to the opening portions 3001 at the four corners in the opening region 30c of the shadow mask 3100. In the present embodiment, alignment is performed such that the four convex portions 402c to 405c of the mask alignment mark 40c of the shadow mask 3200 are in contact with a part of the individual identification information formed by the opening portions 3001 at the four corners of the shadow mask 3100. And a shadow mask 3200 is arranged.

  Since the texture structure is formed under the area where the individual identification information is formed and the reflectivity is substantially uniform, a part of the individual identification information used as a reference for alignment should be specified by an optical microscope. Can do. That is, the region where the individual identification information is formed in the semiconductor substrate 1 functions as an alignment unit. Thus, the opening 40a of the shadow mask 3200 is disposed at a position spaced apart from the n-type amorphous semiconductor layer 4 by a certain distance. Note that after the formation of the p-type amorphous semiconductor layer 5, the steps shown in FIGS. 8H to 10M are performed as in the first embodiment.

  Each time the photoelectric conversion element 10 is manufactured, the n-type amorphous semiconductor layer 4 is formed using a shadow mask in which the positional relationship of the opening 3001 in the opening region 30c is different, so that the individual identification information for each photoelectric conversion element is a semiconductor. It is formed on the back surface of the substrate 1. Since the semiconductor substrate 1 below the region where the individual identification information is formed has a texture structure, the individual identification information can be recognized by an optical microscope after the photoelectric conversion element 10 is manufactured. The element 10 can be specified.

  In the above example, the example in which the individual identification information made of n-type amorphous silicon is formed using the shadow mask 3100 for forming the n-type amorphous semiconductor layer 4 has been described. Even if a shadow mask for forming the amorphous semiconductor layer 5 is used, individual identification information combining identification information made of n-type amorphous silicon and identification information made of p-type amorphous silicon is formed. Good. That is, for example, as shown in FIG. 16, n-type amorphous semiconductor layers 4 and p-type amorphous semiconductor layers 5 are alternately formed adjacent to each other on the back surface of the semiconductor substrate 1B, and n-type amorphous semiconductors are formed. Individual identification information S may be formed by combining identification information 4s made of quality silicon and identification information 5s made of p-type amorphous silicon.

  In this case, an opening 30a for forming the n-type amorphous semiconductor layer 4 and the n-type amorphous semiconductor are formed in the same manner as the shadow mask 3100 in the step of FIG. An n-type amorphous silicon film is formed using a shadow mask provided with an opening 3001 for forming identification information 4s made of high quality silicon. Further, in the process of FIG. 8G, a shadow mask having an opening 40a similar to the shadow mask 3200 and an opening for forming the identification information 5s inside the mask alignment mark 40c in the shadow mask 3200. Is used to form a p-type amorphous silicon film. That is, this shadow mask is different from the shadow mask 3200 in that an opening for forming the identification information 5s is provided inside the mask alignment mark 40c. As a result, as shown in FIG. 16, the individual identification information S including the identification information 4s and the identification information 5s together with the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is formed on the back surface of the semiconductor substrate 1B. It is formed.

[Embodiment 4]
FIG. 17 is a cross-sectional view showing the configuration of the photoelectric conversion element according to this embodiment. In FIG. 17, the same reference numerals as those in the first embodiment are given to the same components as those in the first embodiment. As shown in FIG. 17, the photoelectric conversion element 20 according to the present embodiment is different from the photoelectric conversion element 10 in that it includes passivation films 301 and 302 instead of the passivation film 3 of the photoelectric conversion element 10.

  The passivation film 301 is disposed on the back surface of the semiconductor substrate 1 in contact with the back surface of the semiconductor substrate 1.

  The passivation film 302 is disposed on the back surface of the semiconductor substrate 1 adjacent to the back surface of the semiconductor substrate 1 and in contact with the back surface of the semiconductor substrate 1 in the in-plane direction of the semiconductor substrate 1.

  That is, the passivation films 301 and 302 are alternately arranged in the in-plane direction of the semiconductor substrate 1.

  The n-type amorphous semiconductor layer 4 is disposed on the passivation film 301 in contact with the passivation film 301.

  The p-type amorphous semiconductor layer 5 is disposed on the passivation film 302 in contact with the passivation film 302.

  As a result of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 being disposed on the passivation films 301 and 302, respectively, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are The semiconductor substrate 1 is alternately arranged in the in-plane direction.

  The protective film 8 is in contact with the passivation films 301 and 302, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, the electrodes 6 and 7, and a part of the back surface of the semiconductor substrate 1. Is formed on top.

  Each of the passivation films 301 and 302 is made of the same material as that of the passivation film 3 and has the same thickness as that of the passivation film 3. Note that the thickness of the passivation film 301 may be the same as or different from the thickness of the passivation film 302.

  18 to 21 are process diagrams showing a method for manufacturing the photoelectric conversion element 20 shown in FIG.

  In the present embodiment, first, after sequentially performing the steps of FIGS. 6A to 6C and FIG. 7D, a shadow mask 310 is disposed on the back surface of the semiconductor substrate 1 (see FIG. Step (e) in FIG. 18). The shadow mask 310 is made of the same material as the shadow mask 30 described above, and has openings 30 a and 30 b (see FIG. 8A) similar to the shadow mask 30.

  Then, the passivation film 301 made of i-type amorphous silicon, the n-type amorphous semiconductor layer 4 made of n-type amorphous silicon, and the alignment mark 4M are connected to the semiconductor substrate 1 by a plasma CVD method through the shadow mask 310. Are sequentially deposited on the back surface (see step (f) of FIG. 18). The conditions for forming i-type amorphous silicon and n-type amorphous silicon are as described in the first embodiment. As a result, a passivation film 301 is formed under the n-type amorphous semiconductor layer 4 and the alignment mark 4M. When the passivation film 301, the n-type amorphous semiconductor layer 4, and the alignment mark 4M are formed, a laminated film 311 of i-type amorphous silicon / n-type amorphous silicon is formed on the shadow mask 310.

  After step (f) in FIG. 18, a shadow mask 320 is disposed on the n-type amorphous semiconductor layer 4 and the alignment mark 4M (see step (g) in FIG. 18). The shadow mask 320 is also made of the same material as the shadow mask 40 described above, and has an opening 40a and an alignment opening 40b (see FIG. 11B) similar to the shadow mask 40. Also in the present embodiment, as in the first embodiment, alignment is performed with the alignment opening 40b in the shadow mask 320 and the alignment mark 4M formed on the back surface of the semiconductor substrate 1, so that the shadow mask 320 is not n-type. Arranged on the crystalline semiconductor layer 4. In the present embodiment, the passivation film 301 is not formed in other regions where the alignment mark 4M and the n-type amorphous semiconductor layer 4 are not formed. Therefore, the thickness of the portion where the alignment mark 4M and the n-type amorphous semiconductor layer 4 are formed is thicker than in the first embodiment. As a result, the contrast of the alignment mark 4M is higher than in the case of the first embodiment, the recognition accuracy of the alignment mark 4M when observed with an optical microscope is improved, and the shadow mask 320 is more reliably arranged at an appropriate position. Can do.

  Then, a passivation film 302 made of i-type amorphous silicon and a p-type amorphous semiconductor layer 5 made of p-type amorphous silicon are formed on the back surface of the semiconductor substrate 1 by a plasma CVD method through a shadow mask 320. Sequential deposition is performed (see step (h) in FIG. 19). The conditions for forming the i-type amorphous silicon and the p-type amorphous silicon are as described in the first embodiment. By forming the passivation film 302 and the p-type amorphous semiconductor layer 5, the i-type amorphous silicon / p-type amorphous silicon laminated film 51M is formed on the alignment mark 4M, and the shadow mask 320 is also formed. Then, an i-type amorphous silicon / p-type amorphous silicon laminated film 321 is formed.

  After step (h) in FIG. 19, a shadow mask 330 is disposed (see step (i) in FIG. 19). The shadow mask 330 is made of the same material as the shadow mask 30 described above.

  Then, electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 through the shadow mask 330, respectively (see step (j) in FIG. 20).

  Thereafter, a shadow mask 340 is disposed (see step (k) in FIG. 20). The shadow mask 340 is made of the same material as the shadow mask 30 described above.

  Then, the protective film 8 is formed on the electrodes 6 and 7 through the shadow mask 340. Thus, the photoelectric conversion element 20 is completed (see step (l) in FIG. 21). The photoelectric conversion element 20 is modularized using the wiring sheet 70 described above. The other description in the present embodiment is the same as the description in the first embodiment.

  Thus, in this embodiment, before forming the p-type amorphous semiconductor layer 5, the passivation film 301 is formed in another region where the alignment mark 4M and the n-type amorphous semiconductor layer 4 are not formed. It has not been. Therefore, the film thickness of the alignment mark 4M is thicker than the other areas, and the contrast of the alignment mark 4M is higher than the other areas. As a result, when the p-type amorphous semiconductor layer 5 is formed, the alignment mark 4M can be more reliably recognized by the optical microscope, and the position of the convex portion of the alignment opening 40b of the shadow mask 320 on the alignment mark 4M. Can be combined. Therefore, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are more reliably placed at appropriate positions as compared with the first embodiment in which the passivation film 3 is formed on the entire back surface of the semiconductor substrate 1. Can be formed.

[Embodiment 5]
FIG. 22 is a schematic diagram illustrating a configuration of a photoelectric conversion module including the photoelectric conversion element according to this embodiment. With reference to FIG. 22, the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.

  The plurality of photoelectric conversion elements 1001 are arranged in an array and are connected in series. Note that the plurality of photoelectric conversion elements 1001 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel.

  Each of the plurality of photoelectric conversion elements 1001 includes photoelectric conversion elements 10 and 20.

  The cover 1002 is formed of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001. The cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material (on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001). For example, glass, a resin sheet etc.) and the sealing material (for example, EVA etc.) which fills the clearance gap between a transparent base material and a back surface base material are included.

  The output terminal 1003 is connected to the photoelectric conversion element 1001 arranged at one end of the plurality of photoelectric conversion elements 1001 connected in series.

  The output terminal 1004 is connected to the photoelectric conversion element 1001 arranged at the other end of the plurality of photoelectric conversion elements 1001 connected in series.

  As described above, the photoelectric conversion elements 10 and 20 have improved photoelectric conversion efficiency. Therefore, the photoelectric conversion efficiency of the photoelectric conversion module 1000 can be improved.

  Note that the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 is an arbitrary integer of 2 or more.

  In addition, the photoelectric conversion module according to the present embodiment is not limited to the configuration illustrated in FIG. 22, and may have any configuration as long as any one of the photoelectric conversion elements 10 and 20 is used.

[Embodiment 6]
FIG. 23 is a schematic diagram showing a configuration of a photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

  Referring to FIG. 23, the photovoltaic power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105.

  The connection box 1102 is connected to the photoelectric conversion module array 1101. The power conditioner 1103 is connected to the connection box 1102. Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110. The power meter 1105 is connected to the distribution board 1104 and the grid connection.

  The photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the connection box 1102.

  The connection box 1102 receives DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.

  The power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104.

  Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electric equipment 1110, the distribution board 1104 supplies the surplus AC power to the grid interconnection via the power meter 1105.

  The power meter 1105 measures the power in the direction from the grid connection to the distribution board 1104 and measures the power in the direction from the distribution board 1104 to the grid connection.

  FIG. 24 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG.

  Referring to FIG. 24, photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.

  The plurality of photoelectric conversion modules 1120 are arranged in an array and are connected in series. Note that the plurality of photoelectric conversion modules 1120 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.

  The output terminal 1121 is connected to the photoelectric conversion module 1120 located at one end of the plurality of photoelectric conversion modules 1120 connected in series.

  The output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.

  Note that the number of photoelectric conversion modules 1120 included in the photoelectric conversion module array 1101 is an arbitrary integer of 2 or more.

  The operation in the solar power generation system 1100 will be described. The photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.

  The power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.

  The distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the grid connection via the power meter 1105.

  Further, when the AC power received from the power conditioner 1103 is less than the power consumption of the electric device 1110, the distribution board 1104 receives the AC power received from the grid connection and the AC power received from the power conditioner 1103 to the electric device 1110. Supply.

  As described above, the solar power generation system 1100 includes any one of the photoelectric conversion elements 10 and 20 having excellent photoelectric conversion efficiency. Therefore, the photoelectric conversion efficiency of the solar power generation system 1100 can be improved.

  FIG. 25 is a schematic diagram showing a configuration of another photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

  The photovoltaic power generation system including the photoelectric conversion element according to this embodiment may be a photovoltaic power generation system 1100A shown in FIG.

  Referring to FIG. 25, solar power generation system 1100A is the same as solar power generation system 1100 except that storage battery 1106 is added to solar power generation system 1100 shown in FIG.

  The storage battery 1106 is connected to the power conditioner 1103.

  In solar power generation system 1100A, power conditioner 1103 appropriately converts part or all of the DC power received from connection box 1102 and stores it in storage battery 1106.

  In addition, the power conditioner 1103 performs the same operation as that of the photovoltaic power generation system 1100.

  Storage battery 1106 stores the DC power received from power conditioner 1103. The storage battery 1106 supplies the stored power to the power conditioner 1103 as appropriate according to the amount of power generated by the photoelectric conversion module array 1101 and / or the power consumption of the electric device 1110.

  Thus, since the solar power generation system 1100A includes the storage battery 1106, it can suppress output fluctuations due to fluctuations in the amount of sunshine, and can use the electric power stored in the storage battery 1106 even in a time zone without sunlight. The device 1110 can be supplied.

  Note that the storage battery 1106 may be built in the power conditioner 1103.

  Further, the photovoltaic power generation system according to the present embodiment is not limited to the configuration shown in FIGS. 23 and 24 or the configuration shown in FIGS. 24 and 25, and any configuration as long as one of the photoelectric conversion elements 10 and 20 is used. There may be.

[Embodiment 7]
FIG. 26 is a schematic diagram showing a configuration of a photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

  Referring to FIG. 26, solar power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221. The photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation systems 1100 and 1100A shown in FIGS.

  The power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.

  The transformer 1221 is connected to the power conditioners 1211 to 121n and the grid connection.

  Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).

  Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.

  Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.

  The connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.

  The current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.

  The i photoelectric conversion module arrays 1301 to 130i of the module system 1231 convert sunlight into electricity to generate DC power, and the generated DC power is supplied to the current collecting box 1321 through the connection boxes 1311 to 131i, respectively. Supply. The i photoelectric conversion module arrays 1301 to 130i of the module system 1232 convert sunlight into electricity to generate DC power, and the generated DC power is supplied to the current collecting box 1321 through the connection boxes 1311 to 131i, respectively. Supply. Hereinafter, similarly, the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To supply box 1321.

  Then, the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.

  The j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.

  In the same manner, the j current collection boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.

  Each of the power conditioners 1211 to 121n converts the DC power received from the subsystems 1201 to 120n into AC power, and supplies the converted AC power to the transformer 1221.

  The transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the grid interconnection.

  As described above, the photovoltaic power generation system 1200 includes any one of the photoelectric conversion elements 10 and 20 having excellent photoelectric conversion efficiency. Therefore, the photoelectric conversion efficiency of the photovoltaic power generation system 1200 can be improved.

  FIG. 27 is a schematic diagram showing a configuration of another photovoltaic power generation system including the photoelectric conversion element according to this embodiment.

  The photovoltaic power generation system including the photoelectric conversion element according to this embodiment may be a photovoltaic power generation system 1200A illustrated in FIG.

  Referring to FIG. 27, a photovoltaic power generation system 1200 </ b> A is obtained by adding storage batteries 1241 to 124 n to the photovoltaic power generation system 1200 shown in FIG. 26, and is otherwise the same as the photovoltaic power generation system 1200.

  The storage batteries 1241 to 124n are connected to the power conditioners 1211 to 121n, respectively.

  In photovoltaic power generation system 1200A, power conditioners 1211 to 121n convert the DC power received from subsystems 1201 to 120n into AC power, and supply the converted AC power to transformer 1221. In addition, power conditioners 1211 to 121n appropriately convert DC power received from subsystems 1201 to 120n, respectively, and store the converted DC power in storage batteries 1241 to 124n, respectively.

  The storage batteries 1241 to 124n supply the stored power to the power conditioners 1211 to 121n, respectively, according to the amount of DC power from the subsystems 1201 to 120n.

  Thus, since the photovoltaic power generation system 1200A includes the storage batteries 1241 to 124n, it is possible to suppress output fluctuations due to fluctuations in the amount of sunlight, and power is stored in the storage batteries 1241 to 124n even in a time zone without sunlight. Power can be supplied to the transformer 1221.

  The storage batteries 1241 to 124n may be incorporated in the power conditioners 1211 to 121n, respectively.

  Moreover, the solar power generation system according to the present embodiment is not limited to the configuration shown in FIGS. 26 and 27, and may have any configuration as long as any one of the photoelectric conversion elements 10 and 20 is used.

  Furthermore, in this embodiment, it is not necessary that all the photoelectric conversion elements included in the photovoltaic power generation systems 1200 and 1200A are the photoelectric conversion elements 10 and 20.

  For example, all of the photoelectric conversion elements included in a certain subsystem (any one of the subsystems 1201 to 120n) are any one of the photoelectric conversion elements 10 and 20, and another subsystem (any one of the subsystems 1201 to 120n). In some cases, a part or all of the photoelectric conversion elements included in the photoelectric conversion elements may be photoelectric conversion elements other than the photoelectric conversion elements 10 and 20.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiment but by the scope of claims for patent, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims for patent.

  (1) In the above-described third and fourth embodiments, the example in which the p-type amorphous semiconductor layer 5 is formed after the n-type amorphous semiconductor layer 4 is first formed on the back surface of the semiconductor substrate 1 has been described. The n-type amorphous semiconductor layer 4 may be formed after the p-type amorphous semiconductor layer 5 is formed first.

  (2) In the above-described second and third embodiments, as in the fourth embodiment, the n-type amorphous semiconductor layer 4, the alignment mark 4 M, and the p-type amorphous semiconductor layer 5 only on the lower part thereof. Alternatively, a passivation film made of an intrinsic amorphous semiconductor layer may be formed. In this case, in the second embodiment, alignment marks 41M and 42M include n-type amorphous semiconductor layer 4 and a passivation film formed under n-type amorphous semiconductor layer 4. Therefore, the contrast of the portions where the alignment marks 41M and 42M are formed becomes high, and the shadow mask used when forming the p-type amorphous semiconductor layer 5 can be arranged at a more appropriate position. In the third embodiment, the individual identification information including the n-type amorphous semiconductor layer 4 includes the n-type amorphous semiconductor layer 4 and a passivation film formed under the n-type amorphous semiconductor layer 4. including. Therefore, the contrast of the portion where the individual identification information is formed is increased, and the projections 402c to 405c of the shadow mask 3200 used when forming the p-type amorphous semiconductor layer 5 can be more accurately aligned. .

  (3) In the second embodiment described above, the position of the shadow mask used when forming the p-type amorphous semiconductor layer 5 is determined based on the alignment mark 41M formed of a part of the n-type amorphous semiconductor layer 4. Although an example of adjustment has been described, the position of the shadow mask may be adjusted without using the alignment mark 41M. That is, for example, an alignment pin for aligning each position of a shadow mask used when forming the n-type amorphous semiconductor layer 4 and a shadow mask used when forming the p-type amorphous semiconductor layer 5 is used as a semiconductor. It fixes beforehand to the stand which fixes board | substrate 1A. As in the second embodiment, after a texture structure is formed on at least a part of the back surface of the semiconductor substrate 1A, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are aligned with each alignment pin. The n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are sequentially formed.

  Then, after forming the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, the region where the texture structure is formed is observed with an optical microscope, so that the n-type non-layer formed on the texture structure is observed. The boundary between the crystalline semiconductor layer 4 and the p-type amorphous semiconductor layer 4 can be specified. Thereby, it can be inspected whether the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 do not overlap and are formed at appropriate positions. In other words, a shadow mask is arranged using alignment pins, and the boundary portion between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 formed on the texture structure on the back surface of the semiconductor substrate 1A It is an example of a scattering layer and functions as an inspection unit. In the above description, the example using the alignment pin has been described. However, the method for aligning the shadow mask is not limited to the method using the alignment pin.

  The present invention is applied to a photoelectric conversion element, a solar cell module including the photoelectric conversion element, and a solar power generation system.

  DESCRIPTION OF SYMBOLS 1,1A, 1B ... Semiconductor substrate, 2 ... Antireflection film, 3,301,302 ... Passivation film, 4 ... N-type amorphous semiconductor layer, 4s, 5s ... Identification information, 5 ... P-type amorphous semiconductor layer 6, 7 ... electrodes, 6a, 6b, 7a, 7b ... conductive layer, 8 ... protective film, 10, 20 ... photoelectric conversion element, 30, 40, 50, 60, 310, 320, 330, 340, 3100, 3200 ... Shadow mask, 70 ... Wiring sheet, 1000 ... Solar cell module, 1100, 1100A, 1200, 1200A ... Solar power generation system, 1101, 1301 ... Photoelectric conversion module array, 1120 ... Photoelectric conversion module, S ... Individual identification information, 4M , 41M, 42M ... Alignment mark

Claims (5)

A semiconductor substrate;
A first amorphous semiconductor layer formed on one surface of the semiconductor substrate and having a first conductivity type;
A second conductivity type formed on one surface of the semiconductor substrate and adjacent to the first amorphous semiconductor layer in an in-plane direction of the semiconductor substrate, opposite to the first conductivity type. A second amorphous semiconductor layer having
A texture structure formed on at least a part of one surface of the semiconductor substrate;
An alignment portion formed on the texture structure,
The alignment unit includes individual identification information for identifying a photoelectric conversion element,
The individual identification information is a photoelectric conversion element formed of at least one amorphous semiconductor layer of the first amorphous semiconductor layer and the second amorphous semiconductor layer . The photoelectric conversion element according to claim 1,
The alignment unit is a photoelectric conversion element provided in a region different from a region where the first amorphous semiconductor layer and the second amorphous semiconductor layer are formed . In the photoelectric conversion element according to claim 1 or 2,
A part of the individual identification information is a photoelectric conversion element used as an alignment reference when forming one of the first amorphous semiconductor layer and the second amorphous semiconductor layer . In the photoelectric conversion element according to any one of claims 1 to 3,
The alignment unit further includes at least one amorphous semiconductor layer of the first amorphous semiconductor layer and the second amorphous semiconductor layer constituting the individual identification information, and one surface of the semiconductor substrate. A photoelectric conversion element including an intrinsic amorphous semiconductor layer therebetween. In the photoelectric conversion element according to any one of claims 1 to 4,
When the texture structure is viewed in plan, the average value of the diameter of the circumscribed circle of the convex portion of the texture structure is less than 15 μm.