CN106169417A - 一种异质结终端的碳化硅功率器件及其制备方法 - Google Patents

一种异质结终端的碳化硅功率器件及其制备方法 Download PDF

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CN106169417A
CN106169417A CN201610541460.4A CN201610541460A CN106169417A CN 106169417 A CN106169417 A CN 106169417A CN 201610541460 A CN201610541460 A CN 201610541460A CN 106169417 A CN106169417 A CN 106169417A
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silicon carbide
junctions
hetero
terminal
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刘成
叶念慈
黄侯魁
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
Xiamen Sanan Integrated Circuit Co Ltd
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
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Priority to PCT/CN2017/090512 priority patent/WO2018010545A1/zh
Priority to US16/236,806 priority patent/US20190140046A1/en
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Abstract

本发明公开了一种异质结终端的碳化硅功率器件，包括阴极电极、衬底层、N型SiC外延层及阳极电极，还包括间隔分立的若干P型结构，该些P型结构由生长温度低于SiC的P型半导体材料通过异质外延生长形成于所述N型SiC外延层之上并至少分布于阳极电极外围以构成异质结终端，有效避免了对N型SiC外延层掺杂特性的影响，可以获得高击穿电压及低器件开启电压的碳化硅器件。本发明还公开了其制作方法，大大减少了对高温复杂工艺的要求，制程简单，减少了制作成本。

Description

一种异质结终端的碳化硅功率器件及其制备方法
技术领域
本发明涉及半导体器件，特别是涉及一种异质结终端的碳化硅功率器件及其制备方法。
背景技术
基于宽禁带半导体材料(如碳化硅(SiC)，氮化镓(GaN))的功率器件可以提供更大的击穿电压和功率密度，有望被广泛应用于下一代电力转换中。在SiC功率器件中，由于结的不连续性，电力线往往集中在结的边缘，造成结边缘处高电场的存在。高场的存在将导致结边缘的提早击穿，极大地限制了器件的反向击穿电压。于是在SiC功率器件的设计及制作中，往往会采用各式的结终端技术来缓解边缘电场集中效应，提高器件的击穿电压。常见的结终端技术包括保护环、终端结扩展以及场版结构等。其中，保护环、终端结扩展技术由于不依赖于高质量的介质材料，广为实际器件制作所采用。SiC功率器件一般基于N型SiC衬底和作为漂移区的弱N型外延层。相应的，采用P型SiC作为结终端以形成耗尽区来分散结边缘电场。
目前，该P型SiC区域的制作可以通过外延生长和离子注入的方式。其中，外延生长是在N型SiC层上直接整面生长P型SiC，由于P型SiC生长温度往往较高(>1500℃)，在生长过程中不可避免有一些P型杂质(如Al)扩散到弱N型SiC中，对N型SiC表面形成自掺杂，甚至将该区域转化成P型，导致N型SiC表面掺杂特性改变，进而影响到低器件开启电压的获得；针对SiC的P型离子注入往往需要先进的设备如高温离子注入机和超高温退火炉来完成，且具有复杂的制程工艺，成本高，这制约了其产业化发展。
发明内容
本发明的目的在于克服现有技术之不足，提供一种异质结终端的碳化硅功率器件及其制备方法。
本发明解决其技术问题所采用的技术方案是：一种异质结终端的碳化硅功率器件，由下至上包括阴极电极、衬底层，N型SiC外延层及阳极电极，还包括间隔分立的若干P型结构，该些P型结构由生长温度低于SiC的P型半导体材料通过异质外延生长形成于所述N型SiC外延层之上并至少分布于阳极电极外围以构成异质结终端。
优选的，所述P型半导体材料的生长温度是600℃～1200℃。
优选的，所述P型半导体材料是P型GaN或P型AlGaN。
优选的，该些P型结构包括绕设于所述阳极电极外围的若干封闭环结构，且该些封闭环结构等距离或不等距离间隔排布。
优选的，所述阳极电极与所述N型SiC外延层至少部分形成肖特基接触。
优选的，所述P型结构还包括设置于阳极电极和N型SiC外延层之间的若干分立结构。
优选的，所述P型结构还包括设置于阳极电极和N型SiC外延层之间并隔离所述阳极电极和N型SiC外延层的层状结构。
优选的，所述N型SiC外延层上表面设置有若干凹槽，该些P型结构对应形成于凹槽之内。
优选的，还包括一介质层，该介质层设置于所述N型SiC外延层之上并覆盖所述阳极电极之外的区域以及位于所述区域的该些P型结构。
优选的，所述介质层是SiNx、SiO2、Al2O3、AlN的一种或其组合，其中X大于0小于1。
一种上述碳化硅功率器件的制备方法，包括以下步骤：
(1)提供一碳化硅外延结构，包括层叠的衬底层以及N型SiC外延层；
(2)于N型SiC外延层上通过异质外延生长P型半导体材料并定义形成所述若干间隔分立的P型结构，所述异质外延生长方法包括化学气相沉积法和分子束外延法，且所述P型半导体材料的生长温度低于SiC；
(3)于步骤2)结构的两侧分别制作阳极电极和阴极电极。
优选的，步骤2)中，通过掩膜选择性外延生长、干法蚀刻或湿法蚀刻的方式定义形成所述若干P型结构。
优选的，步骤3)中，在步骤2)得到的结构上方沉积一介质层并蚀刻开窗，于所述开窗部分制作所述阳极电极。
优选的，步骤3)中，所述阳极电极和阴极电极通过电子束蒸镀、磁控溅镀、离子蒸镀或电弧离子蒸镀沉积金属形成，并通过退火形成肖特基接触或欧姆接触。
本发明的有益效果是：
1.于N型SiC外延层之上形成若干间隔分立的P型结构，该些P型结构至少分布于阳极电极外围以形成结终端结构以用于分散边缘电场，该些P型结构是由生长温度低于SiC的P型半导体材料通过异质外延生长形成的，由于较低的生长温度及不同的掺杂机制，有效避免了对N型SiC外延层掺杂特性的影响，可以获得高击穿电压及低器件开启电压的碳化硅器件，得到的器件性能好；同时大大减少了对高温复杂工艺的要求，制程简单，减少了制作成本。
2.适用于肖特基势垒二极管(SBD)、结势垒肖特基二极管(JBS)以及PN结二极管等，其中后两者于阳极电极和N型SiC外延层之间的P型掺杂区亦可以与结终端结构同时形成，简化了制程，适用性广。
附图说明
图1为本发明第一实施例之结构示意图；
图2为本发明第二实施例之结构示意图；
图3为本发明第三实施例之结构示意图。
具体实施方式
以下结合附图及实施例对本发明作进一步详细说明。本发明的各附图仅为示意以更容易了解本发明，其具体比例可依照设计需求进行调整。文中所描述的图形中相对元件的上下关系，在本领域技术人员应能理解是指构件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本说明书所揭露的范围。此外，图中所示的元件及结构的个数，均仅为示例，并不以此对数目进行限制，实际可依照设计需求进行调整。
实施例1
参考图1，本实施例的碳化硅功率器件是碳化硅肖特基势垒二极管(SBD)100，由下至上包括阴极电极110、衬底层120、N型SiC外延层130及阳极电极140，其中阳极电极140与N型SiC外延层130形成金属-半导体的肖特基接触。在N型SiC外延层130之上阳极电极140的外围具有若干间隔分立的P型结构150以形成结终端。在阳极电极140以外的区域，裸露的N型SiC外延层130以及P型结构150之上覆盖有介质层160。
P型结构150是由生长温度低于SiC的P型半导体材料通过异质外延生长直接形成于N型SiC外延层130之上。具体的，P型半导体材料的生长温度在600℃～1200℃之间，例如可以是P型GaN或P型AlGaN。以P型GaN为例，其生长温度约为700℃，而常规SiC生长温度在1500℃以上，在此温度下，P型掺杂杂质并不会渗透到N型SiC外延层130中，对N型SiC外延层130的掺杂特质不产生影响，从而保持了其特性，得到的器件综合性能好。进一步，N型SiC外延层130的掺杂浓度为<5×1016/cm3，P型半导体材料的掺杂浓度为>5×1017/cm3，P型结构150形成耗尽区来分散结边缘电场。相对P型SiC(>1×1018/cm3)，异质生长的P型半导体可以具有较低的掺杂浓度来实现相同的效果。
优选的，该些P型结构150是绕设于阳极电极140外围的若干封闭环结构，且该些封闭环结构等距离或不等距离间隔排布。封闭环的设置可以有效地避免高电场过于集中于SiC主结而导致的器件过早击穿。在高压关断状态下，耗尽区在主结产生并向周围扩展。耗尽区在沿着SiC表面横向的扩展一旦接触到封闭环150区域，该P型封闭环就会感应到一个电势。封闭环上的电势可以有效的帮助耗尽区的进一步扩展，避免由于耗尽区域较小造成的电场集中。进一步，该些封闭环的尺寸包括厚度、宽度和间距需要根据实际的器件的耐压等级(130的厚度)而定。针对600～1200V耐压规格器件，N型SiC外延层130的厚度在4～12μm,对应P型结构150封闭环的厚度可以在200～800nm，宽度可以在0.5～10μm，间距可以在1～10μm。
介质层160覆盖该二极管结构上方阳极电极140之外的区域以扩散电场并有效增加击穿电压，优选的，介质层160是SiNx、SiO2、Al2O3、AlN的一种或其组合，其中X大于0小于1。
本实施例的二极管，其衬底优选为同质的SiC衬底，阳极电极和阴极电极是例如Ti、Ni、Pt、Al、Ag、Au、W、Pb、Si等金属或其合金或其层状复合结构。
以下以GaN的P型结构为例说明其制作方法，首先提供一碳化硅外延结构，包括层叠的衬底层以及N型SiC外延层，于N型SiC外延层上通过化学气相沉积法生长P型GaN层，具体，以三甲基镓、三甲基铝、氨分别作为Ga源、Al源和N源，二茂镁作为P型掺杂源，于700℃的温度下，上述气体裂解，于N型SiC外延层上沉积形成P型GaN层，通过干法蚀刻(例如ICP或RIE)该P型GaN层以定义形成若干间隔分立的P型结构，本实施例中，该P型结构是若干封闭环结构；接着，通过化学气相沉积、原子层沉积、溅射等方法在上述外延结构上表面沉积介质层并蚀刻开窗；通过电子束蒸镀、磁控溅镀、离子蒸镀或电弧离子蒸镀沉积金属于衬底层背面制作阴极电极，优选为Ti/Ni，并于1000℃退火2分钟形成欧姆接触；最后，于介质层的蚀刻窗口通过电子束蒸镀、磁控溅镀、离子蒸镀或电弧离子蒸镀沉积金属制作阳极电极，优选为Ti/Ni，并于550℃退火5分钟形成肖特基接触，该阳极电极的厚度可大于介质层并覆盖周缘介质层上表面的部分区域。
此外，P型半导体材料亦可以通过有机气相沉积或分子束外延法进行生长，其图形化亦可以通过选择性外延——例如制作图形化介质掩膜，以及湿法蚀刻等方式来实现。
实施例2
参考图2，本实施例的碳化硅功率器件是碳化硅结势垒肖特基二极管200，其与实施例1的差别在于，P型结构除了分布于N型SiC外延层230之上阳极电极240外围的P型结构251以形成异质结终端外，还包括设置于阳极电极240和N型SiC外延层230之间的若干分立P型结构252以形成结势垒，具体，P型结构252可以是若干平行的条形结构，与N型SiC外延层230之间形成若干分立排布的PN结，相邻P型结构252之间裸露的N型SiC外延层230与阳极电极240接触形成肖特基结，在反向阻断状态下利用相邻PN结的耗尽区夹断效应，获得与PN二极管类似的阻断特性；在正向导通状态下，低势垒高度的肖特基结开启电流，从而获得与肖特基二极管类似的导通特性。
N型SiC外延层230上表面设置有若干凹槽231，该些P型结构251以及252对应形成于凹槽之内。利用凹槽的深度，PN结由SiC表面转移到内部，可在不牺牲正向导通压降的情况下有效降低反向漏电流。其余结构，例如阴极电极210、衬底层220以及介质层160参照实施例1。
相对于实施例1，本实施例的制作方法，在形成P型结构之前，还包括蚀刻N型SiC外延层上表面以形成上述凹槽的步骤。结势垒结构以及结终端结构同时成型，优选的，P型结构251是封闭环，P型结构252是条形，通过蚀刻或选择性外延等方式进行图案化。
实施例3
参考图3，本实施例的碳化硅功率器件是碳化硅PN结二极管300，其与实施例2的差别在于，P型结构除了分布于N型SiC外延层330之上阳极电极340外围的P型结构351以形成异质结终端外，还包括设置于阳极电极340和N型SiC外延层330之间并隔离阳极电极340和N型SiC外延层330的层状P型结构352。P型结构352与N型SiC外延层330之间形成PN结。其余结构，例如阴极电极310、衬底层320以及介质层360参照实施例1，制作方法参考实施例2，不加以赘述。
上述实施例仅用来进一步说明本发明的一种异质结终端的碳化硅功率器件及其制备方法，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。

Claims (14)

1.一种异质结终端的碳化硅功率器件，由下至上包括阴极电极、衬底层，N型SiC外延层及阳极电极，其特征在于：还包括间隔分立的若干P型结构，该些P型结构由生长温度低于SiC的P型半导体材料通过异质外延生长形成于所述N型SiC外延层之上并至少分布于阳极电极外围以构成异质结终端。
2.根据权利要求1所述的异质结终端的碳化硅功率器件，其特征在于：所述P型半导体材料的生长温度是600℃～1200℃。
3.根据权利要求2所述的异质结终端的碳化硅功率器件，其特征在于：所述P型半导体材料是P型GaN或P型AlGaN。
4.根据权利要求1所述的异质结终端的碳化硅功率器件，其特征在于：该些P型结构包括绕设于所述阳极电极外围的若干封闭环结构，且该些封闭环结构等距离或不等距离间隔排布。
5.根据权利要求1或4所述的异质结终端的碳化硅功率器件，其特征在于：所述阳极电极与所述N型SiC外延层至少部分形成肖特基接触。
6.根据权利要求5所述的异质结终端的碳化硅功率器件，其特征在于：所述P型结构还包括设置于阳极电极和N型SiC外延层之间的若干分立结构。
7.根据权利要求1或4所述的异质结终端的碳化硅功率器件，其特征在于：所述P型结构还包括设置于阳极电极和N型SiC外延层之间并隔离所述阳极电极和N型SiC外延层的层状结构。
8.根据权利要求1所述的异质结终端的碳化硅功率器件，其特征在于：所述N型SiC外延层上表面设置有若干凹槽，该些P型结构对应形成于凹槽之内。
9.根据权利要求1所述的异质结终端的碳化硅功率器件，其特征在于：还包括一介质层，该介质层设置于所述N型SiC外延层之上并覆盖所述阳极电极之外的区域以及位于所述区域的该些P型结构。
10.根据权利要求9所述的异质结终端的碳化硅功率器件，其特征在于：所述介质层是SiNx、SiO2、Al2O3、AlN的一种或其组合，其中X大于0小于1。
11.一种如权利要求1～10任一项所述的碳化硅功率器件的制备方法，其特征在于包括以下步骤：
(1)提供一碳化硅外延结构，包括层叠的衬底层以及N型SiC外延层；
(2)于N型SiC外延层上通过异质外延生长P型半导体材料并定义形成所述若干间隔分立的P型结构，所述异质外延生长方法包括化学气相沉积法和分子束外延法，且所述P型半导体材料的生长温度低于SiC；
(3)于步骤2)结构的两侧分别制作阳极电极和阴极电极。
12.根据权利要求11所述的制备方法，其特征在于：步骤2)中，通过掩膜选择性外延生长、干法蚀刻或湿法蚀刻的方式定义形成所述若干P型结构。
13.根据权利要求11所述的制备方法，其特征在于：步骤3)中，在步骤2)得到的结构上方沉积一介质层并蚀刻开窗，于所述开窗部分制作所述阳极电极。
14.根据权利要求11或13所述的制备方法，其特征在于：步骤3)中，所述阳极电极和阴极电极通过电子束蒸镀、磁控溅镀、离子蒸镀或电弧离子蒸镀沉积金属形成，并通过退火形成肖特基接触或欧姆接触。
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CN112466926A (zh) * 2020-11-02 2021-03-09 深圳大学 肖特基二极管及其制备方法
CN114023805A (zh) * 2021-10-18 2022-02-08 西安电子科技大学 具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管
CN116093164A (zh) * 2023-04-07 2023-05-09 深圳市晶扬电子有限公司 一种带有浮岛型保护环的高压肖特基二极管
CN116093164B (zh) * 2023-04-07 2023-07-11 深圳市晶扬电子有限公司 一种带有浮岛型保护环的高压肖特基二极管
CN117613106A (zh) * 2024-01-23 2024-02-27 山东大学 一种高击穿电压碳化硅肖特基二极管及其制备方法

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