CN114023805A - 具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管 - Google Patents

具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管 Download PDF

Info

Publication number
CN114023805A
CN114023805A CN202111210244.9A CN202111210244A CN114023805A CN 114023805 A CN114023805 A CN 114023805A CN 202111210244 A CN202111210244 A CN 202111210244A CN 114023805 A CN114023805 A CN 114023805A
Authority
CN
China
Prior art keywords
gate
source
cap layer
drain
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111210244.9A
Other languages
English (en)
Inventor
贾护军
张云帆
朱顺威
杨银堂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN202111210244.9A priority Critical patent/CN114023805A/zh
Publication of CN114023805A publication Critical patent/CN114023805A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明涉及场效应晶体管技术领域，公开了一种具有P型掺杂区和凹陷缓冲层的4H‑SiC金属半导体场效应管，自下而上包括4H‑SiC半绝缘衬底、P型缓冲层和N型沟道层，所述N型沟道层表面设有源极帽层和漏极帽层，所述源极帽层和漏极帽层表面分别设有源电极和漏电极，所述N型沟道上表面靠近源极帽层的一侧形成栅电极，所述栅电极与漏极帽层之间形成凹陷栅漏飘移区，所述栅电极与源极帽层之间形成栅源飘移区，所述凹陷栅漏飘移区的表面靠近栅角处设有P型掺杂区，所述栅源飘移区下方的P型缓冲层向下凹陷形成凹陷缓冲层。本发明具有击穿电压大幅提高，漏极输出电流稳定的优点。

Description

具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管
技术领域
本发明涉及场效应晶体管技术领域，特别是一种同时具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应晶体管。
背景技术
碳化硅(SiC)作为第三代新型半导体材料在很多方面都表现出优异的特性，例如，它具有2-4×106V/cm的高击穿电场、3.3eV的较宽的禁带、3.5W/(cm·K)的高热导率以及2.7×107cm/s的高电子饱和速度等优良特性。在SiC的众多同质异形体中，4H-SiC的电子饱和速度高及电子迁移率高(4H-SiC的电子迁移率大约是6H-SiC的两倍左右)，并且其施主杂质的离化能比较小以及各向异性较低，这其综合性能表现最为优越。因此，在射频微波功率器件中，4H-SiC是最理想的功率器件材料的选择，具有很强的竞争力。
目前多数4H-SiC MESFET方面的研究都是以双凹陷4H-SiC MESFET为基础开展的，例如CN104681618A公开了一种具有双凹陷缓冲层的4H-SiC金属半导体场效应晶体管，自下而上包括4H-SiC半绝缘衬底、P型缓冲层、N型沟道层，N型沟道层的两侧分别为源极帽层和漏极帽层，源极帽层和漏极帽层表面分别是源电极和漏电极，沟道上方且靠近源极帽层的一侧形成栅电极，P型缓冲层的上端面在栅源和栅漏间下方设有凹槽。虽然相比于传统结果，双凹陷4H-SiC MESFET在饱和漏极电流和频率等方面有着较大提升，但是其击穿电压却比传统结构下降了很多。这是功率器件一个难以避免需要均衡的问题：宽的沟道带来较大的饱和漏极电流，但同时也降低了沟道的有效电阻，造成了击穿电压的恶化。因此，在保证漏极电流基本不变的条件下大幅提升击穿电压就成了均衡提升器件性能的一个重要研究方向。
发明内容
针对现有技术存在的上述不足，本发明的目的在于提供具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管。
为实现以上目的，本发明采用如下技术方案：
具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管，自下而上包括4H-SiC半绝缘衬底、P型缓冲层和N型沟道层，所述N型沟道层表面设有源极帽层和漏极帽层，所述源极帽层和漏极帽层表面分别设有源电极和漏电极，所述N型沟道上表面靠近源极帽层的一侧形成栅电极，所述栅电极与漏极帽层之间形成凹陷栅漏飘移区，所述栅电极与源极帽层之间形成栅源飘移区，所述凹陷栅漏飘移区的表面靠近栅角处设有P型掺杂区，所述栅源飘移区下方的P型缓冲层向下凹陷形成凹陷缓冲层。
作为本发明的进一步优选方案，所述P型掺杂区以栅电极靠近漏极帽层的一侧边缘为起点，长度为0.2～0.5μm，深度为0.05μm。
作为本发明的进一步优选方案，所述P型掺杂区的掺杂浓度为1×1017～4×1017cm-3。
作为本发明的进一步优选方案，所述凹陷缓冲层以源极帽层的里侧为起点，长度为0.5μm，深度为0.03～0.08μm。
进一步地，所述N型沟道层的上方且距离源极帽层的里侧0.5μm处为0.7μm长的栅电极，其中靠近源极帽层侧的一半栅电极向N型沟道层凹陷0.05μm，形成凹栅结构。
与现有技术相比，本发明在栅漏飘移区引入了P型掺杂区且在栅源飘移区引入了凹陷缓冲层，具有以下有益效果：
(1)提高了饱和漏极电流
对于4H-SiC金属半导体场效应晶体管结构而言，其饱和漏极电流的大小与沟道内的载流子总数成正比。本发明虽然在漏飘移区引入了P型掺杂区，降低了沟道的总电荷数，但是由于栅源飘移区下缓冲层的凹陷又增大了沟道的总电荷数。综合来看，本发明由于凹陷缓冲层和P型掺杂区共同作用的结果，器件的饱和电流相比于双凹陷4H-SiC MESFET有一定提高。
(2)击穿电压得到大幅度提高
由于电场集中效应，4H-SiC MESFET器件的击穿一般发生在漏侧的栅角，此处器件表面的电场最大，本发明通过在栅漏飘移区的栅角处引入P型掺杂区，与N型的沟道形成P-N结，产生耗尽区，器件表面的电场分布得到调节；并且该耗尽区可承受更大的漏极电压，减缓了栅角的电场集中效应，即需要更大的漏电压才能使漏侧栅角达到临界击穿电场，因此大幅提高了器件的击穿电压。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为本发明同时具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应晶体管的结构示意图；
图中标记：1为4H-SiC半绝缘衬底，2为P型缓冲层，3为N型沟道层，4为源极帽层，5为漏极帽层，6为源电极，7为漏电极，8为栅电极，9为栅漏飘移区，10为栅源飘移区，11为P型掺杂区，12为凹陷缓冲层。
具体实施方式
下面结合具体实施例对本发明进行详细说明。以下实施例将有助于本领域的技术人员进一步理解本发明，但不以任何形式限制本发明。应当指出的是，对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进。这些都属于本发明的保护范围。
实施例1
如图1所示，具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应晶体管，自下而上包括：4H-SiC半绝缘衬底1、P型缓冲层2和N型沟道层3，所述P型缓冲层2掺杂浓度为1.4×1015cm-3，厚度为0.5μm；所述N型沟道层3掺杂浓度为3×1017cm-3，厚度为0.25μm；所述N型沟道层3的两侧分别为0.5μm长的N+型源极帽层4和漏极帽层5，两者掺杂浓度和厚度相同且分别为1.0×1020cm-3和0.2μm，源极帽层4和漏极帽层5表面分别是源电极6和漏电极7，源电极6和漏电极7之间形成凹陷的沟道表面，所述N型沟道层3的上方且距离源极帽层4的里侧0.5μm处为0.7μm长的栅电极8，其中靠近源极帽层4侧的一半栅电极8向N型沟道层3凹陷0.05μm，形成凹栅结构，所述栅电极8与漏极帽层5之间形成凹陷栅漏飘移区9，所述栅电极8与源极帽层4之间形成栅源飘移区10，所述凹陷栅漏飘移区9的表面靠近栅角处设有P型掺杂区11，所述栅源飘移区下方的P型缓冲层向下凹陷形成凹陷缓冲层12。
所述P型掺杂区以栅电极8靠近漏极帽层5的一侧边缘为起点，长度为0.3μm，深度为0.05μm，掺杂浓度为3×1017cm-3。
所述凹陷缓冲层12以源极帽层4的里侧边缘为起点，长度为0.5μm，向下凹陷厚度为0.05μm。
实施例2
具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应晶体管，包括掺杂浓度为1×1017cm-3的P型掺杂区，其长度和厚度分别为0.2μm和0.05μm，且凹陷缓冲层深度为0.03μm。
本实施例的其余技术方案与实施例1一致。
实施例3
具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应晶体管，包括掺杂浓度为4×1017cm-3的P型掺杂区，其长度和厚度分别为0.5μm和0.05μm，且凹陷缓冲层深度为0.08μm。
本实施例的其余技术方案与实施例1一致。
通过仿真实验，在相同条件下，相比于现有技术中的双凹陷4H-SiC金属半导体场效应晶体管，本发明击穿电压得到了61.57％的提高，且饱和漏极电流也有一定提高，从而大幅度提高了器件的输出功率密度，输出功率密度提升了约72.85％。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变形或修改，这并不影响本发明的实质内容。

Claims (5)

1.具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管，其特征在于，自下而上包括4H-SiC半绝缘衬底、P型缓冲层和N型沟道层，所述N型沟道层表面设有源极帽层和漏极帽层，所述源极帽层和漏极帽层表面分别设有源电极和漏电极，所述N型沟道上表面靠近源极帽层的一侧形成栅电极，所述栅电极与漏极帽层之间形成凹陷栅漏飘移区，所述栅电极与源极帽层之间形成栅源飘移区，所述凹陷栅漏飘移区的表面靠近栅角处设有P型掺杂区，所述栅源飘移区下方的P型缓冲层向下凹陷形成凹陷缓冲层。
2.根据权利要求1所述具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管，其特征在于，所述P型掺杂区以栅电极靠近漏极帽层的一侧边缘为起点，长度为0.2～0.5μm，深度为0.05μm。
3.根据权利要求1所述具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管，其特征在于，所述P型掺杂区的掺杂浓度为1×1017～4×1017cm-3。
4.根据权利要求1所述具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管，其特征在于，所述凹陷缓冲层以源极帽层的里侧为起点，长度为0.5μm，深度为0.03～0.08μm。
5.根据权利要求1所述具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管，其特征在于，所述N型沟道层的上方且距离源极帽层的里侧0.5μm处为0.7μm长的栅电极，其中靠近源极帽层侧的一半栅电极向N型沟道层凹陷0.05μm，形成凹栅结构。
CN202111210244.9A 2021-10-18 2021-10-18 具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管 Pending CN114023805A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111210244.9A CN114023805A (zh) 2021-10-18 2021-10-18 具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111210244.9A CN114023805A (zh) 2021-10-18 2021-10-18 具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管

Publications (1)

Publication Number Publication Date
CN114023805A true CN114023805A (zh) 2022-02-08

Family

ID=80056492

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111210244.9A Pending CN114023805A (zh) 2021-10-18 2021-10-18 具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管

Country Status (1)

Country Link
CN (1) CN114023805A (zh)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10178024A (ja) * 1996-12-18 1998-06-30 Matsushita Electric Ind Co Ltd 電界効果型トランジスタ及びその製造方法
US5821576A (en) * 1995-10-18 1998-10-13 Northrop Grumman Corporation Silicon carbide power field effect transistor
WO2005114746A1 (en) * 2004-05-21 2005-12-01 Nanyang Technological University Novel structures of silicon carbide metal semiconductor field effect transistors for high voltage and high power applications
US20060043379A1 (en) * 2004-08-31 2006-03-02 An-Ping Zhang SIC metal semiconductor field-effect transistors and methods for producing same
CN1787228A (zh) * 2004-12-07 2006-06-14 三菱电机株式会社 半导体器件
CN102339868A (zh) * 2011-09-01 2012-02-01 西安电子科技大学 带反型隔离层结构的金属半导体场效应晶体管及制作方法
CN102738228A (zh) * 2012-06-28 2012-10-17 电子科技大学 栅边缘凹槽型源场板结构高电子迁移率晶体管
CN103928529A (zh) * 2014-04-30 2014-07-16 西安电子科技大学 4H-SiC金属半导体场效应晶体管
CN104393047A (zh) * 2014-10-28 2015-03-04 西安电子科技大学 具有阶梯缓冲层结构的4H-SiC金属半导体场效应晶体管
CN106169417A (zh) * 2016-07-11 2016-11-30 厦门市三安集成电路有限公司 一种异质结终端的碳化硅功率器件及其制备方法
CN108447907A (zh) * 2018-03-26 2018-08-24 英诺赛科（珠海）科技有限公司 晶体管及其制备方法
CN113257887A (zh) * 2021-03-23 2021-08-13 西安电子科技大学 一种具有三种区域的4H-SiC金属半导体场效应晶体管

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821576A (en) * 1995-10-18 1998-10-13 Northrop Grumman Corporation Silicon carbide power field effect transistor
JPH10178024A (ja) * 1996-12-18 1998-06-30 Matsushita Electric Ind Co Ltd 電界効果型トランジスタ及びその製造方法
WO2005114746A1 (en) * 2004-05-21 2005-12-01 Nanyang Technological University Novel structures of silicon carbide metal semiconductor field effect transistors for high voltage and high power applications
US20060043379A1 (en) * 2004-08-31 2006-03-02 An-Ping Zhang SIC metal semiconductor field-effect transistors and methods for producing same
CN1787228A (zh) * 2004-12-07 2006-06-14 三菱电机株式会社 半导体器件
CN102339868A (zh) * 2011-09-01 2012-02-01 西安电子科技大学 带反型隔离层结构的金属半导体场效应晶体管及制作方法
CN102738228A (zh) * 2012-06-28 2012-10-17 电子科技大学 栅边缘凹槽型源场板结构高电子迁移率晶体管
CN103928529A (zh) * 2014-04-30 2014-07-16 西安电子科技大学 4H-SiC金属半导体场效应晶体管
CN104393047A (zh) * 2014-10-28 2015-03-04 西安电子科技大学 具有阶梯缓冲层结构的4H-SiC金属半导体场效应晶体管
CN106169417A (zh) * 2016-07-11 2016-11-30 厦门市三安集成电路有限公司 一种异质结终端的碳化硅功率器件及其制备方法
CN108447907A (zh) * 2018-03-26 2018-08-24 英诺赛科（珠海）科技有限公司 晶体管及其制备方法
CN113257887A (zh) * 2021-03-23 2021-08-13 西安电子科技大学 一种具有三种区域的4H-SiC金属半导体场效应晶体管

Similar Documents

Publication Publication Date Title
TWI447911B (zh) 具有增強傳導之非貫穿半導體通道的半導體裝置及製造方法
JP6066219B2 (ja) 低いソース抵抗を有する電界効果トランジスタデバイス
Wang et al. Hysteresis-free and μs-switching of D/E-modes Ga2O3 hetero-junction FETs with the BV2/Ron, sp of 0.74/0.28 GW/cm2
CN102364688B (zh) 一种垂直双扩散金属氧化物半导体场效应晶体管
US9263560B2 (en) Power semiconductor device having reduced gate-collector capacitance
CN109920839B (zh) P+屏蔽层电位可调碳化硅mosfet器件及制备方法
CN115188814B (zh) 一种rc-jgbt器件及其制作方法
CN107437566B (zh) 一种具有复合介质层宽带隙半导体纵向双扩散金属氧化物半导体场效应管及其制作方法
US20120280252A1 (en) Field Effect Transistor Devices with Low Source Resistance
CN117497600B (zh) 超结碳化硅晶体管的结构、制造方法及电子设备
CN117497601B (zh) 平面型碳化硅晶体管的结构、制造方法及电子设备
WO2019114201A1 (zh) 一种低导通电阻的碳化硅功率半导体器件
CN113270492A (zh) 一种沟槽型GaN绝缘栅双极型晶体管
CN108550621A (zh) 一种具有变k介质槽的超结碳化硅vdmos器件
CN113257887A (zh) 一种具有三种区域的4H-SiC金属半导体场效应晶体管
Jiang et al. Simulation study of 4h-SiC trench MOSFETs with various gate structures
CN106910775B (zh) 一种具有多凹陷缓冲层的4H-SiC金属半导体场效应晶体管
CN109346517B (zh) 一种碳化硅mos栅控晶闸管
CN114023805A (zh) 具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管
CN109103239B (zh) 一种具有栅下局部低掺杂的4H-SiC金属半导体场效应晶体管
CN105789282B (zh) 一种具有部分高掺杂沟道4H-SiC金半场效应管
Yi et al. SiC trench MOSFET with integrated side-wall Schottky barrier diode having P+ electric field shield
CN113380877A (zh) 一种双结型场板的功率器件
Chen et al. Study of 4H–SiC trench MOSFET structures
CN104916706A (zh) 一种具有宽沟道深凹陷的金属半导体场效应管

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20220208