CN106165104B - 于半导体薄膜的应变松弛的异质外延中用于缺陷的有效深宽比捕捉的具倾角的沟槽的使用 - Google Patents

于半导体薄膜的应变松弛的异质外延中用于缺陷的有效深宽比捕捉的具倾角的沟槽的使用 Download PDF

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CN106165104B
CN106165104B CN201580019086.5A CN201580019086A CN106165104B CN 106165104 B CN106165104 B CN 106165104B CN 201580019086 A CN201580019086 A CN 201580019086A CN 106165104 B CN106165104 B CN 106165104B
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inclination angle
groove
crystalline material
crystalline
defect
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CN106165104A (zh
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斯瓦米纳坦·T·斯里尼瓦桑
法里恩·阿德尼·哈贾
埃罗尔·安东尼奥·C·桑切斯
帕特里克·M·马丁
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Applied Materials Inc
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Abstract

本公开内容的实施方式涉及降低异质外延生长薄膜中的位错密度，以及包括具有降低的位错密度的异质外延薄膜的装置。根据本公开内容的实施方式，高深宽比沟槽的侧壁可倾斜或具有倾角，以允许形成于高深宽比沟槽中的结晶材料中的缺陷终止于倾斜的侧壁中，所述缺陷包括沿高深宽比沟槽的长度传播的缺陷。本公开内容的实施方式可用以减少微电子应用中硅(Si)上异质外延生长中的缺陷，诸如在场效应晶体管中使用第III族‑第V族元素的高迁移率通道。

Description

于半导体薄膜的应变松弛的异质外延中用于缺陷的有效深宽 比捕捉的具倾角的沟槽的使用
技术领域
本公开内容的实施方式涉及具有高晶格失配的材料的异质外延生长。更特定而言，本公开内容的实施方式涉及降低异质外延生长薄膜中的位错密度，以及包括具有降低的位错密度的异质外延薄膜的装置。
背景技术
异质外延是在结晶基板上或不同材料的薄膜上的结晶薄膜生长，异质外延具有许多实际应用。例如，硅(Si)上的锗(Ge)异质外延用作场效应晶体管(field effecttransistor；FET)中的p型通道。然而，由于两种不同结晶材料之间的晶格失配，异质外延薄膜易于产生缺陷，诸如位错、反相晶界，以及迭积缺层。
深宽比捕捉(aspect ratio trapping；ART)已经用以减少异质外延薄膜中的缺陷。在深宽比捕捉中，结晶材料在较深的狭窄沟槽(即高深宽比沟槽)中生长，以使得由晶格失配所引起的一些位错可终止于槽壁，由此，所述位错可在高深宽比沟槽内被捕捉，而非达到结晶材料的有效区域。
然而，常规深宽比捕捉无法终止沿狭窄沟槽的长度所产生的位错。图1示意性地图示了常规深宽比捕捉的结构100。狭窄沟槽106在介电层104中形成于结晶材料102上方，使得异质外延薄膜可在狭窄沟槽106中形成。狭窄沟槽106沿x方向较为狭窄，且沿z方向长度延伸。在狭窄沟槽106底部110曝露的结晶材料102充当种晶结构，以用于外来材料在狭窄沟槽106中的外延生长。在异质外延期间，由外来材料与结晶材料102的晶格失配所引起的位错自底部110产生且沿所有方向扩展。沿x-y平面(即垂直于狭窄沟槽106的长度)扩展的位错可到达侧壁108且终止。然而，沿x-z平面(即平行于狭窄沟槽106的长度)扩展的位错可到达狭窄沟槽106的顶部112且对所欲有效区域产生负面影响。
因此，需要在异质外延薄膜中具有减少的缺陷的方法及结构。
发明内容
本公开内容的实施方式涉及具有高晶格失配的材料的异质外延生长。更特定而言，本公开内容的实施方式涉及降低异质外延生长薄膜中的位错密度，以及包括具有降低的位错密度的异质外延薄膜的装置。
一个实施方式提供一种装置，所述装置包括：第一结晶材料；以及在第一结晶材料上方形成的非结晶层。具有倾角的沟槽贯穿非结晶层而形成，以使得第一结晶材料位于具有倾角的沟槽的底部。所述装置进一步包括在具有倾角的沟槽中通过外延生长而形成的第二结晶材料。第一结晶材料和第二结晶材料具有失配的晶格尺寸。具有倾角的沟槽的侧壁在第一结晶材料顶表面上的投影长于具有倾角的沟槽的底部在所述顶表面上的投影。
本公开内容的另一个实施方式提供一种用于形成半导体装置的方法。所述方法包括在第一结晶材料上方形成非结晶层，贯穿非结晶层形成具有倾角的沟槽以在具有倾角的沟槽底部曝露第一结晶材料的一部分，以及从具有倾角的沟槽底部起通过外延生长形成第二结晶材料以填充具有倾角的沟槽，其中第一结晶材料和第二结晶材料具有失配的晶格尺寸。
本公开内容的另一个实施方式提供一种用于形成半导体装置的方法。所述方法包括在含硅结晶基板上方形成介电层，以及贯穿介电材料形成具有倾角的沟槽以在具有倾角的沟槽底部曝露含硅结晶基板的一部分。具有倾角的沟槽的侧壁与含硅结晶基板的顶表面之间的倾角小于其中h表示介电层厚度，且w表示具有倾角的沟槽沿含硅结晶基板顶表面的宽度。所述方法进一步包括在具有倾角的沟槽的底部蚀刻曝露的含硅结晶基板以沿(111)晶面方向产生一表面，以及在具有倾角的沟槽中通过外延生长形成结晶材料，所述结晶材料包括第III族元素和第V族元素。
附图说明
因此，以上简要总结的本公开内容的上述特征可被详细理解的方式、对本公开内容更加特定的描述，可通过参考实施方式获得，所述实施方式中的一些示出于附图中。然而，值得注意的是，所述附图仅示出了本公开内容的典型的实施方式，因此将不被视为对本公开内容的范围的限制，因为本公开内容可允许其它等效的实施方式。
图1是通过深宽比捕捉进行常规异质外延的结构的示意图。
图2示意性地示出根据本公开内容一个实施方式的用于异质外延的具有倾角的沟槽。
图3A是根据本公开内容的一个实施方式的用于形成具有倾角的沟槽的处理腔室的示意性剖面图。
图3B是根据本公开内容的另一个实施方式的用于形成具有倾角的沟槽的处理腔室的示意性剖面图。
图4A-4D示意性地绘示根据本公开内容的一个实施方式的装置的形成，所述装置在具有倾角的沟槽中具有异质外延薄膜。
图5示意性地绘示根据本公开内容一个实施方式的替换外延线的形成。
图6A-6B示意性地绘示根据本公开内容的一个实施方式通过回蚀进行的外延线的形成。
图7是根据本公开内容的一个实施方式的异质外延生长方法的流程图。
为便于理解，已尽可能的情况下使用相同的参考数字指定这些附图中共通的相同元件。可以考虑到的是，在一个实施方式中公开的元件可有利地用于其它实施方式，而无需赘述。
具体实施方式
根据本公开内容的实施方式，高深宽比沟槽的侧壁可倾斜或具有倾角，以允许形成于高深宽比沟槽中的结晶材料缺陷将在倾斜侧壁中终止，所述缺陷包括沿高深宽比沟槽的长度传播的缺陷。本公开内容的实施方式可用以减少由异质外延形成的任何结晶薄膜中的缺陷。例如，本公开内容的实施方式可用以减少微电子应用中硅(Si)上异质外延生长中的缺陷，诸如场效应晶体管中使用第III族-第V族元素的高迁移率通道。本公开内容的实施方式也可用于形成其它外延薄膜，诸如形成于蓝宝石上的氮化镓(GaN)薄膜、形成于砷化镓(GaAs)上或单结晶CVD钻石上或铱上的磷化铝镓铟(AlGaInP)薄膜。
图2示意性地示出根据本公开内容的一个实施方式的结构200，结构200具有用于异质外延的具有倾角的沟槽206。结构200包括结晶材料202。结晶材料202可具有沿y-z平面的顶表面202a。非结晶层204可在结晶材料202的顶表面202a上形成。具有倾角的沟槽206在非结晶层204中形成以曝露结晶材料202的顶表面202a的一部分。具有倾角的沟槽206由侧壁210和底部212界定，底部212是顶表面202a的一部分。侧壁210和底部212在边缘203处会合。为论述方便起见，具有倾角的沟槽206的倾角α是侧壁210与底部212之间的倾角，具有倾角的沟槽206的宽度w由边缘203之间的距离界定，且具有倾角的沟槽206的高度h由非结晶材料204的厚度界定。外来结晶材料208在具有倾角的沟槽206中自底部212形成，且填充具有倾角的沟槽206。外来结晶材料208和结晶材料202的晶格尺寸不同。结晶材料202与结晶材料208之间的晶格尺寸的失配导致外来结晶材料208中形成缺陷，诸如位错、反相晶界和迭积缺层。可选择具有倾角的沟槽206的倾角α、宽度w以及高度h，以使得在结晶材料202与外来结晶材料208面接的位置处，自具有倾角的沟槽206的底部212起始的缺陷可在具有倾角的沟槽206的侧壁210上终止。
在一个实施方式中，倾角α经设定以使得在平行于x-z平面的平面内沿具有倾角的沟槽206的长度延伸的缺陷在具有倾角的沟槽的侧壁210上终止。具体地，选择倾角α和宽度w以使得侧壁210在y-z平面上的投影w'比具有倾角的沟槽206的宽度w长，
或
在一个实施方式中，选择深宽比，即高度与宽度之比h/w，以使得自底部212产生且沿平行于x-y平面的平面传播的缺陷可在侧壁210上终止。应当注意的是，高度与宽度之比h/w无单位。
在一个实施方式中，具有倾角的沟槽206的高度h可为约100纳米或更小。具有倾角的沟槽206的宽度w可为约20纳米至约40纳米之间。具有倾角的沟槽206的倾角α可为约11度至约45度之间。在一个实施方式中，具有倾角的沟槽206的倾角α可为约30度。
结晶材料202可为由结晶材料形成的基板，或在基板上形成的结晶层。在一个实施方式中，结晶材料202可为含硅基板，所述含硅基板包括锗(Ge)、碳(C)、硼(B)、磷(P)或其它可与硅材料共同生长、掺杂，和/或相关联的已知元素。
非结晶材料204可为介电材料，所述介电材料包括以下中的一个或多个：氮化硅(SiN)、二氧化硅(SiO2)、氮氧化硅(SiON)或可用以形成介电层的其它适合材料。
外来结晶材料208可在具有倾角的沟槽206的底部212上自曝露的结晶材料202起通过异质外延而形成。外来结晶材料208可包括二元或三元第III族-第V族元素中的一个。第III族元素可包括镓(Ga)、铝(Al)和铟(In)。第V族元素可包括氮(N)、磷(P)和砷(As)。
结构200可用于形成任何适合的需要异质外延沟槽材料的装置，诸如场效应晶体管和光电子装置。
结构200的具有倾角的沟槽206可由定向蚀刻工艺形成。在一个实施方式中，具有倾角的沟槽206可通过修正等离子体入射倾角和将经修正的等离子体引导至基板而形成。图3A是根据本公开内容的一个实施方式的用于形成具有倾角的沟槽的等离子体处理腔室300的示意性剖面图。等离子体处理腔室300包括界定处理空间302的腔室主体301。基板支撑件306安置于处理空间302中以在操作期间支撑基板308。等离子体处理腔室300进一步包括等离子体源304以在处理空间302中在基板308上方产生并维持等离子体310。
等离子体处理腔室300进一步包括绝缘修正器320，以在将等离子体310引导至基板308之前修正等离子体310的入射倾角322。在一个实施方式中，绝缘修正器320可包括两个绝缘板312、314。两个绝缘板312和314经定位以使得在两者之间形成间隙316。在一个实施方式中，两个绝缘板312可安置于不同水平位准，以使得间隙316包括沿平行于基板表面326的方向的水平元件322与垂直于基板表面326的垂直元件324。绝缘修正器320的间隙316定位在接近基板308的等离子体鞘310a附近。间隙316修正等离子体鞘310a内的电场以控制等离子体310与等离子体鞘310a之间的边界形状。从间隙316吸引至基板308的等离子体310中的离子流318以一倾角334击打基板308。
离子流318的倾角334是能够在基板308上的处理带328上形成具有倾角的沟槽。倾角334类似于正在形成的具有倾角的沟槽的倾角。可通过调整间隙316的垂直元件324与水平元件322而微调倾角334。在一个实施方式中，致动器330和332可连接至绝缘板312、314以分别移动绝缘板312、314，以调整间隙316的垂直元件324与水平元件322。
基板308和绝缘修正器320可相对于彼此移动以移动处理带328，由此通过扫描基板308上方的处理带328而处理整个基板308。在一个实施方式中，致动器330和332也可相对于基板308移动绝缘板312、314，以移动处理带328。
或者，具有倾角的沟槽206可通过离子束蚀刻方法而形成，所述方法例如离子束蚀刻(ion beam etching；IBE)、反应性离子束蚀刻(reactive ion beam etching；RIBE)，以及化学辅助离子束蚀刻(chemical assisted ion beam etching；CABIE)。图3B是根据本公开内容的另一个实施方式的用于形成具有倾角的沟槽的处理腔室350的示意性剖面图。处理腔室350可包括界定处理区域354的腔室主体352。基板支撑件356将基板358定位在处理区域354中。处理腔室350进一步包括离子束源360。离子束源360将梳状离子束362引向处理区域352中的基板358。离子束362可沿中心轴364为梳状。基板支撑件356将基板358定位在垂直于基板轴366的方向上。基板轴366相对于离子束362的中心轴364成倾角368，以使得离子束362以倾角368轰击基板358，以产生具有倾角的沟槽。
图4A-4D示意性地绘示根据本公开内容的一个实施方式的装置400的形成，所述装置在具有倾角的沟槽中具有异质外延薄膜。在一个实施方式中，装置400可为平面金氧半导体场效应晶体管(metal-oxide-semiconductor field effect transistor；MOSFET)的一部分。或者，装置400可为FinFET的一部分，所述FinFET即具有连接源极与漏极的薄鳍状物的场效应晶体管。MOSFET的源极与漏极之间的通道或FinFET的薄鳍状物可通过根据本公开内容的实施方式的异质外延而形成。
如图4A中所示，基板402上形成有介电层406。基板402由结晶材料形成。基板402可为硅基板，或具有以下元素的硅基板：锗(Ge)、碳(C)、硼(B)、磷(P)或其它可与硅材料共同生长、掺杂和/或相关联的已知元素。在一个实施方式中，浅沟槽隔离(shallow trenchisolation；STI)404可在基板402中形成以在相邻装置之间提供隔离。浅沟槽隔离404可由氧化硅形成。
介电层406可包括以下的一个或多个：氮化硅(SiN)、二氧化硅(SiO2)、氮氧化硅(SiON)或可用以形成非结晶介电层的其它适合材料。
沟槽图案410可在介电层406上方的掩膜层408中形成。沟槽图案410可用以形成根据本公开内容的实施方式的具有倾角的沟槽。掩膜层408可为光刻胶层或硬掩膜层。掩膜层408可由光刻胶、氧化硅、氮化硅、玻璃上硅(silicon on glass；SOG)、保形碳层以及其它适合的材料形成。
在图4B中，具有倾角的沟槽412贯穿介电层406而形成，以在具有倾角的沟槽412的底表面414曝露基板402的一部分。底表面414上的结晶结构可充当种晶以用于具有倾角的沟槽412中的外延生长。在具有倾角的沟槽412形成之后可移除掩膜层408。
具有倾角的沟槽412可通过干式蚀刻而形成，例如通过上文中图3A或图3B中描述的设备和方法而形成。在一个实施方式中，蚀刻气体的等离子体或离子束可被引导至基板402以形成具有倾角的沟槽412。蚀刻气体可包括SF6、C3F8、CF4、BF3、BI3、N2、Ar、PH3、AsH3、B2H6、H2、Xe、Kr、Ne、He、SiH4、SiF4、GeH4、GeF4、CH4、AsF5、PF3、PF5，或它们的组合。
根据本公开内容的实施方式，具有倾角的沟槽412的深宽比倾角α经设定以使得缺陷延伸至具有倾角的沟槽412的上部412a。在一个实施方式中，倾角α小于其中h是介电层406的厚度或具有倾角的沟槽412的高度，且w是具有倾角的沟槽412的宽度。在一个实施方式中，具有倾角的沟槽412的高度可为约100纳米或更少，且具有倾角的沟槽412的宽度w可在约20纳米至约40纳米之间。具有倾角的沟槽412的倾角α可在约11度至约45度之间。在一个实施方式中，具有倾角的沟槽412的倾角α可为约30度。
在图4C中，可对基板402执行额外蚀刻以曝露具有更合乎外延生长需要的晶面定向的表面。例如，对于硅晶体而言，(111)晶面定向具有更紧密堆积密度，且更易于在晶面定向上生长外延薄膜。由于最常用硅基板具有(100)晶面定向，因此具有倾角的沟槽412的底表面414最有可能具有(100)晶面定向。如图4C所示，V形槽416可经蚀刻至基板402以产生具有(111)晶面定向的表面。V形槽416可通过任何适合的蚀刻工艺形成，诸如湿式或干式蚀刻方法或等离子体辅助蚀刻方法。
在一个实施方式中，种晶层418可在V形槽416上形成。种晶层418可包括具有实现V形槽416的优良覆盖能力的材料，V形槽416具有含(111)晶面定向的表面。
在一个实施方式中，当第III族-第V族结晶体将在具有倾角的沟槽412中形成时，种晶层418可包括第III族元素或第V族元素中的至少一个。在一个实施方式中，第III族元素可包括镓(Ga)或铝(Al)，且第V族元素可包括砷(As)。一个或多个第III族或第V族来源材料可用于形成种晶层418。来源材料可为金属有机前驱物或类似物。示例性第III族和第V族来源材料可包括叔丁基磷、叔丁基砷、三乙基锑、三甲基锑、三乙基镓、三甲基镓、三乙基铟、三甲基铟、氯化铟、磷化铟、氯化镓、三甲基铝，或有机磷化合物。种晶层418可通过任何适合的沉积方法形成，诸如减压化学气相沉积(chemical vapor deposition；CVD)、外延沉积，或任何其它适合的沉积方法。
在图4D中，结晶材料420在具有倾角的沟槽412中形成，且填充满具有倾角的沟槽412。结晶材料420可通过外延沉积而形成。在一个实施方式中，结晶材料420可包括二元或三元第III族-第V族材料中的一个。在一个实施方式中，结晶材料420可包括铟、镓和砷。
在一个实施方式中，结晶材料420的组成在沉积期间可变更。例如，二元或三元第III族-第V族元素的莫耳比率可经设定以在填充具有倾角的沟槽412的初期减少缺陷的产生，且经设定以在填充具有倾角的沟槽412的后期提供合乎需要的装置特性，诸如改良的迁移率。
如图4B所示，垂直线424示意性地示出一个方向，由晶格失配所产生的缺陷将沿所述方向在平行于具有倾角的沟槽412的长度(进入纸内的方向)的平面中传播。垂直线424与具有倾角的沟槽412的侧壁相交，指示缺陷在具有倾角的沟槽412的侧壁412b处终止。水平线422指示缺陷可到达的最高位准。换言之，水平线422上方的结晶材料420中可没有源于晶格失配的缺陷。在一个实施方式中，水平线422下方的结晶材料420可包括In0.3Ga0.7As(莫耳比率)以将缺陷降至最低，且水平线422上方的结晶材料420可包括In0.53Ga0.47As(莫耳比率)以获得改良的迁移率。
可将额外结构增添至装置400，以使得水平线422上方的结晶材料420充当操作区域。
或者，如图5所示，额外结晶材料可由结晶材料420形成，以产生目标装置的操作范围。可能在化学机械研磨处理之后，可在介电材料406和结晶材料420上方形成介电材料502。介电材料502可为氧化硅、氮化硅或其它适合的材料。狭窄沟槽504可贯穿介电材料502而形成以在底表面506处曝露结晶材料420的一部分。狭窄沟槽504大体上垂直于具有倾角的沟槽412且与沟槽412对准。狭窄沟槽504比具有倾角的沟槽412窄。通道材料508具有与结晶材料420大体上相同的晶格大小，通道材料508随后在狭窄沟槽504中由结晶材料420而形成。通道材料508可大体上不含迭积缺层、穿透位错以及其它缺陷。在一个实施方式中，介电材料503可具有约60纳米或更少的厚度。狭窄沟槽504可具有约5纳米至约10纳米之间的宽度。
在另一个实施方式中，如图6A-6B所示，可通过在具有倾角的沟槽412中回蚀结晶材料420而形成通道材料，以形成装置600。执行化学机械研磨以曝露介电材料406和结晶材料420的平面表面602。与具有倾角的沟槽412的狭窄展宽(stretch)重叠的掩膜604可在平面表面602上方形成。
如图6B所示，执行蚀刻处理以在结晶材料420上部形成通道材料608。在一个实施方式中，通道材料608可通过异向性湿式蚀刻形成。例如，可向所曝露的顶表面602提供异向性湿式蚀刻溶液，诸如硫酸(H2SO4)与过氧化氢(H2O2)，或柠檬酸(C6H8O7)与过氧化氢(H2O2)。在蚀刻处理之后，通道材料608可在新曝露的平面表面606上方延伸。平面表面606可位于水平线422上方以使得通道材料608由结晶材料420的部分形成，所述部分大体上不含由晶格失配产生的缺陷。
图7是根据本公开内容的一个实施方式的用于异质外延生长的方法700的流程图。方法700可用以形成包括根据本公开内容的具有倾角的沟槽的装置。
在步骤710中，非结晶层可在第一结晶材料上方形成。第一结晶材料可为结晶基板或基板上的结晶层。例如，如图2所示，非结晶材料204形成于结晶材料202之上。在一个实施方式中，第一结晶材料可为硅或掺杂硅，且非结晶材料可为介电材料。
在步骤720中，具有倾角的沟槽可贯穿非结晶层而形成，且在具有倾角的沟槽的底部曝露第一结晶材料的一部分。例如，如图2所示，具有倾角的沟槽206形成于非结晶层204之中。
具有倾角的沟槽提供自第一结晶材料的曝露部分起的边界，所述边界用于诸如外延生长的结晶生长。具有倾角的沟槽的倾角经设定以使得缺陷将在具有倾角的沟槽的非结晶倾斜侧壁处终止，所述缺陷在晶体生长期间发源于具有倾角的沟槽底部，且沿具有倾角的沟槽的长度平面而传播。在一个实施方式中，具有倾角的沟槽的侧壁在第一结晶材料的顶表面上的投影比具有倾角的沟槽的底部的投影长。此外，具有倾角的沟槽可为具高深宽比的狭窄沟槽，以使得缺陷将在具有倾角的沟槽的侧壁处终止，所述缺陷发源于具有倾角的沟槽底部，且沿具有倾角的沟槽的宽度的平面内传播。
具有倾角的沟槽可由任何适合的蚀刻方法形成。在一个实施方式中，具有倾角的沟槽可由具有倾角的离子束通过修正等离子体鞘而形成，如图3A所示。在另一个实施方式中，具有倾角的沟槽可通过相对于离子束源以一具有倾角的位置定位基板而形成，如图3B所示。
在步骤730中，可对具有倾角的沟槽底部执行可选蚀刻，以曝露第一结晶材料中的表面，所述表面对结晶生长而言合乎需要的。例如，如图4C所示，V形槽可在具有倾角的沟槽底部中形成以曝露具有(111)晶面定向的晶体表面。湿式蚀刻方法可用以执行可选蚀刻。
在步骤740中，种晶层可自具有倾角的沟槽的底表面起形成，用于进一步的外延生长。种晶层可包括具有实现第一结晶材料的曝露表面的优良覆盖能力的材料。
在步骤750中，第二结晶材料可通过外延生长而在具有倾角的沟槽中形成。在一个实施方式中，第一结晶材料和第二结晶材料具有不同晶格尺寸，且在形成期间，由于晶格失配，第二结晶材料中可能产生缺陷。如步骤720中所论述，具有倾角的沟槽的侧壁经定位以捕获并终止由晶格失配所引起的缺陷。因此，具有倾角的沟槽的顶部部分附近的第二结晶材料大体上无缺陷，因此在半导体中用作功能结构是合乎需要的，所述功能结构如FinFET中的鳍状物。
可选地，功能结构可通过额外处理在具有倾角的沟槽中由第二结晶材料而形成，如步骤750所述。在步骤760中，功能结构可通过蚀刻第二结晶材料或在第二结晶材料上方沉积第三结晶材料而形成。在一个实施方式中，功能结构可为垂直鳍状物或纳米线，所述功能结构比具有倾角的沟槽中的第二结晶材料更窄，以便在目标装置中提供合乎需要的功能。在一个实施方式中，第二结晶材料的顶部部分可经回蚀以形成更窄的功能结构，例如图6A-6B中所示。在另一个实施方式中，更窄的垂直沟槽可在第二结晶材料上方形成。第三结晶材料随后形成于更窄的垂直沟槽中以作为功能结构，例如图5中所示。
尽管本公开内容的实施方式在上文中结合在FinFET中制造外延鳍状物而进行论述，但是本公开内容可用以在任何适合的装置中形成任何适当的结构。例如，本公开内容的实施方式可用以形成纳米线，所述线可用于FinFET之后的下一代装置中。纳米线可通过使用根据上文论述的具有额外处理的实施方式的具有倾角的深宽比捕捉而形成。
尽管前述内容针对本公开内容的实施方式，但可在不脱离本公开内容基本范围的前提下设计本公开内容的其它以及另外实施方式，且本公开内容的范围由以下所附的权利要求所确定。

Claims (13)

1.一种包括具有降低的位错密度的异质外延膜的装置，所述装置包括：
第一结晶材料；
非结晶层，所述非结晶层在所述第一结晶材料上方形成，其中具有倾角的沟槽贯穿所述非结晶层而形成，以使得所述第一结晶材料处于所述具有倾角的沟槽的底部；
第二结晶材料，所述第二结晶材料通过外延生长而在所述具有倾角的沟槽中形成，其中所述第一结晶材料和所述第二结晶材料具有失配晶格尺寸，且所述具有倾角的沟槽的侧壁在所述第一结晶材料的顶表面上的投影比所述具有倾角的沟槽的所述底部的投影长；以及
所述第二结晶材料的在所述具有倾角的沟槽上方延伸的垂直部分，其中所述第二结晶材料的所述垂直部分具有比所述具有倾角的沟槽窄的宽度。
2.如权利要求1所述的装置，其中所述具有倾角的沟槽的所述侧壁与所述第一结晶材料的所述顶表面之间的倾角小于h表示所述非结晶层的厚度，且w表示所述具有倾角的沟槽沿所述第一结晶材料的所述顶表面的宽度。
3.如权利要求2所述的装置，其中所述倾角在11度至45度之间。
4.如权利要求2所述的装置，其中所述具有倾角的沟槽的深宽比h/w经设定以使得缺陷在所述具有倾角的沟槽的所述侧壁处终止，所述缺陷自所述具有倾角的沟槽的所述底部产生，且沿平行于所述具有倾角的沟槽的所述宽度的平面传播。
5.如权利要求2所述的装置，其中所述第一结晶层包括硅或掺杂硅，且所述第二结晶材料包括二元或三元材料，所述二元或三元材料包括第III族元素和第V族元素。
6.如权利要求5所述的装置，其中所述第III族元素包括镓(Ga)、铝(Al)及铟(In)中的一个，且所述第V族元素包括氮(N)、磷(P)及砷(As)中的一个。
7.如权利要求5所述的装置，其中所述非结晶层的所述厚度h小于100纳米，且所述具有倾角的沟槽的所述宽度w为20纳米至40纳米之间。
8.如权利要求1所述的装置，其中所述垂直部分通过在外延生长之后蚀刻所述第二结晶材料而形成。
9.如权利要求1所述的装置，其中所述第一结晶材料与所述第二结晶材料之间的界面具有类似于V形槽的形状。
10.一种用于形成半导体装置的方法，所述方法包括以下步骤：
在第一结晶材料上方形成非结晶层；
贯穿所述非结晶层而形成具有倾角的沟槽，以在所述具有倾角的沟槽的底部曝露所述第一结晶材料的一部分；
通过外延生长自所述具有倾角的沟槽的所述底部起形成第二结晶材料以填充所述具有倾角的沟槽，其中所述第一结晶材料和所述第二结晶材料具有失配晶格尺寸；以及
通过蚀刻所述第二结晶材料的上部或在垂直狭窄沟槽中在所述第二结晶材料上方沉积第三结晶材料而形成功能结构，所述功能结构比所述具有倾角的沟槽窄。
11.如权利要求10所述的方法，其中所述具有倾角的沟槽的侧壁与所述第一结晶材料的顶表面之间的倾角小于h表示所述非结晶层的厚度，且w表示所述具有倾角的沟槽沿所述第一结晶材料的所述顶表面的宽度。
12.如权利要求10所述的方法，其中形成所述具有倾角的沟槽的步骤包括以下步骤：
在所述非结晶层上方产生等离子体；以及
修正所述等离子体的鞘，以自所述鞘产生具有倾角的离子流且将所述具有倾角的离子流引向所述非结晶层。
13.如权利要求10所述的方法，其中形成所述具有倾角的沟槽的步骤包括以下步骤：
将离子束以一倾角引向所述非结晶层。
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