CN106057800A - 集成半导体器件 - Google Patents

集成半导体器件 Download PDF

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CN106057800A
CN106057800A CN201610207661.0A CN201610207661A CN106057800A CN 106057800 A CN106057800 A CN 106057800A CN 201610207661 A CN201610207661 A CN 201610207661A CN 106057800 A CN106057800 A CN 106057800A
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semiconductor device
transistor
normally
hemt
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G·库拉托拉
F·卡尔曼
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Infineon Technologies Austria AG
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Abstract

本申请涉及集成半导体器件。半导体器件包括第一半导体器件、第二半导体器件和第三半导体器件。第一半导体器件和第二半导体器件被集成以形成半桥。第三半导体器件是与半桥串联设置的常关型半导体器件。

Description

集成半导体器件
技术领域
本发明的实施例涉及集成半导体器件，具体地，包括半桥或全桥设置。
背景技术
美国专利No.7,550,781B2公开了集成III族氮化物功率器件，其具有至少两个半导体器件例如以半桥或全桥结构在公共管芯中的共同封装。美国专利No.6,649,287B2公开了位于硅衬底上方的GaN层结构(缓冲材料)。美国专利No.7,326,971B2公开了常关型基于GaN的HEMT(高电子迁移率器件)。
发明内容
一个实施例涉及一种集成半导体器件。该器件包括第一半导体器件、第二半导体器件和第三半导体器件。第一半导体器件和第二半导体器件被集成以形成半桥，以及第三半导体器件是被设置为与半桥串联的常关型半导体器件。
附图说明
参照附图示出和说明实施例。附图用于示出基本原理，因此仅示出了用于理解基本原理所需的方面。附图不需要按比例绘制。在附图中，相同的参考标号表示类似的特征。
图1示出了包括被设置为与常关型晶体管串联的两个高压宽带隙晶体管的半桥结构的示例性集成；
图2示出了根据图1的III-V族半桥半导体器件的示例性单片方式；
图3示出了全单片集成GaN常关型半桥设置；
图4示出了常关型全桥(H桥)的可选实施例；
图5示出了基于图4的另一可选实施例，其中附加腿(leg)(即，高侧GaN MOSFET的串联连接)被设置为与第一腿并联；以及
图6示出了基于图5的又一可选实施例，其中至少一个附加的低压常关型晶体管被放置为与低压晶体管并联。
具体实施方式
本文描述的实例尤其涉及两个或多个宽带隙晶体管以形成总体“常关型”半导体装置的结构的集成，具体为芯片或管芯，这种半导体装置可以被封装在公共封装件中。
根据示例性实施例，提供了半桥结构的III-V族半导体器件的单片集成。
本文呈现的实例具体涉及集成解决方案，其包括至少两个宽带隙晶体管，使得它们形成常关型结构。具体地，可以在单个封装件中组合包括这种晶体管的全桥结构或半桥结构。
根据示例性实施例，提供了完全单片的解决方案。
图1示出了半桥结构的示例性集成，其包括两个高压宽带隙晶体管101和102(它们可以为常开型晶体管)。每个晶体管101、102都可以是具有漏极、源极和栅极的高电子迁移率晶体管(HEMT)。晶体管101可以是高侧(HS)GaN MOSFET，以及晶体管102可以是低侧(LS)GaN MOSFET。晶体管101的漏极连接至高压，晶体管101的源极连接至晶体管102的漏极。晶体管102的源极与低压晶体管103串联连接。晶体管103是常关型晶体管，其尤其可以停止突发的短路电流。晶体管103可以是低压(LV)晶体管，其可以是Si晶体管或宽带隙器件。
图2示出了根据图1的III-V族半桥半导体器件的示例性单片方式。
在硅衬底201的顶部上是AlN层202，在层202的顶部上设置多个GaN层203和多个AlGaN层204(以交替顺序)。
在最后堆叠的AlGaN层的顶部上，设置较大的GaN层205。在GaN层205的顶部上为AlGaN阻挡层209，在AlGaN阻挡层209的顶部上设置另一个GaN层210。该层可以被称为GaN盖层。然而，GaN盖层210可以是任选的，并且具体地可以省略该层。在层210的顶部上设置钝化层211。
金属接触件(或电极)206、207和208被设置为穿过层211、210、209进入层205(事实上，到达层209和205之间的电子气)。
在钝化层211的顶部上，金属接触件(电极)212被设置在接触件208和207之间，以及金属接触件(电极)213被设置在接触件206和207之间。
接触件208对应于晶体管102的源极，接触件212对应于晶体管102的栅极，接触件207对应于晶体管101的源极和晶体管102的漏极，接触件213对应于晶体管101的栅极，并且接触件206对应于晶体管101的漏极。
低压常关型晶体管103的源极214被注入到硅衬底201中，并且其栅极为多晶硅层217的顶部上的金属接触件215，其中多晶硅层217被设置为在硅衬底201的顶部上。硅晶体管的栅极可以是金属电极或高掺杂多晶硅层。在这种金属接触件和硅衬底之间，可以夹置钝化层，例如栅极氧化物。钝化层可以包括SiO2、高k介电材料等。晶体管103的漏极216被注入到硅衬底201中并且连接至晶体管102的源极的接触件208。因此，晶体管103被集成到硅衬底201中，其顶部上生长基于GaN的技术。
在制造GaN高侧和低侧晶体管101和102之后，可以在GaN缓冲层中打开向下达到硅衬底201的沟槽(例如，经由蚀刻步骤)。该硅衬底201可以是<111>定向的，其可以不同于传统用于基于Si的技术的<100>定向。然而，这可以满足低压常关型晶体管103的需求，因为晶体管103可主要用作阻挡危险的短路电流的安全开关。可以选择该晶体管103的宽度，使得由晶体管103引入的寄生串联电阻不会显著影响整体半桥性能。
图3示出了全单片集成GaN常关型半桥装置。与图2对比，晶体管103也以GaN技术实现。该晶体管103是常关型低压类型；存在多种用于实现常关型GaN晶体管的选项，例如pGaN、凹部和氧化物、氟注入等。
根据图3，接触件208也是晶体管103的漏极。晶体管103的栅极对应于(金属)接触件301，接触件301达到阻挡层209中但不到达其下方的GaN层205。在凹部方法的情况下，栅极隔离层可以夹置在金属电极301与AlGaN阻挡层209之间。栅极隔离层可以包括任何栅极氧化物，例如SiN、高k电介质、Al2O3。晶体管103的源极对应于(金属)接触件302，接触件302到达层205中(与接触件206-208相当)。
图4示出了常关型全桥(H桥)的可选实施例，其包括两个高侧GaN MOSFET 401、402以及两个低侧GaN MOSFET 403、404，其中MOSFET 401和403串联连接且MOSFET 404和404串联连接。每个串联连接也被称为“腿”。MOSFET的两个串联连接(即，两个腿)并联装置，并且MOSFET 401-404的这种并联装置与低压常关型晶体管405串联连接。
图5示出了基于图4的另一可选实施例，其中，附加腿(即，高侧GaN MOSFET 501和低侧GaN MOSFET 502的串联连接)被设置为与包括MOSFET 401、403的第一腿和包括MOSFET 402、404的第二腿并联。因此，多于两个的腿(即，“n腿桥实施”)可以被并联装置，并且那些并联连接的腿被设置为与低压常关型晶体管450串联。
图6示出了基于图5的又一可选实施例，其中至少一个附加低压常关型晶体管601被放置为与晶体管405并联。
注意，晶体管405(和/或晶体管601)可以是低压硅晶体管或宽带隙低侧晶体管。
进一步注意，上面附图所示的GaN MOSFET是示例性n沟道MOSFET。
具体地，本文建议的实例可以基于以下解决方案中的至少一种。具体地，可以使用以下特征的组合以实现期望的结果。方法的特征可以与器件、装置或系统的任何特征进行组合，反之亦然。
提供了一种集成半导体器件。该器件包括第一半导体器件、第二半导体器件和第三半导体器件，其中第一半导体器件和第二半导体器件被集成以形成半桥，并且其中第三半导体器件是被设置为与半桥串联的常关型半导体器件。
因此，由于第三半导体器件(包括至少一个晶体管，例如场效应晶体管)，实现了整体常关型装置的集成解决方案。
包括第一半导体器件和第二半导体器件(串联)的半桥也可以被称为“腿”。可以并联装置多个这种腿。然后，将多个腿的这种并联组合与第三半导体器件串联连接以提供集成常关型装置。例如，两个腿(两个半桥)可以实现全桥(也称为H桥)。
在一个实施例中，第一半导体器件和第二半导体器件是高电子迁移率晶体管。
在一个实施例中，第一半导体器件和第二半导体器件是基于III族氮化物的半导体器件。
典型的HEMT(高电子迁移率晶体管)可以包括衬底，其可以由GaN、Si、SiC或石墨形成。在衬底上方可以设置第一III族氮化物半导体，诸如GaN。可以在第一半导体本体上方设置由不同带隙的另一III族氮化物半导体(诸如AlGaN)形成的第二半导体本体。可以具有相互堆叠设置的第一半导体和第二半导体的多层，从而形成堆叠层结构(或缓冲器)。
在一个实施例中，第一半导体器件和第二半导体器件是常开型晶体管。
在一个实施例中，第三半导体器件包括至少一个常关型晶体管。
具体地，常关型晶体管是低压场效应晶体管。
在一个实施例中，第三半导体器件包括至少两个常关型晶体管，它们相互并联设置。
在一个实施例中，第三半导体器件是基于III族氮化物的半导体器件。
在一个实施例中，第三半导体器件在GaN缓冲器的沟槽中实现。
在一个实施例中，该器件还包括第四半导体器件和第五半导体器件，其中第一、第二、第四和第五半导体器件被耦合以形成H桥。
这种H桥也被称为全桥。注意，总共n个的半桥腿可以相互并联设置以实现n腿桥。n个半桥腿与第三半导体器件串联连接。
在一个实施例中，第四半导体器件和第五半导体器件是高电子迁移率晶体管。
在一个实施例中，第四半导体器件和第五半导体器件是基于III族氮化物的半导体器件。
在一个实施例中，第四半导体器件和第五半导体器件是常开型晶体管。
尽管公开了本发明的各个示例性实施例，但本领域技术人员明白，在不背离本发明的精神和范围的情况下可以进行各种改变和修改来实现本发明的一些优势。本领域技术人员应该理解，可以适当地替代执行相同功能的其他部件。应该提及的是，参照特定附图解释的特征可以与其他附图的特征进行组合，即使在文中没有明确提及。此外，可以在使用适当的处理器指令全部利用软件来实现本发明的方法，或者以利用硬件逻辑和软件逻辑的组合的混合实施来实现相同的结果。旨在通过所附权利要求来覆盖对发明概念的这种修改。

Claims (19)

1.一种集成半导体器件，包括：
第一半导体器件；
第二半导体器件；以及
第三半导体器件，
其中，所述第一半导体器件和所述第二半导体器件被集成以形成半桥；并且
其中，所述第三半导体器件包括被设置为与所述半桥串联的常关型半导体器件。
2.根据权利要求1所述的器件，其中，所述第一半导体器件和所述第二半导体器件包括高电子迁移率晶体管。
3.根据权利要求1所述的器件，其中，所述第一半导体器件和所述第二半导体器件包括基于III族氮化物的半导体器件。
4.根据权利要求1所述的器件，其中，所述第一半导体器件和所述第二半导体器件包括常开型晶体管。
5.根据权利要求1所述的器件，其中，所述第三半导体器件包括常关型晶体管。
6.根据权利要求1所述的器件，其中，所述第三半导体器件包括被设置为相互并联的多个常关型晶体管。
7.根据权利要求1所述的器件，其中，所述第三半导体器件包括基于III族氮化物的半导体器件。
8.根据权利要求1所述的器件，其中，所述第三半导体器件在GaN缓冲器的沟槽中实施。
9.根据权利要求1所述的器件，还包括第四半导体器件和第五半导体器件，其中所述第一半导体器件、所述第二半导体器件、所述第四半导体器件和所述第五半导体器件被耦合以形成H桥。
10.根据权利要求9所述的器件，其中，所述第四半导体器件和所述第五半导体器件包括高电子迁移率晶体管。
11.根据权利要求9所述的器件，其中，所述第四半导体器件和所述第五半导体器件包括基于III族氮化物的半导体器件。
12.根据权利要求9所述的器件，其中，所述第四半导体器件和所述第五半导体器件包括常开型晶体管。
13.一种集成半导体器件，包括：
第一常开型高电子迁移率晶体管；
第二常开型高电子迁移率晶体管，其中所述第一高电子迁移率晶体管和所述第二高电子迁移率晶体管被集成以形成半桥；以及
常关型晶体管，被设置为与所述半桥串联。
14.根据权利要求13所述的器件，其中，所述第一高电子迁移率晶体管和所述第二高电子迁移率晶体管包括基于III族氮化物的半导体器件。
15.根据权利要求13所述的器件，还包括被设置为与所述常关型晶体管并联的第二常关型晶体管。
16.根据权利要求13所述的器件，其中，所述常关型晶体管包括基于III族氮化物的半导体器件。
17.根据权利要求13所述的器件，其中，在GaN缓冲器的沟槽中实施所述常关型晶体管。
18.根据权利要求13所述的器件，还包括第三常开型高电子迁移率晶体管和第四常开型高电子迁移率晶体管，其中，所述第一高电子迁移率晶体管、所述第二高电子迁移率晶体管、所述第三高电子迁移率晶体管和所述第四高电子迁移率晶体管被耦合以形成H桥。
19.根据权利要求18所述的器件，其中，所述第三高电子迁移率晶体管和所述第四高电子迁移率晶体管包括基于III族氮化物的半导体器件。
CN201610207661.0A 2015-04-06 2016-04-05 集成半导体器件 Pending CN106057800A (zh)

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