CN105990452B - 具有可调整击穿电压的齐纳二极管 - Google Patents

具有可调整击穿电压的齐纳二极管 Download PDF

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CN105990452B
CN105990452B CN201510818928.5A CN201510818928A CN105990452B CN 105990452 B CN105990452 B CN 105990452B CN 201510818928 A CN201510818928 A CN 201510818928A CN 105990452 B CN105990452 B CN 105990452B
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R·西莫拉
P·弗纳拉
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STMicroelectronics Rousset SAS
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Abstract

本发明涉及具有可调整击穿电压的齐纳二极管。本发明涉及一种齐纳二极管，包括：形成在半导体衬底(SUB)中并且平行于在阴极区域(CD1)与阳极区域(AD1)之间的衬底的表面的齐纳二极管结、被配置成在受到适当的电压时生成垂直于齐纳二极管结的第一电场的传导区域(BDC，EDC，ED1，NW)、以及被配置成在受到适当的电压时生成在齐纳二极管结的平面中的第二电场的传导区域(GT1，GTC)。

Description

具有可调整击穿电压的齐纳二极管
技术领域
本发明涉及齐纳二极管。
背景技术
齐纳二极管通常用于调节电路中的电压或者用于供应稳定的参考电压。出于这一目的，齐纳二极管与电压源反向并联连接。当由电压源供应的电压达到二极管的击穿电压时，二极管变为传导并且然后将电压维持在这一值。
图1是形成在由第一传导类型(例如P类型)的半导体材料形成的衬底中的常规齐纳二极管的横截面。齐纳二极管包括具有形成齐纳二极管的阳极区域的第二传导类型(例如N类型)的掺杂的阱NW。齐纳二极管包括形成在阱NW中的第一P+传导类型的高掺杂的阴极区域CD。区域CD形成在具有第二N+传导类型的高掺杂的区域ZD中。区域CD和ZD通过浅沟槽隔离STI与阱NW的其余部分隔离。齐纳二极管包括形成在阱NW中并且通过沟槽STI与阴极区域隔离的第二N+传导类型的高掺杂的阳极连接区域ED。另外，衬底SUB包括形成衬底SUB的偏置区域的第一P+传导类型的高掺杂的区域SP。衬底偏置区域SP通过浅沟槽隔离STI与区域CD、ZD隔离。
图2表示根据在区域CD与ED之间施加的反向电压穿过齐纳二极管的电流的变化的曲线C11。曲线C11示出常规反向偏置的齐纳二极管的操作。在0与近似2.5V之间，穿过二极管的电流保持为低(低于10-12A)。从近似2.5V直到近似5.2V，穿过二极管的电流线性增加(根据对数尺度)直到近似10-8A。由于所谓的“带到带”现象引起的这一操作区不可以用于供应参考电压或者执行电压调节。在近似2.5V以上，出现击穿现象，二极管通过雪崩效应变为高度传导，同时达到近似5.5V的被称为“击穿电压”的最大电压BV。二极管将这一电压保持恒定而不管电流的强度，假定电流保持在近似10-8A到10-6A之间。齐纳二极管通常在该操作区中使用，以供应稳定的参考电压或者执行电压调节。
已经做出的一个提议包括制造将若干分立部件组合的电路以使用控制输入来复制齐纳二极管的操作以调整齐纳二极管的击穿电压。因此，被标记为TL431的电路以类似于齐纳二极管的方式工作，其击穿电压可以通过向电路的控制端子提供的电压值来调整。然而，由于包括几十个分立部件(包括多于十个晶体管)这一事实，这一电路十分复杂并且尺寸很大。
发明内容
因此期望制造具有可调整击穿电压的齐纳二极管。还期望能够通过实现通常用于制造CMOS晶体管的制造步骤以集成电路中的分立部件的形式来制造这一二极管。
一些实施例涉及一种齐纳二极管，包括：形成在半导体衬底中并且平行于在阴极区域与具有第一传导类型的阳极区域之间的衬底的表面的齐纳二极管结，阴极区域由在衬底的表面上的具有第二传导类型的区域形成；被配置成在受到适当的电压时生成垂直于齐纳二极管结的第一电场的第一传导区域。根据一个实施例，齐纳二极管包括被配置成在受到适当的电压时生成沿着齐纳二极管结的平面的第二电场的第二传导区域。
根据一个实施例，第二传导区域包括仅通过介电层与齐纳二极管结分离的嵌入式栅极。
根据一个实施例，介电层具有在15到25nm之间的厚度。
根据一个实施例，栅极将阴极区域与阳极连接区域隔离。
根据一个实施例，栅极环绕齐纳二极管结。
根据一个实施例，栅极具有八边形或矩形形状。
根据一个实施例，齐纳二极管包括：形成在半导体衬底中并且具有第二传导类型并且形成阳极区域的阱，以及形成在衬底的表面上的阱中并且与阴极区域隔离的第二传导类型的阳极连接区域。
根据一个实施例，阱通过浅沟槽隔离与衬底隔离。
根据一个实施例，齐纳二极管包括布置在阳极区域与阴极区域之间的第一传导类型的薄区域。
一些实施例还可以涉及包括如先前定义的齐纳二极管的电路。
一些实施例还可以涉及用于控制如先前定义的齐纳二极管的方法，过程包括以下步骤：向阴极区域施加第一电压；向阳极区域施加第二电压以反向偏置齐纳二极管，第一电压与第二电压之间的差大于或等于齐纳二极管的击穿电压。根据一个实施例，方法包括向第二传导区域施加第三电压以生成沿着齐纳二极管结的平面的电场的步骤。
根据一个实施例，第三电压通过嵌入式栅极被施加给第二传导区域，嵌入式栅极仅通过介电层与齐纳二极管结分离。
根据一个实施例，控制方法包括根据齐纳二极管要达到的击穿电压来调整第三电压的步骤。
根据一个实施例，击穿电压能够通过引起第三电压在第一电压与第二电压之间变化而在5到13V之间调整。
附图说明
下面关于而非限于附图来描述本发明的实施例的一些示例，在附图中：
图1(以上描述)是常规齐纳二极管的横截面；
图2(以上描述)表示根据常规齐纳二极管的端子处的电压的电流的特性曲线；
图3是根据一个实施例的齐纳二极管的横截面；
图4是图3的齐纳二极管的详细的部分横截面；
图5表示根据图3的齐纳二极管的端子处的电压的电流的特性曲线；
图6表示根据栅极电压的齐纳二极管的击穿电压的变化的曲线；
图7是根据一个实施例的齐纳二极管的俯视图；
图8和9是根据另一实施例的齐纳二极管的横截面和俯视图；
图10是根据另一实施例的图7的二极管的俯视图；
图11和12是根据另一实施例的齐纳二极管的横截面和俯视图；
图13是根据另一实施例的图10的齐纳二极管的俯视图；以及
图14是根据一个实施例的齐纳二极管的横截面。
具体实施方式
图3表示根据一个实施例的齐纳二极管ZR。齐纳二极管形成在阱NW中，阱NW形成在由具有第一传导类型(例如P类型)的掺杂的半导体材料制成的衬底SUB中。阱NW具有第二传导类型(N类型)的掺杂。齐纳二极管ZR包括具有形成在构成阳极区域的阱NW中的第一传导类型(例如P+类型)的高掺杂的阴极区域CD1。阱NW通过浅沟槽隔离STI1与衬底SUB的其余部分隔离。齐纳二极管ZR还包括形成阱NW的偏置区域并且因此形成二极管ZR的阳极的连接区域的第二传导类型(N+类型)的高掺杂区域ED1。另外，衬底SUB包括形成衬底SUB的偏置区域的第一传导类型(P+类型)的一个或多个高掺杂的区域SP1。齐纳二极管ZR还包括形成在区域CD1上的阴极接触焊盘CDC以及形成在区域ED1上的阳极接触焊盘EDC。衬底的一个或多个偏置接触SPC形成在衬底SUB的偏置区域SPP上。
根据一个实施例，齐纳二极管ZR包括竖直嵌入式栅极GT1，竖直嵌入式栅极GT1形成在阱NW中，以便仅通过栅极氧化物层GTD与阴极区域CD1以及特别地与在区域CD1与由阱NW形成的阳极区域之间的二极管ZR的结区域PN分离。提供栅极GT1以通过栅极接触焊盘GTC来接收偏置电压GV。电压GV可以由电路CMD来供应，电路CMD还向阴极接触焊盘CDC供应阴极电压CV并且向阳极接触焊盘EDC供应阳极电压。
为了增加形成齐纳二极管的结PN的P+与N掺杂之间的过渡斜坡，并且因此获得“突变”结PN，可以在具有第二N+传导类型的高掺杂的相对薄的区域ZD1上形成区域CD1。然而，区域ZD1保持可选并且在期望减小通过引起向栅极GTC施加的电压发生变化而容易被达到的击穿电压BV的范围的情况下，可以被提供。
栅极GT1可以通过在衬底SUB中蚀刻孔或沟槽、通过在沟槽的壁上和底部形成介电层GTD(例如通过氧化)、并且然后通过用诸如金属或多晶硅等传导材料填充沟槽来制造。这些制造步骤、以及使得不同掺杂区域和沟槽STI能够被形成的这些步骤通常被实现以制造基于CMOS晶体管的电路。介电或栅极氧化物层GTD可以具有在15nm到25nm之间、例如在20nm数量级的厚度以获得大于5V的击穿电压。
图4更详细地表示形成在区域CD1与阱NW之间的齐纳二极管ZR的结PN以及特别地在结PN与栅极GT1之间的接触区域。当齐纳二极管ZR被反向偏置时，阴极接触焊盘CDC接收低于向阱NW的偏置接触焊盘EDC施加的电压的电压，例如被设置为0V的电压。在这些情况下，二极管ZR的结PN的区域中出现从阱NW朝向区域CD1的、方向垂直于衬底SUB的表面的电场Ez。如果栅极GT1接收到正的电压，则阴极CD1与形成在阱NW中的阳极区域之间的结PN的平面中也出现方向朝着栅极GT1的电场Ex。电场Ez和Ex的同时出现形成具有被定位在场Ez与Ex的方向之间的有角扇形中的方向的所得到的场Er。可见，场Er的幅度大于场Ez。除了增加电场这一效果，还存在接近效应，因为栅极GT1与结PN直接接触。结果是，在结PN处出现的电荷受到更高的电场并且因此在向区域CD1施加的较低电压的影响下变为移动，这一移动性(mobility)通过雪崩效应产生击穿现象。因此，栅极GT1在此用作电传导元件以将电压带到齐纳二极管的结PN的附近，以便产生电场Ex。
图5表示在向阴极区域CD1施加的电压CV在0到-15V之间变化时根据电压CV穿过齐纳二极管ZR的电流的变化的曲线C12、C13、C14，其中向阳极连接区域ED1施加的电压AV例如被设置为0V。二极管ZR因此被反向偏置。曲线C12通过向栅极GT1施加等于阳极电压AV的电压GV(0V)来获得。曲线C13通过向栅极GT1施加大于阳极电压AV的电压(近似3V)来获得，并且曲线C14通过向栅极GT1施加低于阳极电压AV的电压GV(近似-3V)来获得。在用于曲线C12的0与近似8.5V之间，在用于曲线C13的0与6.5V之间，以及在用于曲线C14的0与近似11V之间，穿过二极管ZR的电流根据对数尺度线性增加，同时保持非常低(低于5·10-8A)。在这些值以上，出现击穿现象，二极管ZR在用于曲线C12的近似9V的击穿电压BV2、用于曲线C13的近似7V的击穿电压BV3、以及用于曲线C14的近似11.4V的击穿电压BV4处变为高度传导。二极管ZR保持这一电压BV2、BV3、BV4恒定，而不管电流的强度，假定电流保持大于近似10-6A。曲线C12、C13和C14的比较示出栅极GT1上的电压的施加使得能够引起二极管ZR的击穿电压发生变化。
根据一个实施例，例如通过电路CMD通过调整向栅极GT1施加的电压GV来控制二极管ZR的击穿电压。以这一方式，齐纳二极管ZR可以用于产生可调整参考电压源或具有可调整设定点电压的电压调节器。
图6表示根据向栅极GT1施加的电压GV的二极管ZR的击穿电压BV的变化的曲线C15。曲线C15示出二极管ZR的击穿电压BV在栅极电压GT1从-6V增加到3V时从近似12.7V到6.7V基本上线性减小，其中阳极电压AV被设置为0V。应当注意，通过再次增加栅极电压GT1，可以将击穿电压减小到5V，并且通过减小栅极电压，击穿电压可以达到13V。
图7表示根据一个实施例的齐纳二极管ZR。在图7上，栅极GT1将区域CD1、ZD1与偏置区域ED1隔离。沟槽ST1环绕包括区域CD1、ZD1、栅极GT1以及区域ED1的区。可以在二极管ZR周围形成由沟槽ST1界定的用于偏置衬底SUB的一个或多个区域SP1。
图8和9表示根据另一实施例的齐纳二极管ZR1。在图8和9上，二极管ZR1包括阴极区域CD2，阴极区域CD2具有第一传导类型(P+类型)的高掺杂，被叠加在具有第二传导类型(N+类型)的高掺杂的区域ZD2上。区域CD2、ZD2形成在具有第二传导类型(N类型)的掺杂并且形成在衬底SUB中的阱NW中。
根据一个实施例，嵌入式栅极GT2形成在区域DB2、ZD2中，以便与二极管ZR1的结PN接触。包括栅极GT2的区域CD2、ZD2通过浅沟槽隔离STI2与阱NW的其余部分隔离。齐纳二极管ZR1还包括在阱NW中的第二传导类型(N+类型)的高掺杂的区域ED2，其形成用于偏置阱NW并且用于连接二极管ZR1的阳极的区域。阱NW通过浅沟槽隔离ST3与衬底SUB的其余部分隔离。另外，衬底SUB包括形成衬底SUB的偏置区域的第一传导类型(P+类型)的一个或多个高掺杂的区域SP1。齐纳二极管ZR1还包括形成在区域CD2上的阴极接触焊盘CDC、形成在区域ED2上的阳极接触焊盘EDC、以及形成在栅极GT2上的栅极接触焊盘GTC。一个或多个偏置接触SPC形成在衬底SUB的偏置区域SPP上。
在图9上，沟槽隔离STI2、STI3隔离三个区域，即中央区域以及在中央区域的任一侧上的包括阳极连接区域ED2的两个侧面区域。中央区域包括栅极GT2以及在栅极的任一侧的阴极区域CD2。
图10表示根据另一实施例的具有可以类似于图8的横截面配置的齐纳二极管ZR2。二极管ZR2包括叠加在阳极区域上的、环绕嵌入式栅极GT3的阴极区域CD3，阴极区域CD3被沟槽隔离STI4环绕。二极管ZR2还包括环绕沟槽隔离STI4并且通过沟槽隔离STI5与衬底SUB隔离的阳极连接区域ED3。阴极区域CD3和阳极连接区域ED3以及沟槽STI4、STI5具有八边形形状。栅极GT3可以具有正方形形状或者更一般地具有矩形或甚至八边形形状。
图11和12表示包括叠加在具有第二传导类型(N+类型)的高掺杂的区域ZD4上的具有第一传导类型(P+类型)的高掺杂的阴极区域CD4的齐纳二极管ZR3。区域CD4、ZD4形成在阱NW中并且通过形成在环绕区域CD4、ZD4的沟槽中的嵌入式栅极GT4与阱NW的其余部分隔离。在阱NW中沿着栅极GT4的外部边缘形成有阳极连接区域ED4。阱NW通过环绕栅极GT4和阳极连接区域ED4的沟槽隔离STI6与衬底SUB隔离。
图13表示根据另一实施例的具有可以类似于图11的横截面配置的齐纳二极管ZR4。二极管ZR4包括叠加在阳极区域上并且被嵌入式栅极GT5环绕的阴极区域CD5，栅极GT5被阳极连接区域ED5环绕。二极管ZR4还包括将阳极连接区域ED5和阱NW与衬底SUB隔离的浅沟槽隔离STI7。阴极区域CD5和阳极连接区域ED5、以及栅极GT5和沟槽STI7具有八边形形状。
本领域技术人员应当理解，本发明容许各种替选实施例和各种应用。特别地，本发明不限于所呈现的齐纳二极管的不同区域的形状。特别地，主要在不希望减小通过引起向栅极GT2、GT3、GT4、GT5施加的电压发生变化来容易被达到的击穿电压的范围的情况下，可以省略区域ZD2和ZD4。可以针对齐纳二极管的不同区域考虑除了所描述的矩形和八边形形状之外的其他形状。因此，可以针对这些区域考虑圆形和正方形形状以及其他多边形形状。
另外，在以上描述的所有实施例中，可以反转形成齐纳二极管的不同区域的掺杂的传导类型。因此，图14表示具有形成在具有第一传导类型(P类型)的掺杂的阱PW中的二极管ZR的形状的齐纳二极管ZR5，其中阱PW形成在通过在衬底SUB中深度注入第二传导类型(N类型)的掺杂剂来形成的阱N0中。如以上，阱PW通过沟槽隔离STI8与阱N0隔离。阱N0可以通过浅沟槽隔离STI9与衬底SUB隔离。二极管ZR5包括嵌入在阱PW中的竖直栅极GT6。在图14的示例中，栅极GT6在具有沟槽隔离STI8的一侧界定叠加在第一传导类型(P+类型)的高掺杂的区域ZD6上的第二传导类型(N+类型)的高掺杂的阴极区域CD6。栅极GT6在具有沟槽隔离STI8的另一侧界定第一传导类型(P+类型)的高掺杂的阳极连接区域ED6。区域CD6和ED6顶部设有相应的接触焊盘CDC和EDC。阱N0通过第二传导类型(N+类型)的高掺杂的偏置区域SNC被偏置(接地)，每个偏置区域顶部设有偏置接触焊盘SNC。应当注意，通过向阴极接触焊盘CDC施加大于向接触焊盘EDC施加的电压的电压以偏置阱PW来反向偏置齐纳二极管ZR5。在此，可以出于与先前所提及的相同的原因再次省略区域ZD6。
另外，不言而喻，可以按照不同的方式来组合以上描述的各种实施例，同时保持在本发明的框架内。

Claims (13)

1.一种齐纳二极管，包括：
齐纳二极管结，形成在半导体衬底中，在阴极区域与阳极区域之间，并且平行于所述衬底的表面，所述阳极区域具有第一传导类型，所述阴极区域由在所述衬底的所述表面上的具有第二传导类型的区域形成；以及
第一传导区域，被配置成在受到适当的电压时生成垂直于所述齐纳二极管结的第一电场，
其特征在于，所述齐纳二极管包括第二传导区域，所述第二传导区域被配置成在受到适当的电压时生成沿着所述齐纳二极管结的平面的第二电场，
其中所述第二传导区域包括仅通过介电层与所述齐纳二极管结分离的嵌入式栅极。
2.根据权利要求1所述的齐纳二极管，其中所述介电层具有在15到25nm之间的厚度。
3.根据权利要求1或2所述的齐纳二极管，其中所述栅极将所述阴极区域与阳极连接区域隔离。
4.根据权利要求1或2所述的齐纳二极管，其中所述栅极环绕所述齐纳二极管结。
5.根据权利要求1或2所述的齐纳二极管，其中所述栅极具有八边形或矩形形状。
6.根据权利要求1或2所述的齐纳二极管，包括：
阱，形成在所述半导体衬底中并且具有所述第二传导类型并且形成所述阳极区域，以及
所述第二传导类型的阳极连接区域，形成在所述衬底的所述表面上的所述阱中并且与所述阴极区域隔离。
7.根据权利要求6所述的齐纳二极管，其中所述阱通过浅沟槽隔离与所述衬底隔离。
8.根据权利要求1或2所述的齐纳二极管，包括布置在所述阳极区域与所述阴极区域之间的所述第一传导类型的薄区域。
9.一种电路，包括根据权利要求1到8中的一项所述的齐纳二极管。
10.一种用于控制根据权利要求1到8中的一项所述的齐纳二极管的方法，所述方法包括以下步骤：
向所述阴极区域施加第一电压；以及
向所述阳极区域施加第二电压以反向偏置所述齐纳二极管，所述第一电压与所述第二电压之间的差等于或大于所述齐纳二极管的击穿电压，
其特征在于，所述方法包括向所述第二传导区域施加第三电压以生成沿着所述齐纳二极管结的平面的电场的步骤。
11.根据权利要求10所述的方法，其中通过嵌入式栅极向所述第二传导区域施加所述第三电压，所述嵌入式栅极仅通过介电层与所述齐纳二极管结分离。
12.根据权利要求10或11所述的方法，包括根据所述齐纳二极管要达到的击穿电压来调整所述第三电压的步骤。
13.根据权利要求10或11所述的方法，其中所述击穿电压能够通过引起所述第三电压在所述第一电压与所述第二电压之间变化而在5到13V之间调整。
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CN105990452A (zh) 2016-10-05
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US20170148926A1 (en) 2017-05-25
FR3033938B1 (fr) 2018-04-27
US20160276447A1 (en) 2016-09-22
FR3033938A1 (fr) 2016-09-23
CN111599871A (zh) 2020-08-28
US9577053B2 (en) 2017-02-21

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