CN105988464A - 半导体装置、电子装置以及用于半导体装置的自诊断方法 - Google Patents

半导体装置、电子装置以及用于半导体装置的自诊断方法 Download PDF

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Publication number
CN105988464A
CN105988464A CN201610128485.1A CN201610128485A CN105988464A CN 105988464 A CN105988464 A CN 105988464A CN 201610128485 A CN201610128485 A CN 201610128485A CN 105988464 A CN105988464 A CN 105988464A
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CN
China
Prior art keywords
scan
semiconductor device
circuit
self
memory
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Pending
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CN201610128485.1A
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English (en)
Chinese (zh)
Inventor
西川卓郎
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN105988464A publication Critical patent/CN105988464A/zh
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B23/00—Testing or monitoring of control systems or parts thereof
    • G05B23/02—Electric testing or monitoring
    • G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
    • G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318569—Error indication, logging circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
CN201610128485.1A 2015-03-20 2016-03-08 半导体装置、电子装置以及用于半导体装置的自诊断方法 Pending CN105988464A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015058012A JP6491507B2 (ja) 2015-03-20 2015-03-20 半導体装置、電子装置および半導体装置の自己診断方法
JP2015-058012 2015-03-20

Publications (1)

Publication Number Publication Date
CN105988464A true CN105988464A (zh) 2016-10-05

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CN201610128485.1A Pending CN105988464A (zh) 2015-03-20 2016-03-08 半导体装置、电子装置以及用于半导体装置的自诊断方法

Country Status (3)

Country Link
US (2) US9797950B2 (enExample)
JP (1) JP6491507B2 (enExample)
CN (1) CN105988464A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108958209A (zh) * 2017-05-22 2018-12-07 瑞萨电子株式会社 半导体器件和控制半导体器件的方法
CN109061432A (zh) * 2014-10-29 2018-12-21 因诺帝欧股份有限公司 Ic芯片的测试装置、方法及系统和计算机可读记忆媒体
CN110161399A (zh) * 2018-02-12 2019-08-23 三星电子株式会社 半导体器件

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10649028B2 (en) 2016-01-05 2020-05-12 International Business Machines Corporation Logic built in self test circuitry for use in an integrated circuit with scan chains
US10088524B2 (en) 2016-01-05 2018-10-02 International Business Machines Corporation Logic built in self test circuitry for use in an integrated circuit with scan chains
JP6419140B2 (ja) 2016-12-08 2018-11-07 ウィンボンド エレクトロニクス コーポレーション 半導体装置およびその調整方法
JP6832787B2 (ja) * 2017-04-28 2021-02-24 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置のテスト方法
JP2019049884A (ja) * 2017-09-11 2019-03-28 株式会社東芝 画像処理装置、および故障診断制御方法
KR102035421B1 (ko) * 2018-05-08 2019-10-22 한양대학교 에리카산학협력단 Ic chip의 저전력 테스트 방법 및 장치
JP6611877B1 (ja) 2018-07-25 2019-11-27 三菱電機株式会社 半導体集積回路および回転検出装置
KR102551551B1 (ko) 2018-08-28 2023-07-05 삼성전자주식회사 이미지 센서의 구동 방법 및 이를 수행하는 이미지 센서
US10976366B2 (en) * 2018-10-19 2021-04-13 Silicon Laboratories Inc. Two pin scan interface for low pin count devices
JP2020165780A (ja) * 2019-03-29 2020-10-08 ローム株式会社 半導体集積回路
JP7305583B2 (ja) * 2020-03-05 2023-07-10 株式会社東芝 半導体集積回路
EP4112680A1 (de) 2021-06-29 2023-01-04 Evonik Operations GmbH Flammgeschützte polyamid-formmassen für die isolation von elektrischen bauteilen
US12092689B2 (en) 2021-12-08 2024-09-17 Qorvo Us, Inc. Scan test in a single-wire bus circuit
CN118633029A (zh) * 2022-01-05 2024-09-10 谷歌有限责任公司 高吞吐量扫描架构
US12182052B2 (en) 2022-01-20 2024-12-31 Qorvo Us, Inc. Slave-initiated communications over a single-wire bus
CN115201669B (zh) * 2022-09-16 2022-11-15 中诚华隆计算机技术有限公司 一种芯片内部电路检测方法和装置
WO2024147381A1 (ko) * 2023-01-05 2024-07-11 엘지전자 주식회사 전자 장치 및 그 동작 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272653B1 (en) * 1997-11-14 2001-08-07 Intrinsity, Inc. Method and apparatus for built-in self-test of logic circuitry
US20030115525A1 (en) * 2001-12-18 2003-06-19 Mentor Graphics Corporation Restartable logic bist controller
CN1469451A (zh) * 2002-07-15 2004-01-21 萧正杰 用于集成电路上的芯片间晶片级信号传输方法
US20050097418A1 (en) * 2003-10-30 2005-05-05 Kenichi Anzou Semiconductor integrated circuit
CN101627314A (zh) * 2007-03-08 2010-01-13 晶像股份有限公司 用来防止扫描移位期间的峰值功率问题的电路系统
CN101663648A (zh) * 2007-02-12 2010-03-03 明导公司 低功耗扫描测试技术及装置
US20120242368A1 (en) * 2011-03-25 2012-09-27 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method for designing the same

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0789143B2 (ja) * 1988-12-08 1995-09-27 日本電気株式会社 半導体集積回路装置
US5951703A (en) * 1993-06-28 1999-09-14 Tandem Computers Incorporated System and method for performing improved pseudo-random testing of systems having multi driver buses
US6028983A (en) * 1996-09-19 2000-02-22 International Business Machines Corporation Apparatus and methods for testing a microprocessor chip using dedicated scan strings
US5991909A (en) * 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
US5761215A (en) * 1997-06-03 1998-06-02 Motorola, Inc. Scan based path delay testing of integrated circuits containing embedded memory elements
US6966021B2 (en) * 1998-06-16 2005-11-15 Janusz Rajski Method and apparatus for at-speed testing of digital circuits
US6405355B1 (en) * 1999-03-24 2002-06-11 Synopsys, Inc. Method for placement-based scan-in and scan-out ports selection
US6463561B1 (en) * 1999-09-29 2002-10-08 Agere Systems Guardian Corp. Almost full-scan BIST method and system having higher fault coverage and shorter test application time
US6615380B1 (en) * 1999-12-21 2003-09-02 Synopsys Inc. Dynamic scan chains and test pattern generation methodologies therefor
US7577540B2 (en) * 2002-03-01 2009-08-18 Nec Corporation Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards
US7185253B2 (en) * 2002-03-27 2007-02-27 Intel Corporation Compacting circuit responses
JP2003332443A (ja) * 2002-05-08 2003-11-21 Toshiba Corp 半導体集積回路とその設計支援装置およびテスト方法
JP2004152027A (ja) * 2002-10-30 2004-05-27 Matsushita Electric Ind Co Ltd 不揮発性メモリ内蔵マイクロコンピュータチップ、及びその検査方法
EP1475644A1 (en) * 2003-04-29 2004-11-10 Koninklijke Philips Electronics N.V. Data compression
JP4317715B2 (ja) * 2003-07-01 2009-08-19 株式会社日立製作所 自己診断型論理回路
US7134061B2 (en) * 2003-09-08 2006-11-07 Texas Instruments Incorporated At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
US7296249B2 (en) * 2003-10-10 2007-11-13 Thomas Hans Rinderknecht Using constrained scan cells to test integrated circuits
US7502978B2 (en) * 2004-12-21 2009-03-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for reconfiguring scan chains
US7487419B2 (en) * 2005-06-15 2009-02-03 Nilanjan Mukherjee Reduced-pin-count-testing architectures for applying test patterns
JP2007226711A (ja) * 2006-02-27 2007-09-06 Hitachi Ltd 集積回路装置、集積回路装置の診断方法、および診断回路
WO2008008546A2 (en) * 2006-07-14 2008-01-17 Xinghao Chen Universal reconfigurable scan architecture
JP4802139B2 (ja) * 2007-05-15 2011-10-26 株式会社東芝 半導体集積回路モジュール
US7962885B2 (en) * 2007-12-04 2011-06-14 Alcatel-Lucent Usa Inc. Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing
JP2009188881A (ja) * 2008-02-08 2009-08-20 Renesas Technology Corp 半導体装置
JP2010157009A (ja) * 2008-12-26 2010-07-15 Renesas Technology Corp Ｅｄａツール、半導体装置およびスキャンチェイン構成方法
US7937634B2 (en) * 2009-02-17 2011-05-03 Almukhaizim Sobeeh A Circuit and method providing dynamic scan chain partitioning
JP2010281609A (ja) * 2009-06-02 2010-12-16 Fujitsu Semiconductor Ltd 試験方法及び半導体装置
JP5347951B2 (ja) * 2009-12-24 2013-11-20 富士通セミコンダクター株式会社 集積回路及び故障診断回路
US8458543B2 (en) * 2010-01-07 2013-06-04 Freescale Semiconductor, Inc. Scan based test architecture and method
IT1398937B1 (it) * 2010-02-17 2013-03-28 St Microelectronics Srl Metodo per eseguire un testing elettrico di dispositivi elettronici
US9316690B2 (en) * 2010-03-19 2016-04-19 Qualcomm Incorporated Data recirculation in configured scan paths
US20120054564A1 (en) * 2010-08-27 2012-03-01 Abhishek Kumar Tiwary Method and apparatus to test memory using a regeneration mechanism
US8438433B2 (en) * 2010-09-21 2013-05-07 Qualcomm Incorporated Registers with full scan capability
US8856602B2 (en) * 2011-12-20 2014-10-07 International Business Machines Corporation Multi-core processor with internal voting-based built in self test (BIST)
US9377510B2 (en) * 2012-12-28 2016-06-28 Nvidia Corporation System for reducing peak power during scan shift at the global level for scan based tests
JP5583244B1 (ja) * 2013-06-10 2014-09-03 三菱電機株式会社 集積回路素子を有する電子制御装置及びその集積回路素子の単品検査装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272653B1 (en) * 1997-11-14 2001-08-07 Intrinsity, Inc. Method and apparatus for built-in self-test of logic circuitry
US20030115525A1 (en) * 2001-12-18 2003-06-19 Mentor Graphics Corporation Restartable logic bist controller
CN1469451A (zh) * 2002-07-15 2004-01-21 萧正杰 用于集成电路上的芯片间晶片级信号传输方法
US20050097418A1 (en) * 2003-10-30 2005-05-05 Kenichi Anzou Semiconductor integrated circuit
CN101663648A (zh) * 2007-02-12 2010-03-03 明导公司 低功耗扫描测试技术及装置
CN101627314A (zh) * 2007-03-08 2010-01-13 晶像股份有限公司 用来防止扫描移位期间的峰值功率问题的电路系统
US20120242368A1 (en) * 2011-03-25 2012-09-27 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method for designing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109061432A (zh) * 2014-10-29 2018-12-21 因诺帝欧股份有限公司 Ic芯片的测试装置、方法及系统和计算机可读记忆媒体
CN109061432B (zh) * 2014-10-29 2020-09-04 因诺帝欧股份有限公司 Ic芯片的测试装置、方法及系统和计算机可读记忆媒体
CN108958209A (zh) * 2017-05-22 2018-12-07 瑞萨电子株式会社 半导体器件和控制半导体器件的方法
CN108958209B (zh) * 2017-05-22 2023-06-06 瑞萨电子株式会社 半导体器件和控制半导体器件的方法
CN110161399A (zh) * 2018-02-12 2019-08-23 三星电子株式会社 半导体器件

Also Published As

Publication number Publication date
US20180003771A1 (en) 2018-01-04
US9797950B2 (en) 2017-10-24
US20160274185A1 (en) 2016-09-22
JP6491507B2 (ja) 2019-03-27
JP2016176843A (ja) 2016-10-06
US10317466B2 (en) 2019-06-11

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