CN105981167A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN105981167A
CN105981167A CN201580007474.1A CN201580007474A CN105981167A CN 105981167 A CN105981167 A CN 105981167A CN 201580007474 A CN201580007474 A CN 201580007474A CN 105981167 A CN105981167 A CN 105981167A
Authority
CN
China
Prior art keywords
leading section
terminal
semiconductor device
circuit board
grafting material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201580007474.1A
Other languages
English (en)
Other versions
CN105981167B (zh
Inventor
小松康佑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN105981167A publication Critical patent/CN105981167A/zh
Application granted granted Critical
Publication of CN105981167B publication Critical patent/CN105981167B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/29294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32106Disposition relative to the bonding area, e.g. bond pad the layer connector connecting one bonding area to at least two respective bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48105Connecting bonding areas at different heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15158Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15158Shape the die mounting substrate being other than a cuboid
    • H01L2924/15162Top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

半导体装置具备:层叠基板,具有电路板;半导体芯片,固定于电路板;端子,具有筒状的前端部、和非筒状的布线部,且前端部和布线部由一个导电部件构成;以及接合材料,对电路板和前端部进行电连接和机械连接。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
作为半导体装置之一的功率半导体模块具备:层叠基板、半导体芯片、壳体和端子。层叠基板例如通过依次层叠电路板、绝缘板和金属板而构成。此外,半导体芯片通过接合材料而电连接且机械连接于电路板的一个区域。此外,壳体容纳金属基板和半导体芯片,且壳体内填充有密封材料。端子的一端通过接合材料而电连接且机械连接于在半导体芯片的正面设置的电极和/或电路板,端子的另一端从壳体引出到外部。接合材料例如为焊锡。
功率半导体模块的端子大体上分为两类,其中一类为主端子。主端子的主要功能是经由半导体芯片等而流通主电流。另一类为控制端子,它也被称为感测端子。控制端子的主要功能是向半导体芯片输入控制信号,另外还引导温度检测用的信号。
主端子的与电路板接合的部分的截面积具有根据电流额定值所需的预定的面积。此外,基于确保可靠性的观点,主端子与电路板以能够充分接合的形状进行焊接。另一方面,控制端子只流通微小的电流,或仅被施加电压。因此,控制端子的与半导体芯片的正面电极和/或电路板接合的部分的面积,与主电流的电流额定值无关,而具有与产品的封装形状对应的预定的面积。与端子接合的半导体芯片的正面电极和/或电路板的区域具有比端子的前端大的面积。
专利文献1中图示有由导电板构成,并具有折弯成L字形的前端的端子。此外,专利文献2中记载有由线材引脚和插入线材引脚的筒状部构成的端子。
现有技术文献
专利文献
专利文献1:日本特开2004-6603号公报
专利文献2:日本特开2010-283107号公报
发明内容
技术问题
具有折弯成L字形的前端的端子与电路板接合时,端子的前端堆叠在涂布于电路板的焊锡膏上并被加热。由加热而熔融的焊锡由于表面张力而凝集在端子的前端附近。
然而,存在熔融的焊锡的一部分飞溅而附着到电路板的侧面的情况。这一情况有可能引发绝缘不良。此外,存在熔融的焊锡成为蔓延到电路板的端部的状态的情况。这一情况有可能在功率半导体模块的热循环试验或热冲击试验时,由于焊锡与电路板之间的线膨胀系数的差而产生热应力,导致电路板从绝缘板剥离。
作为上述的绝缘不良和剥离的应对方案而进行的有:将端子的接合位置远离电路板的端部,和将电路板的面积设置为充分大于端子的前端的截面积。可是,这些应对方案会限制电路板配置的自由度。
本发明为有利地解决上述问题的发明,其目的在于提供一种能够抑制电路板与绝缘板的剥离和绝缘不良,此外,能够提高电路板配置的自由度的半导体装置。
技术方案
本发明的一个形态的半导体装置,具备:层叠基板,具有电路板;半导体芯片,固定于上述电路板;端子,具有筒状的前端部、和非筒状的布线部,且上述前端部和上述布线部由一个导电部件构成;以及接合材料,对上述电路板和上述前端部进行电连接和机械连接。
此外,本发明的另一个形态的半导体装置,具备:层叠基板,具有电路板;半导体芯片,在正面具备电极,且背面被固定于上述电路板;端子,具有筒状的前端部、和非筒状的布线部,且上述前端部和上述布线部由一个导电部件构成;以及接合材料,对上述电极和上述前端部进行电连接和机械连接。
技术效果
根据本发明的半导体装置,能够抑制电路板与绝缘板的剥离和绝缘不良,此外,能够提高电路板配置的自由度。
附图说明
图1是本发明的实施方式一的半导体装置的示意性截面图。
图2是实施方式一的端子的说明图。
图3是实施方式一的端子的作用效果的截面图。
图4是实施方式二的端子的说明图。
图5是实施方式三的端子的说明图。
图6是实施方式四的端子的说明图。
图7是实施方式三和实施方式四的端子的作用效果的截面图。
图8是将参考例的端子用于与半导体芯片连接的情况的俯视图。
图9是将实施方式五的端子用于与半导体芯片连接的情况的俯视图。
符号说明
1:半导体装置
2:底板
3:层叠基板
3a:绝缘板
3b:金属板
3c、3c1、3c2:电路板
4:接合材料
5:半导体芯片
5e:电极
6:接合材料
6a:圆角(Fillet)
7、8、9:端子
10:键合线
11:框体
12:密封材料
13:盖
20:前端部
20a~20e:侧面
20g:缺口(Gap)
20s:狭缝(Slit)
21:布线部
具体实施方式
(实施方式一)
以下,参照附图对本发明的半导体装置的实施方式进行具体说明。
图1中以示意性截面图示出的本实施方式的半导体装置1为功率半导体模块的例子。半导体装置1具备:层叠基板3、半导体芯片5、端子7~9和接合材料6。进一步地,半导体装置1具备:底板2、框体11、密封材料12和盖13。
层叠基板3由绝缘板3a、设置在绝缘板3a的一侧的面的金属板3b、设置在绝缘板3a的另一侧的面的电路板3c构成。绝缘板3a和金属板3b具有大致四边形的平面形状。绝缘板3a例如由氮化铝、氮化硅或氧化铝等绝缘性陶瓷构成,金属板3b、电路板3c例如由铜构成。对于层叠基板3,可以使用将绝缘板3a与金属板3b、电路板3c这些基板直接接合而得的DCB(DirectCopper Bond:直接键合铜)基板等。金属板3b通过焊锡等接合材料4与底板2的主表面接合。
电路板3c在图示的例子中具有构成预定的电路的3c1、3c2。在电路板3c1通过导电性的接合材料6例如焊锡接合有半导体芯片5。导电性的接合材料可以为选自焊锡、金属膏及导电性粘结剂中的一种。
半导体芯片5在正面和背面分别设置有电极。并且,背面的电极通过焊锡等导电性的接合材料4而电连接且机械连接于电路板3c1。“电连接且机械连接”不限于目标物体彼此通过直接接合而连接的情况,还包括通过焊锡和/或金属烧结材料等导电性的接合材料来连接目标物体彼此的情况,在以下的说明中也是同样的。
半导体芯片5,具体说来,例如是肖特基势垒二极管、功率MOSFET、IGBT(绝缘栅双极型晶体管)等。半导体芯片5可以是硅半导体,也可以是SiC半导体。在半导体芯片5为碳化硅(SiC)功率MOSFET的情况下,与硅半导体芯片相比为高耐压,且能够以高频率进行开关,因此最适合作为本实施方式的半导体装置的半导体芯片5。不过,半导体芯片5不限于IGBT、功率MOSFET,也可以是能够进行开关动作的一个半导体元件或多个半导体元件的组合。
在本实施方式中,作为一例,对半导体芯片5为IGBT的情况进行说明。在此情况下,半导体芯片5的背面的电极为集电极,正面的电极为发射极和栅极。
在电路板3c1通过焊锡等导电性的接合材料6而电接合且机械接合有作为主端子的端子7。端子7与半导体芯片5的背面的集电极电连接。此外,在半导体芯片5的正面的发射极通过焊锡等导电性的接合材料6而电连接且机械连接有作为主端子的端子8。进一步地,在电路板3c2通过焊锡等导电性的接合材料6而电连接且机械连接有与半导体芯片5的栅极电连接的作为控制端子的端子9。电路板3c2与半导体芯片的栅极通过键合线10而电连接。即,在本实施方式中端子7为集电极端子,端子8为发射极端子,端子9为栅极端子。
散热用的金属制的底板2由导热性良好的金属,例如铜等构成,并具有大致四边形的平面形状。
在底板2的周边通过未图示的粘结剂而粘结有由树脂构成的框体11。此外,在框体11的上部固定有盖13。通过底板2、框体11、盖13构成半导体装置1的壳体。并且,在壳体内容纳有层叠基板3和半导体芯片5,并填充有提高绝缘性的密封材料12。
图2中示出端子7~9的主视图(图2(A))、侧视图(图2(B))和俯视图(图2(C))。此外,图2(D)为前端部形成前的端子7~9的展开图。
端子7~9由前端部20和布线部21构成。前端部20利用接合材料6与电路板3c和/或半导体芯片5的正面电极进行电连接和机械连接。此外,布线部21具有从连接于前端部20的位置起向半导体装置1的预定的位置进行电气布线的功能。并且,前端部20为筒状,布线部21为非筒状的形状(在本实施例中为板状)。前端部20具有:与布线部21一体地连续的侧面20a、与侧面20a垂直的侧面20b和20c。并且,在侧面20b和侧面20c之间配置有沿筒的轴向延伸的缺口20g。即,就端子7~9而言,前端部20和布线部21由一个导电部件构成。在本实施例中,如图2(D)的展开图可知,将一张导电板沿折弯线L1、L2进行折弯加工而配置侧面20a、20b、20c和缺口20g,形成筒状的前端部20。如图2(C)所示,前端部20具有由三个侧面构成的大致U字形的横截面形状。换言之,前端部20的垂直于筒的轴的截面具有一边开口的四边形,更具体地为长方形。
缺口20g沿前端部20的筒的轴向延伸。并且,设置在与侧面20a相向的位置,侧面20a为布线部21和前端部20的连结位置。
端子7~9的材料为铜板,并且根据需要而实施镀镍。作为端子7~9如果使用与在通常的功率半导体模块中使用的导电板相同的材料,具体地,与导线相同的材料,则容易获取材料。因此,可以以低价制造端子7~9。
利用图3来说明具有前端部20的端子7~9(端子9在这里为控制端子)的作用效果。在对端子9进行接合时,在将电路板3c2与端子9的前端之间空出0.5~1.0mm的程度的间隔c的状态下进行加热。熔融的接合材料6由于表面张力而凝集,并与端子9的前端接触。由于前端部20为筒状,所以熔融的接合材料6由于毛细作用而被向上吸入到筒状的前端部20的内部。并且,当将熔融的接合材料6冷却并固化时,在电路板3c2与端子9的前端之间形成圆角6a。由此,接合材料6在电路板3c2上所占的面积为由前端部20包围的部分和圆角6a的总和。该面积与使用具有折弯成L字形的前端的专利文献1所记载的端子的情况相比要小。因此,由于熔融的接合材料6不会蔓延到电路板3c2的端部,所以能够抑制电路板3c从绝缘板3a剥离。此外,由于能够抑制熔融的接合材料6的一部分飞溅而附着到电路板3c的端部的侧面,所以能够抑制绝缘不良。
此外,与专利文献2所记载的筒状部相比,由于前端部20采用简单的结构,所以能够降低部件的成本。进一步地,前端部20的折弯加工容易,并且与专利文献2所记载的预先焊接筒状部,进而插入线材引脚的工序相比,能够削减工序,从而能够降低制造成本。
此外,进一步地,在专利文献2所记载的技术中,如果在筒状部的内部加入过多的熔融的接合材料,则会阻碍线材引脚的插入,所以需要严格控制接合材料的量。另一方面,在本实施方式中即使在筒状的前端部20的内部加入过多的熔融的接合材料6也不会产生特别的阻碍,因此,不需要严格控制接合材料的量。因此,能够降低制造成本。应予说明,前端部20的高度优选为比被向上吸入前端部20内的接合材料6的高度要高,以使接合材料6即使过剩也不从前端部20溢出。
如果电路板3c与端子9的前端之间的间隔c设定为0.5~1.0mm的程度,则在端子9的前端附近的接合材料6能够形成形状良好的圆角6a,因此优选。
前端部20具有缺口20g,由此在加热时熔融的接合材料6可通过缺口20g在筒状的前端部20的内外移动。因此,与前端部20不具有缺口20g的情况相比,能够形成宽度和高度都大的圆角6a。因此,能够提高接合材料6的接合强度,并能够提高接合的可靠性。
此外,如图1所示,也可以将端子7~9的布线部21的与前端部20相反的一侧的端部直接引出到半导体装置1的壳体的外部。这是因为端子7~9通过筒状的前端部20被牢固地接合,所以即使从外部对端子7~9施加应力,接合部也不会剥离。通过将布线部21直接引出到壳体的外部,从而不需要外部引出用的专用端子,所以能够降低制造成本。
此外,在本实施方式中布线部21为板状,但只要能够以非筒状的形状容易地在预定的位置布线,无论何种形状都可以。在本实施方式中,布线部21为非筒状的形状的理由是因为筒状难以折弯,因此如果布线部为筒状则难以布线到预定的位置。因此,对于布线部21的形状,适用板状、棒状、线状等容易进行折弯加工的形状。
应予说明,在本实施方式中,使用框体11、密封材料12和盖13来构成半导体装置1。另一方面,也可以通过使用热固化性树脂的嵌件成型来密封半导体芯片等,从而构成半导体装置。由此,能够实现半导体装置的小型化。
此外,在本实施方式中,作为接合材料6而使用焊锡,但只要是能够以液态在前端部20形成圆角6a的导电性的接合材料,无论使用何种接合材料都可以。作为接合材料6也可以使用例如金属膏、导电性粘结剂。
(实施方式二)
图4中示出实施方式二的端子7~9的俯视图。这是与实施方式一的图2(C)对应的图。
实施方式二的半导体装置的端子7~9将其侧面20b、20c的折弯加工的加工程度增大而减小了两侧端之间的缺口20g。由此,前端部20的垂直于筒的轴的截面形状具有大致梯形的形状。除此之外具有与利用图2、图3说明的实施方式一相同的构成。本实施方式的端子7~9具有与实施方式一的端子7~9同样的作用效果。此外,进一步地,与实施方式一相比能够缩小接合面积,因此,在将端子接合于狭窄区域的情况下是有效的。
(实施方式三)
图5(A)~图5(C)中示出实施方式三的端子7~9。这是与实施方式一的图2(A)、图2(C)和图2(D)对应的图。
实施方式三的半导体装置的端子7~9具有:筒状且横截面形状为大致长方形的前端部20、和板状的布线部21。前端部20具有:与布线部21一体地连续的侧面20a、与侧面20a垂直的侧面20b和侧面20c、与侧面20b、侧面20c垂直且宽度比它们窄的侧面20d和侧面20e。并且,在侧面20d与侧面20e之间,配置有沿筒的轴向延伸的缺口20g。如图5(C)的展开图可知,将一张导电板沿折弯线L1~L4进行折弯加工来配置侧面20a~20e和缺口20g,从而形成筒状的前端部20。
实施方式三的端子7~9除了前端部20的横截面形状不同之外,具有与实施方式一、实施方式二的端子7~9相同的构成。并且,本实施方式的端子7~9具有与实施方式一、实施方式二的端子7~9同样的作用效果。进一步地,在本实施方式中,由于与实施方式一、实施方式二相比,前端部20的侧面的面积扩大,所以容易引起熔融的接合材料6的毛细作用。
端子7~9并不限于在实施方式一~三中所说明的具有长方形或梯形的横截面形状的前端部20,可以进行各种变形。例如,可以为多边形或圆形的横截面形状。前端部20的内径为可通过毛细作用而将熔融的接合材料6向上吸入到前端部20内部的内径。
(实施方式四)
图6(A)~图6(C)中示出实施方式四的端子7~9。这是与实施方式一的图2(A)、图2(B)和图2(D)对应的图。
实施方式四的半导体装置的端子7~9与实施方式三的端子7~9同样,具有:筒状且横截面形状为大致长方形的前端部20、和板状的布线部21。进一步地,在本实施方式中,如图6(B)的侧视图和图6(C)的展开图所示,在侧面20a、侧面20b和侧面20c,在利用接合材料6连接的一侧配置有分别沿筒的轴向延伸的多个,在图示例中为三个狭缝20s。
即,实施方式四的端子7~9除了配置有狭缝20s之外,具有与实施方式三的端子7~9相同的构成。因此,实施方式四的端子7~9具有与实施方式三的端子7~9同样的效果。进一步地,实施方式四的端子7~9由于在前端部20配置有狭缝20s,所以在加热时熔融的接合材料6可以通过狭缝20s在筒状的前端部20的内外移动。因此,与前端部不具有狭缝20s的情况相比,可形成宽度和高度都大的圆角6a。
将不具有狭缝20s的实施方式三的截面图示于图7(A),将具有狭缝20s的实施方式四的截面图示于图7(B)。根据图7(A)和图7(B)的对比,实施方式四的接合材料6的圆角6a比实施方式三的接合材料6的圆角6a大。因此,在实施方式四中,能够进一步提高端子7~9的接合强度,因此在要求接合强度的情况下是有效的。此外,在实施方式三中,能够缩小接合材料6的宽度,因此在电极和/或电路板无法取得较大面积的情况等想要缩小接合材料6的设置面积的情况下是有效的。
此外,在本实施方式中,在相向的侧面20b和侧面20c分别配置有狭缝20s。这样通过在彼此相向的位置上配置两个狭缝20s,能够如图7(B)所示那样使接合材料6的圆角6a为线对称形状。因此,能够在前端部20中使相向的侧面彼此的接合力为均等,有效提高可靠性。应予说明,如前所述,缺口20g和狭缝20s都具有相同的功能。因此,如本实施方式所示,在彼此相向的位置上配置缺口20g和狭缝20s也是有效的。
具有狭缝20s的端子7~9的前端部分的横截面形状不限于图6所示的长方形,也可以应用图3所示的梯形、其他多边形和/或圆形的横截面形状。
(参考例)
图8是将专利文献1所记载的L字形的端子108用于与半导体芯片105连接的情况的俯视图。
L字形的端子108通过导电性的接合材料(未图示)而电连接且机械连接于半导体芯片105的正面的电极105e。此外,将配置于半导体芯片5的正面电极设置为长方形。
对于半导体芯片105来说,存在将利用接合材料进行的芯片背面与电路板的接合、和利用接合材料进行的正面与端子108的接合通过同一加热工序来实施的情况。在此情况下,半导体芯片的背面侧的接合材料也熔融,因此在端子108的前端形状与电极105e相比相对小的情况下,半导体芯片105有可能当场发生旋转。
(实施方式五)
图9是将实施方式五的端子8用于与半导体芯片5连接的情况的俯视图。
在实施方式五中,将端子8的侧面20a、20b、20c中的一边设置为比在半导体芯片5的正面存在的长方形的电极5e的一边5e1(短边)或5e2(长边)长。换言之,将端子8的成为长边的侧面20b(20c)设置为比电极5e的短边5e1长。由此,能够防止半导体芯片5当场发生旋转。即,根据本实施方式,能够实现半导体芯片5的自对准(self alignment)。
以上,利用附图和实施方式对本发明的半导体装置进行了具体的说明,但本发明的半导体装置并不限于实施方式和附图的记载,在不脱离本发明的主旨的范围内,可进行各种变形。例如,前端部20不限于相对于电路板3c或半导体芯片5的表面垂直地设置的情况,也可以具有预定的角度。此外,也可以在前端部20上预先附着有焊锡膏。
权利要求书(按照条约第19条的修改)
1.一种半导体装置,其特征在于,具备:
层叠基板,具有电路板;
半导体芯片,固定于所述电路板;
端子,具有至少两端开放的中空形状的前端部和布线部,且所述前端部和所述布线部由一个导电部件构成;以及
接合材料,对所述电路板和所述前端部进行电连接和机械连接,
所述前端部的一个开放端与所述电路板相向,
所述前端部的另一个开放端与所述布线部连接。
2.一种半导体装置,其特征在于,具备:
层叠基板,具有电路板;
半导体芯片,在正面具备电极,且背面被固定于所述电路板;
端子,具有至少两端开放的中空形状的前端部和布线部,且所述前端部和所述布线部由一个导电部件构成;以及
接合材料,对所述电极和所述前端部进行电连接和机械连接,
所述前端部的一个开放端与所述电路板相向,
所述前端部的另一个开放端与所述布线部连接。
3.根据权利要求1或2所述的半导体装置,其特征在于,
所述前端部具有沿所述中空的轴向延伸的缺口。
4.根据权利要求3所述的半导体装置,其特征在于,
所述缺口设置在与所述前端部和所述布线部的连结位置相向的位置。
5.根据权利要求3所述的半导体装置,其特征在于,
所述前端部的垂直于所述中空的轴的截面为一边开口的四边形。
6.根据权利要求1或2所述的半导体装置,其特征在于,
所述前端部在利用所述接合材料连接的一侧具有一个以上的狭缝。
7.根据权利要求6所述的半导体装置,其特征在于,
所述狭缝具备多个,所述狭缝中的两个配置于彼此相向的位置。
8.根据权利要求2所述的半导体装置,其特征在于,
所述前端部的垂直于所述中空的轴的截面和所述电极为四边形,
所述前端部的截面的一边比所述电极的一边长。
9.根据权利要求1或2所述的半导体装置,其特征在于,
所述布线部为板状。
10.根据权利要求1或2所述的半导体装置,其特征在于,
所述布线部被引出到容纳所述层叠基板和所述半导体芯片的壳体的外部。
11.根据权利要求1或2所述的半导体装置,其特征在于,
所述前端部的横截面形状为U字形。
12.根据权利要求1或2所述的半导体装置,其特征在于,
所述前端部的横截面形状为长方形或圆形。

Claims (10)

1.一种半导体装置,其特征在于,具备:
层叠基板,具有电路板;
半导体芯片,固定于所述电路板;
端子,具有筒状的前端部、和非筒状的布线部,且所述前端部和所述布线部由一个导电部件构成;以及
接合材料,对所述电路板和所述前端部进行电连接和机械连接。
2.一种半导体装置,其特征在于,具备:
层叠基板,具有电路板;
半导体芯片,在正面具备电极,且背面被固定于所述电路板;
端子,具有筒状的前端部、和非筒状的布线部,且所述前端部和所述布线部由一个导电部件构成;以及
接合材料,对所述电极和所述前端部进行电连接和机械连接。
3.根据权利要求1或2所述的半导体装置,其特征在于,
所述前端部具有沿筒的轴向延伸的缺口。
4.根据权利要求3所述的半导体装置,其特征在于,
所述缺口设置在与所述前端部和所述布线部的连结位置相向的位置。
5.根据权利要求3所述的半导体装置,其特征在于,
所述前端部的垂直于筒的轴的截面为一边开口的四边形。
6.根据权利要求1所述的半导体装置,其特征在于,
所述前端部在利用所述接合材料连接的一侧具有一个以上的狭缝。
7.根据权利要求6所述的半导体装置,其特征在于,
所述狭缝具备多个,所述狭缝中的两个配置于彼此相向的位置。
8.根据权利要求2所述的半导体装置,其特征在于,
所述前端部的垂直于所述筒的轴的截面和所述电极为四边形,
所述前端部的截面的一边比所述电极的一边长。
9.根据权利要求1或2所述的半导体装置,其特征在于,
所述布线部为板状。
10.根据权利要求1或2所述的半导体装置,其特征在于,
所述布线部被引出到容纳所述层叠基板和所述半导体芯片的壳体的外部。
CN201580007474.1A 2014-08-12 2015-06-23 半导体装置 Active CN105981167B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014-164427 2014-08-12
JP2014164427 2014-08-12
PCT/JP2015/068065 WO2016024445A1 (ja) 2014-08-12 2015-06-23 半導体装置

Publications (2)

Publication Number Publication Date
CN105981167A true CN105981167A (zh) 2016-09-28
CN105981167B CN105981167B (zh) 2019-05-28

Family

ID=55304075

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580007474.1A Active CN105981167B (zh) 2014-08-12 2015-06-23 半导体装置

Country Status (4)

Country Link
US (1) US10170394B2 (zh)
JP (1) JP6308300B2 (zh)
CN (1) CN105981167B (zh)
WO (1) WO2016024445A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110137092A (zh) * 2019-04-29 2019-08-16 中国电子科技集团公司第十三研究所 功率半导体器件制作方法及功率半导体器件
CN111630644A (zh) * 2018-03-02 2020-09-04 新电元工业株式会社 半导体装置及其制造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6717103B2 (ja) * 2016-08-03 2020-07-01 株式会社豊田自動織機 半導体モジュール
JP7172325B2 (ja) * 2018-09-14 2022-11-16 富士電機株式会社 配線基板、半導体装置、配線基板の製造方法
JP6997690B2 (ja) * 2018-09-26 2022-01-18 日立Astemo株式会社 パワーモジュール
BE1028071B1 (de) * 2020-02-19 2021-09-13 Phoenix Contact Gmbh & Co Elektrisches Kontaktelement
JP7435415B2 (ja) * 2020-11-16 2024-02-21 三菱電機株式会社 半導体装置及びその製造方法
JP2022125386A (ja) * 2021-02-17 2022-08-29 富士電機株式会社 物理量センサ装置および物理量センサ装置の製造方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4056302A (en) * 1976-06-04 1977-11-01 International Business Machines Corporation Electrical connection structure and method
JPS63254689A (ja) * 1987-04-10 1988-10-21 株式会社 ニチフ端子工業 電線端子の製造方法
JPH06291230A (ja) * 1993-04-02 1994-10-18 Nippon Inter Electronics Corp 複合半導体装置の製造方法
JPH1041460A (ja) * 1996-05-20 1998-02-13 Fuji Electric Co Ltd 半導体装置
EP0887884A2 (en) * 1997-05-28 1998-12-30 Harness System Technologies Research, Ltd. Bus bar structure
US6365965B1 (en) * 1998-11-26 2002-04-02 Samsung Electronics Co., Ltd. Power semiconductor module with terminals having holes for better adhesion
US20060281347A1 (en) * 2005-06-08 2006-12-14 Delta Electronics, Inc. Fixing auxiliary device
US20100127383A1 (en) * 2008-11-25 2010-05-27 Mitsubishi Electric Corporation Power semiconductor module
JP2012000995A (ja) * 2011-08-01 2012-01-05 Mitsuboshi Diamond Industrial Co Ltd ピン
US20140174823A1 (en) * 2012-12-21 2014-06-26 Chief Land Electronic Co., Ltd. Method for sleeve retaining a solder material onto a terminal unit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129797A (ja) * 1995-10-27 1997-05-16 Hitachi Ltd パワー半導体装置
US6623283B1 (en) * 2000-03-08 2003-09-23 Autosplice, Inc. Connector with base having channels to facilitate surface mount solder attachment
JP2004006603A (ja) 2002-03-26 2004-01-08 Fuji Electric Holdings Co Ltd 半導体パワーデバイス
JP4274528B2 (ja) * 2003-04-28 2009-06-10 協伸工業株式会社 タブ端子
DE102005016650B4 (de) * 2005-04-12 2009-11-19 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit stumpf gelöteten Anschluss- und Verbindungselementen
DE102008005547B4 (de) * 2008-01-23 2013-08-29 Infineon Technologies Ag Leistungshalbleitermodul und Schaltungsanordnung mit einem Leistungshalbleitermodul
US8378231B2 (en) * 2008-07-31 2013-02-19 Ibiden Co., Ltd. Semiconductor device and method for manufacturing the same
JP5268786B2 (ja) * 2009-06-04 2013-08-21 三菱電機株式会社 半導体モジュール
JP5069758B2 (ja) * 2010-01-04 2012-11-07 三菱電機株式会社 半導体装置
EP2650972B1 (en) 2010-12-08 2016-03-16 Furukawa Electric Co., Ltd. Crimp terminal, connection structure, and production method for same
TWI436529B (zh) * 2011-07-14 2014-05-01 Nan Ya Printed Circuit Board 電子元件
JP6415111B2 (ja) * 2013-06-20 2018-10-31 キヤノン株式会社 プリント回路板、半導体装置の接合構造及びプリント回路板の製造方法
DE102014101238A1 (de) * 2014-01-31 2015-08-06 Hs Elektronik Systeme Gmbh In Leiterplatten eingebettetes Leistungsmodul

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4056302A (en) * 1976-06-04 1977-11-01 International Business Machines Corporation Electrical connection structure and method
JPS63254689A (ja) * 1987-04-10 1988-10-21 株式会社 ニチフ端子工業 電線端子の製造方法
JPH06291230A (ja) * 1993-04-02 1994-10-18 Nippon Inter Electronics Corp 複合半導体装置の製造方法
JPH1041460A (ja) * 1996-05-20 1998-02-13 Fuji Electric Co Ltd 半導体装置
EP0887884A2 (en) * 1997-05-28 1998-12-30 Harness System Technologies Research, Ltd. Bus bar structure
US6365965B1 (en) * 1998-11-26 2002-04-02 Samsung Electronics Co., Ltd. Power semiconductor module with terminals having holes for better adhesion
US20060281347A1 (en) * 2005-06-08 2006-12-14 Delta Electronics, Inc. Fixing auxiliary device
US20100127383A1 (en) * 2008-11-25 2010-05-27 Mitsubishi Electric Corporation Power semiconductor module
JP2012000995A (ja) * 2011-08-01 2012-01-05 Mitsuboshi Diamond Industrial Co Ltd ピン
US20140174823A1 (en) * 2012-12-21 2014-06-26 Chief Land Electronic Co., Ltd. Method for sleeve retaining a solder material onto a terminal unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111630644A (zh) * 2018-03-02 2020-09-04 新电元工业株式会社 半导体装置及其制造方法
CN111630644B (zh) * 2018-03-02 2023-07-14 新电元工业株式会社 半导体装置及其制造方法
CN110137092A (zh) * 2019-04-29 2019-08-16 中国电子科技集团公司第十三研究所 功率半导体器件制作方法及功率半导体器件

Also Published As

Publication number Publication date
JPWO2016024445A1 (ja) 2017-04-27
JP6308300B2 (ja) 2018-04-11
US20160343642A1 (en) 2016-11-24
CN105981167B (zh) 2019-05-28
US10170394B2 (en) 2019-01-01
WO2016024445A1 (ja) 2016-02-18

Similar Documents

Publication Publication Date Title
CN105981167A (zh) 半导体装置
US10727163B2 (en) Semiconductor device
CN104170085B (zh) 半导体装置
US7884455B2 (en) Semiconductor device
CN105765716B (zh) 功率半导体模块和复合模块
US8563364B2 (en) Method for producing a power semiconductor arrangement
WO2015111691A1 (ja) 電極端子、電力用半導体装置、および電力用半導体装置の製造方法
US10186354B2 (en) Mounting structure for mounting shunt resistor and method of manufacturing mounting structure for mounting shunt resistor
KR20170086828A (ko) 메탈범프를 이용한 클립 본딩 반도체 칩 패키지
CN104810333A (zh) 功率半导体模块
CN108780792A (zh) 功率模块及其制造方法以及功率电子器件及其制造方法
US9666557B2 (en) Small footprint semiconductor package
KR20170126469A (ko) 칩 배열 및 접촉 연결을 형성하는 방법
US20150262917A1 (en) Semiconductor device and method of manufacturing the same
US9076782B2 (en) Semiconductor device and method of manufacturing same
US11315850B2 (en) Semiconductor device
CN105814682A (zh) 半导体装置
JP5233853B2 (ja) 半導体装置
JP2017034152A (ja) 電力用半導体装置
JP5623367B2 (ja) 半導体装置および半導体装置モジュール
CN112106194A (zh) 用于半导体功率模块的排热组件
JP2018517302A (ja) クリップシフトを低減させつつ半導体ダイを取り付けるための導電性クリップを具備するリードフレーム
CN108292642B (zh) 电力用半导体装置
CN107078126B (zh) 半导体模块以及半导体模块用的导电构件
WO2018151010A1 (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant