CN105981166B - 包括具有穿过封装层的侧势垒层的通孔的集成器件 - Google Patents

包括具有穿过封装层的侧势垒层的通孔的集成器件 Download PDF

Info

Publication number
CN105981166B
CN105981166B CN201580008236.2A CN201580008236A CN105981166B CN 105981166 B CN105981166 B CN 105981166B CN 201580008236 A CN201580008236 A CN 201580008236A CN 105981166 B CN105981166 B CN 105981166B
Authority
CN
China
Prior art keywords
layer
implementations
hole
substrate
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201580008236.2A
Other languages
English (en)
Chinese (zh)
Other versions
CN105981166A (zh
Inventor
J·S·李
H·B·蔚
D·W·金
S·顾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105981166A publication Critical patent/CN105981166A/zh
Application granted granted Critical
Publication of CN105981166B publication Critical patent/CN105981166B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Micromachines (AREA)
CN201580008236.2A 2014-02-13 2015-02-11 包括具有穿过封装层的侧势垒层的通孔的集成器件 Expired - Fee Related CN105981166B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461939523P 2014-02-13 2014-02-13
US61/939,523 2014-02-13
US14/274,517 2014-05-09
US14/274,517 US9466554B2 (en) 2014-02-13 2014-05-09 Integrated device comprising via with side barrier layer traversing encapsulation layer
PCT/US2015/015421 WO2015123301A1 (en) 2014-02-13 2015-02-11 Integrated device comprising via with side barrier layer traversing encapsulation layer

Publications (2)

Publication Number Publication Date
CN105981166A CN105981166A (zh) 2016-09-28
CN105981166B true CN105981166B (zh) 2019-04-16

Family

ID=53775574

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580008236.2A Expired - Fee Related CN105981166B (zh) 2014-02-13 2015-02-11 包括具有穿过封装层的侧势垒层的通孔的集成器件

Country Status (5)

Country Link
US (1) US9466554B2 (https=)
EP (1) EP3105787B1 (https=)
JP (1) JP2017511971A (https=)
CN (1) CN105981166B (https=)
WO (1) WO2015123301A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343417B2 (en) 2013-09-18 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Hollow metal pillar packaging scheme
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9355963B2 (en) * 2014-09-26 2016-05-31 Qualcomm Incorporated Semiconductor package interconnections and method of making the same
TWI559829B (zh) 2014-10-22 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
US10651160B2 (en) * 2017-03-20 2020-05-12 Qualcomm Incorporated Low profile integrated package
CN114093770B (zh) * 2021-10-27 2026-04-14 珠海越亚半导体股份有限公司 埋嵌封装结构及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1658385A (zh) * 2004-02-17 2005-08-24 三洋电机株式会社 半导体装置及其制造方法
CN1898150A (zh) * 2003-12-24 2007-01-17 凯文迪什动力学有限公司 容纳装置以及相应装置的方法
WO2010041630A1 (ja) * 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
CN101740490A (zh) * 2008-11-26 2010-06-16 佳能株式会社 半导体装置制造方法和半导体装置
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构
JP2012129262A (ja) * 2010-12-13 2012-07-05 Sumitomo Bakelite Co Ltd 半導体素子封止体の製造方法および半導体パッケージの製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586682B2 (en) 2000-02-23 2003-07-01 Kulicke & Soffa Holdings, Inc. Printed wiring board with controlled line impedance
US8239162B2 (en) * 2006-04-13 2012-08-07 Tanenhaus & Associates, Inc. Miniaturized inertial measurement unit and associated methods
US8021981B2 (en) 2006-08-30 2011-09-20 Micron Technology, Inc. Redistribution layers for microfeature workpieces, and associated systems and methods
DE102007020266B3 (de) * 2007-04-30 2008-11-13 Advanced Micro Devices, Inc., Sunnyvale Halbleiterstruktur mit einem elektrisch leitfähigen Strukturelement und Verfahren zu ihrer Herstellung
US7799602B2 (en) 2008-12-10 2010-09-21 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure
KR20100075204A (ko) * 2008-12-24 2010-07-02 삼성전자주식회사 스터드 범프를 이용한 적층형 반도체 패키지, 반도체 패키지 모듈, 및 그 제조방법
JP2010157690A (ja) 2008-12-29 2010-07-15 Ibiden Co Ltd 電子部品実装用基板及び電子部品実装用基板の製造方法
JP5423572B2 (ja) * 2010-05-07 2014-02-19 セイコーエプソン株式会社 配線基板、圧電発振器、ジャイロセンサー、配線基板の製造方法
US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8766422B2 (en) 2010-12-30 2014-07-01 Stmicroelectronics Pte Ltd. Through hole via filling using electroless plating
US8476770B2 (en) * 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
US9040346B2 (en) 2012-05-03 2015-05-26 Infineon Technologies Ag Semiconductor package and methods of formation thereof
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1898150A (zh) * 2003-12-24 2007-01-17 凯文迪什动力学有限公司 容纳装置以及相应装置的方法
CN1658385A (zh) * 2004-02-17 2005-08-24 三洋电机株式会社 半导体装置及其制造方法
WO2010041630A1 (ja) * 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
CN101740490A (zh) * 2008-11-26 2010-06-16 佳能株式会社 半导体装置制造方法和半导体装置
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构
JP2012129262A (ja) * 2010-12-13 2012-07-05 Sumitomo Bakelite Co Ltd 半導体素子封止体の製造方法および半導体パッケージの製造方法

Also Published As

Publication number Publication date
EP3105787A1 (en) 2016-12-21
JP2017511971A (ja) 2017-04-27
EP3105787B1 (en) 2021-08-25
US20150228556A1 (en) 2015-08-13
CN105981166A (zh) 2016-09-28
US9466554B2 (en) 2016-10-11
WO2015123301A1 (en) 2015-08-20

Similar Documents

Publication Publication Date Title
US11626388B2 (en) Interconnect structure with redundant electrical connectors and associated systems and methods
USRE50796E1 (en) Semiconductor package having spacer layer
CN106463496B (zh) 包括无机层中的高密度互连和有机层中的重分布层的集成器件
US20200140267A1 (en) Seal for microelectronic assembly
JP6309643B2 (ja) 再分配層上に積層ダイを備える集積デバイス
US9613931B2 (en) Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9818720B2 (en) Structure and formation method for chip package
US9472483B2 (en) Integrated circuit cooling apparatus
CN105981166B (zh) 包括具有穿过封装层的侧势垒层的通孔的集成器件
US10381336B2 (en) Proximity coupling interconnect packaging systems and methods
US9368566B2 (en) Package on package (PoP) integrated device comprising a capacitor in a substrate
CN108364926A (zh) 具有分层互连结构的桥互连
JP2016533651A (ja) ＷＬＣＳＰコンポーネントをｅ−ＷＬＢ及びｅ−ＰＬＢ内に埋設する方法
JP2017507495A (ja) 高密度インターコネクトおよび再分配層を備える集積デバイス
CN203085525U (zh) 可用于堆叠的集成电路
JP2017515314A (ja) ＰｏＰパッケージのための基板ブロック
CN109671680A (zh) 具有不同高度的管芯结构的芯片封装件及其形成方法
CN107871732A (zh) 封装结构
CN106233458B (zh) 包括作为封装层中的通孔的导线的集成器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20190416

Termination date: 20220211