CN105529369B - 一种半导体元胞结构和功率半导体器件 - Google Patents

一种半导体元胞结构和功率半导体器件 Download PDF

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CN105529369B
CN105529369B CN201610131447.1A CN201610131447A CN105529369B CN 105529369 B CN105529369 B CN 105529369B CN 201610131447 A CN201610131447 A CN 201610131447A CN 105529369 B CN105529369 B CN 105529369B
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structure cell
semiconductor
deep trouth
semi
layer
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CN105529369A (zh
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谭开洲
胡刚毅
唐昭焕
王健安
杨永晖
钟怡
曹阳
刘勇
朱坤峰
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CETC 24 Research Institute
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Priority to PCT/CN2016/078270 priority patent/WO2017152443A1/zh
Priority to US16/068,098 priority patent/US10483358B2/en
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Abstract

本发明提供一种半导体元胞结构和功率半导体器件，其中，该半导体元胞结构包括有高掺杂半导体材料区，外延层，介质绝缘层，半绝缘材料，有源器件区，在所述外延层上还刻蚀有一深槽，所述深槽垂直进入到高掺杂半导体材料区里，于所述深槽内的侧壁上形成有介质绝缘层，且于所述深槽内填有半绝缘材料，半绝缘层顶部电极，在实际应用中可以将上述元胞以结构应用到功率半导体器件中，本发明大大降低了工艺实施难度，放宽了电荷平衡严酷的要求，容忍的电荷失配百分比大致放宽了10倍，同时也提高了器件元胞正常工作的长期可靠性，同时该技术方案结构也相对简单，相同可实施工艺条件下，保持了已有技术方案的主要性能。

Description

一种半导体元胞结构和功率半导体器件
技术领域
本发明涉及半导体器件和集成电路技术领域，特别是涉及一种高压低漂移区导通电阻的半导体元胞结构。
背景技术
目前半导体器件，尤其是高压硅功率器件，其承受耐压的漂移区击穿电压和导通电阻的优化设计是互相影响和相互矛盾的，获得高击穿电压一般就很难获得低的导通电阻，当然这不包括承受耐压的漂移区在器件导通时存在少子或非平衡双载流子调制的情况，如IGBT(英文全称：Insulated Gate Bipolar Transistor，翻译为：绝缘栅双极型晶体管)、PIN(P-I-N二极管)和GTO(英文全称：Gate Turn-Off Thyristor，翻译为：门控晶闸管)等器件。一般在100V以上的高压半导体硅器件中，很大一部分导通电阻都由该器件高压漂移区占据，这种情况随着工作电压的增加也越来越严重，这就是非调制型功率器件最著名的击穿电压2.5次方与漂移区导通电阻成正比的硅理论限制。
为了降低高压情况下非调制型功率器件漂移区导通电阻，近十几年来，业界针对传统的器件元胞结构提出了一些在保持击穿电压不变条件下降低导通电阻的方法和器件元胞结构，最著名的是基于RESURF二维电场原理和电荷平衡原则改进的超结(SuperJunction)结构的器件。其中，将该结构实现商业化的是英飞凌公司的名为CoolMOSTM的VDMOS功率器件，这种器件通过多于3次的外延和相应次数的定位杂质注入形成近似平行电流流向的PN结，并严格要求这个PN结垂直电流方向上杂质总量相等和达到空间耗尽电荷平衡，如此才能充分地承受最高电压，同时还能降低电流流过漂移区所产生的压降，也才能较好地突破普通一维平行平面PN结漂移区导通电阻与耐压的2.5次方的理论限制，不过这种工艺实现方式的难度和成本都比较大。
此外，现有技术中还有众多基于超结理论的新的实现方法和等效结构技术方案，在这些技术中能够工业实现的方案主要是以深槽为特点的结构与方法，其中尤其以深槽后的倾斜注入和外延填充比较接近超结理论，同时又相对容易实施一点。
总的来说，所有的现有技术的核心都基于超结的二维理论，同时也符合RESURF原理，核心的要求是若要使得一块二维半导体某个方向上承受高于平行平面结电压，同时漂移区导通电阻还能降低，则需在平行电流方向的这块半导体侧面形成一个PN结，并且要求在器件承受高压时这个PN结两侧全耗尽且能够刚好达到电荷平衡，同时杂质浓度或者空间耗尽层电荷满足RESURF条件。极少数情况下可以使用氧化层等绝缘体中固定均匀电荷来替代不参与导电的前述PN结一侧空间耗尽层电荷。
以图1为例，来综合说明现有技术的特点及实现面临的问题或不足之处，图1为一个现有技术高压低导通元胞结构高度概括的示意图，如图所示，图中区域1为器件关断承受高压的漂移区，同时也是器件导通时的电流通道；区域6为器件有源区，可以是VDMOS的栅和沟道区，也可以简单的只是肖特基或高压PN结二极管结面区等器件主功能区；区域7为器件高压高掺杂区，可以是VMDOS的漏区，或者是作为肖特基、PN结二极管高掺杂、低电阻的高压电极区。
可以看出，图1中的有源区(即区域6)、漂移区(即区域1)和高压电极区(及区域7)构成此类高压功率器件的基本功能要素，它们正是基于普通一维平行平面PN结高压器件的可独立工作的基本核心结构，而漂移区1正是这类器件中高压与低导通电阻矛盾的焦点，因为此漂移区在反向时承受高压，而正向导通时成为电流的必然通路。
为了进一步提高器件性能，即更高电压同时更低导通电阻的性能，利用RESURF原理以及超结电荷平衡二维效应机理，现有的那些技术基本都采用了在图1增加电流侧边与漂移区1相反杂质类型的区域2，并且区域2与器件漂移区1形成所谓超结的基本方案，这种解决方案是基于超结理论，突破平行平面PN结导通电阻与耐压的2.5次方的理论限制的第一代高压功率半导体器件，CoolMOSTM是这种结构的典型，并且已经商业实现的典型代表。
另外，少数现有技术方案还提出绝缘介质中电荷来等效和替代区域2，如图1中绝缘介质中电荷3。除了图1中区域1、区域2、区域3外，有些现有技术器件元胞结构还有一些次要的附加结构，如图1中的区域4和区域5，它们常常由多晶等半绝缘层和氧化层，氮化硅等绝缘层单独或者组合形成，多数情况下区域4是通过以深槽的工艺技术为特征来形成的，区域5一般是深槽4底部的一些结构的变形，一般情况下多数只有区域4，没有或不需要区域5。
不过，上述所涉及的现有技术方案在器件结构的工艺实现上存在以下一些困难或不足：
1)对于不存在区域4和区域5的器件元胞结构技术方案，区域1和区域2之间电荷平衡很难控制，一般地，根据RESURF原理，硅在100V～10000V电压范围里，区域1和区域2之间电荷平衡要求的电荷数面密度在1×1012cm-2～2×1012cm-2范围内，电压越高要求越严格，其10％的变化仅仅为1×1011cm-2～2×1011cm-2，这样的电荷控制，本行业内做过半导体的技术员都明白其控制难度，而就这样的变化量，对于800V左右的超结器件，将导致150V左右的变化。因此，实际商业化的器件一般都必须牺牲一点导通性能来权衡击穿与导通特性的矛盾，考虑到版图CD在工艺过程中的变化的影响也增加了超结器件的工艺实现难度。
2)对于存在区域4和区域5的器件元胞结构方案，与不存在区域4和区域5情况类似的，仍然存在区域1和区域2之间电荷平衡很难控制的问题，并且当区域4和(或)区域5存在绝缘介质时，一般不可避免还将引入绝缘介质层界面电荷或者绝缘介质内固定电荷，典型的如氧化层中固定氧化物电荷。对于较薄的氧化层固定电荷相对较少，对于20nm及以上的热氧化层其中的氧化物电荷一般在3×1010cm-2～2×1011cm-2范围，当然工艺控制水平较好时，这种电荷是可控和重复性较好的。即便是这样，对于高压功率器件，其工作环境一般是比较恶劣的，难免遇到尖峰电压干扰，这容易引起氧化层电荷注入或者退化，使得超结失去电荷平衡并影响高压器件工作的稳定性。
3)对于极少数使用绝缘层中电荷替代图1中区域2与有源功能区域1形成超结的情况，一个方面仍然存在前述通常绝缘层特有的不确定电荷影响，另一方面，目前在绝缘层上使用的绝缘层电荷一般是使用金属铯(Cesium)，属于碱金属族，与半导体硅工艺兼容性很差。
4)另外，现有技术中以深槽为工艺特征相对比较容易实现的工艺方案，目前有两种方法，即大倾斜角离子注入和直接外延方法。
其中，大倾斜角可以利用离子注入较好的剂量精确性，但是倾斜角度的精度以及等效杂质面密度1×1010cm-2～1×1011cm-2的精度也相当具有挑战性，并且如何满足现代平面集成工艺要求而封闭深槽，又不引起超结结构系统的电荷波动也是工艺实现的一个难题。若采用介质层封闭，介质绝缘层电荷的控制是个难点，且深槽底部多余的注入杂质电荷也需要小心处理，若采用多晶或单晶半导体外延则需要很好控制空间耗尽层或者单晶缺陷，否则将引起比较严重的反向漏电。
另外，直接外延的方法，一方面需要精确控制掺杂剂量，绝对控制精度在1～2×1011cm-2杂质面密度以内，另一方面在深槽中外延生长单晶如何完美封闭掉深槽而不形成缺陷也是一个难题，否则同样引起严重的反向漏电。
综上所述，如何提供一种兼具耐压和低导通电阻的高压硅功率器件并且能够在制造工艺中更加容易实现，这就成了本领域技术人员所亟待解决的问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种半导体元胞结构和功率半导体器件，用于解决现有技术在对功率半导体器件承受耐压的漂移区击穿电压和导通电阻进行优化时所存在的不足。
为实现上述目的或者其它相关的技术目的，本发明提供以下技术方案：
一种半导体元胞结构，至少包括：高掺杂半导体材料区；形成于所述高掺杂半导体材料区上的外延层；形成于所述外延层上的有源器件区；其中，在所述外延层上还有一深槽，于所述深槽内的侧壁上形成有介质绝缘层，且于所述深槽内填有半绝缘材料，所述半绝缘材料的上方形成有一与所述半绝缘材料接触的电极，所述半绝缘材料底部与所述高掺杂半导体材料区接触。
优选地，所述深槽垂直伸入于所述高掺杂半导体材料区内，这样可以使得电场分布最佳。
优选地，所述高掺杂半导体材料区与外延层可以为相同导电杂质类型。这是因为如果在不同导电杂质类型情况下虽然仍有一定的效果，不过一般会引起少子注入引起外延层载流子调制效应。
优选地，所述半绝缘材料电阻率为1×104Ω·cm～1×1013Ω·cm。
优选地，所述外延层杂质浓度高于同等工作电压下平行平面结对应的漂移区杂质浓度，以便降低导通电阻。这是因为不提高浓度，低导通电阻就无法实现，还会因为深槽面积占用电阻还会增加，是基本低导通功能需要。
优选地，所述介质绝缘层由单层介质或多层介质构成，以此来满足实际应用的范围。
进一步地，作为上述发明及其优选方案的进一步优化，于有源器件区上方形成有源区低压电极，作为所述半导体元胞结构的低压电极，其中，高掺杂半导体材料区对应为所述半导体元胞结构的高压电极。
另外，本发明还提供了一种功率半导体器件，其中，所述功率半导体器件中包括上述发明或其优选方案中任意一种半导体元胞结构。
需要说明的是此处高压应该理解为正高压或者负高压，有源区低压电极一般是此元胞阻断高压时最低电压，以典型的VDMOS(英文全称：vertical double diffusion metaloxide semiconductor，中文译为：垂直双扩散金属-氧化物半导体场效应晶体管)为例子来说，有源区低压电极是元胞的源电极或者是栅电极，当其处于关断时，是阻断高压状态，或者是关断承受高压的状态，此时栅电极可以是比源电极还低的关断电压，或者与源电极电压相同的电压，此时元胞仍然是关断承受高压的状态，因此，半绝缘层顶部电极连接到源电极或者连接到栅电极都是可以的，一般情况下，从简单可靠考虑，半绝缘层顶部电极直接连接到源电极，若连接到栅电极会增加栅电极的负载，影响元胞结构的开关速度，但连接到栅电极上对正向导通时的正向导通有一定好处，能进一步减小正向导通电阻，而反向关断承受高压时性能基本是相同的。
如上所述，本发明至少具有以下有益效果：
1)工艺相对其他现有高压低漂移区导通电阻半导体元胞结构更容易实现，成本相对较低；
2)因为其工作原理是电阻场板电势分布强制漂移区电场分布，对介质层中电荷有更好的抑制作用；
3)降低了现有普通超结电荷平衡工艺技术实施的难度，同样的电压因电荷失配导致的损失，包括介质层电荷引起的失配，举一个例子说明，对于600V的元胞结构，5％的普通超结元胞结构电压降低大约50～100V，而本方案元胞结构同样降低55V，可允许85％的电荷失配，这对降低工艺实施难度和工艺能力的要求，提高成品率有很大冗余度和好处，同时也提高了该结构工作的稳定性；
4)理论上保持了同等电压下比理想平行平面结漂移区小10～1000倍的比导通电阻性能，实际性能受制于工艺可实施能力。
附图说明
图1是高压低漂移区导通电阻半导体元胞结构现有技术方案示意图。
图2是本发明高压低漂移区导通电阻半导体元胞结构示意图。
图3是本发明实施例在N+高掺杂半导体材料区上生长N-外延层，并在其表面形成P型掺杂作为有源器件区，生长氧化层，使用光刻和刻蚀深槽后示意图。
图4是在本发明图3的硅片上深槽侧壁形成氧化层，并利用各向异性干法刻蚀掉深槽底部氧化层后示意图。
图5是在本发明图4的硅片上进行深槽半绝缘材料长，并去除表面半绝缘材料和氧化层，形成连接半绝缘材料电极和有源器件区的有源区低压电极后示意图。
元件标号说明
101 高掺杂半导体材料区
102 外延层
103 介质绝缘层
104 半绝缘材料
105 有源器件区
106 电极
107 有源区低压电极
108 氧化层
109 深槽
具体实施方式
以下由特定的具体实施例说明本发明的实施方式，熟悉此技术的人士可由本说明书所揭露的内容轻易地了解本发明的其他优点及功效。
请参阅图2至图5。须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“左”、“右”、“中间”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
请参阅图2，为一种高压低漂移区导通电阻半导体元胞结构的原理示意图，如图所示，该半导体元胞结构可以包括：高掺杂半导体材料区101，外延层102，介质绝缘层103，半绝缘材料104，有源器件区105，半绝缘层顶部电极106，有源区低压电极107。
在具体实施中，高掺杂半导体材料区101与外延层102可以是相同导电杂质类型。这是因为，一般来说应该主要只针对同型导电杂质类型，如果不同一般会引起少子注入引起外延层载流子调制效应。
在具体实施中，介质绝缘层103可以由单层介质或多层介质构成，介质绝缘层103垂直表面穿过外延层102，其底部延伸进入到高掺杂半导体材料区101里。
在具体实施中，半绝缘材料104位于介质绝缘层103的一侧，并随着介质绝缘层103垂直进入到高掺杂半导体材料区101里，且其底部与介质绝缘层103底部平齐，且半绝缘材料104底部与高掺杂半导体材料区101接触。
具体地，上述介质绝缘层103和半绝缘材料104可以通过在外延层102上还刻蚀有一深槽109，于深槽109内的侧壁上形成有介质绝缘层103并于深槽109内填有半绝缘材料104来实现。
在具体实施中，高掺杂半导体材料区101同时作为此高压低漂移区导通电阻半导体元胞结构的高压电极，其对应的低压电极是有源区低压电极107和半绝缘层顶部电极106，且半绝缘层顶部电极106与有源区低压电极107可以是同一电位。
在具体实施中，半绝缘材料104电阻率在1×104Ω·cm～1×1013Ω·cm范围内，外延层102杂质浓度高于同等工作电压下平行平面结对应的漂移区杂质浓度，否则本结构达不到降低导通电阻的效果，这是本技术领域的基本常识，这里不再进一步阐述。理论上此杂质浓度可以高到半导体材料的杂质固溶度的最大浓度，实际浓度取决于该元胞结构的工艺技术可实施能力。
在具体实施中，最佳的高压低漂移区导通电阻半导体元胞结构电场分布特征是：有源器件区105在反向高压时A位置附近的最高电场与外延层102、介质绝缘层103、高掺杂半导体材料区101交会点、外延层102侧B位置最高电场接近相等时，该元胞结构具有最佳的效果。
在具体实施中，介质绝缘层103和半绝缘材料104垂直进入外延层102的深度h与介质绝缘层103的厚度t相关，一般的趋势是介质绝缘层103的厚度t越薄，则深度h越小，极限情况下，深度h为零，即介质绝缘层103的厚度t与介质绝缘层103和半绝缘材料104垂直进入外延层102的深度h呈亚线性关系，极限情况下介质绝缘层103和半绝缘材料104底部与外延层102底部平齐。
在具体实施中，针对不同的工作电压，具体的最佳元胞尺寸结构采用工艺仿真软件结合工艺实施能力进行计算和仿真确定。
需要说明的是此处高压应该理解为正高压或者负高压，有源区低压电极107一般是此元胞阻断高压时最低电压，以典型的VDMOS为例子来说，有源区低压电极107是元胞的源电极或者是栅电极，当其处于关断时，是阻断高压状态，或者是关断承受高压的状态，此时栅电极可以是比源电极还低的关断电压，或者与源电极电压相同的电压，此时元胞仍然是关断承受高压的状态，因此，半绝缘层顶部电极106连接到源电极或者连接到栅电极都是可以的，一般情况下，从简单可靠考虑，半绝缘层顶部电极106直接连接到源电极，若连接到栅电极会增加栅电极的负载，影响元胞结构的开关速度，但连接到栅电极上对正向导通时的正向导通有一定好处，能进一步减小正向导通电阻，而反向关断承受高压时性能基本是相同的；
还需说明的是附图2高压低漂移区导通电阻半导体元胞结构只是左右对称的一半结构，简单做一个左右镜像(如图2，M为镜面)对称就得到完整的高压低漂移区导通电阻半导体元胞结构。
为了让本领域技术人员能够更好地理解上述方案，下面将通过举例来对上述方案进行详细地说明。
以有源器件区105为一个最简单的600V耐压的PN结二极管元胞结构为例来说明本技术方案的实施，二极管以外的其它具备本元胞结构描述特征的实施例不应被视为不同的元胞结构。这里的有源器件区105还可以是双极三极管、MOSFET、VDMOS、IGBT等能够利用此元胞结构达到高压低漂移区导通电阻性能的半导体元胞结构。
下面以结构最简单的硅二极管为例来具体说明：
1、根据二极管600V耐压要求，结合工艺实施能力，利用行业通用的半导体器件仿真工具软件进行元胞结构仿真，假设基本工艺能力可以做到3μm宽、40μm的深槽刻蚀，得到此高压低漂移区导通电阻半导体元胞结构参数为：
1)深槽深度40μm，宽度3μm，深入高掺杂半导体材料区101的深度h为3μm，
2)外延层102厚度为37μm，N型掺杂浓度为2.8×1015cm-3，
3)外延层102横向宽度5μm，
4)介质绝缘层103厚度t为300nm，
5)高掺杂半导体材料区101电阻率为0.02～0.001Ω·cm，N型<100>硅材料，
此时，该二极管元胞结构可承受的耐压为623V，比导通电阻为10mΩ·cm2，比同样耐压的理想平行平面结比导通小6.5倍，略好于普通超结元胞结构的5倍水平。
2、在上述元胞结构设计完成后，取0.02～0.001Ω.cm N型<100>硅材料上采用行业通行方法形成光刻对位标识，同时该硅材料作为高掺杂半导体材料区101；
3、在上述硅片上采用行业通行外延方法生长N型外延层102，其掺杂浓度取为上述设计值确定的2.8×1015/cm3，在需要形成表面P型掺杂的区域使用套刻带胶离子注入方式来实现，其浓度大于1×1019/cm3，与外延层102形成的PN结结深0.1μm～2μm，此PN结作为有源器件区105，使用行业通用热氧化形成40nm氧化层，再使用LPCVD淀积500nm氧化层形成氧化层108，作为深槽刻蚀的硬掩膜，采用通用光刻方法曝光显影出待刻蚀深槽图形，并在外延层102上使用高度各向异性的干法刻蚀机刻蚀出深槽109，如图3所示；
4、完成第3步后，采用行业通用清洗程序将硅片清洗干净，使用热氧化或者CVD方式对深槽侧壁进行热氧化或者淀积氧化层，此氧化层厚度为300nm，再使用高度各向异性干法刻蚀将深槽底部的氧化层刻蚀掉，保留深槽侧壁的氧化层，形成介质绝缘层103，如图4所示；
5、再使用行业通用的LPCVD方式在第4步硅片上淀积半绝缘多晶硅层，厚度要能填满深槽，具体值是1.8μm，可以分为3次完成此半绝缘多晶硅的淀积，此半绝缘多晶硅电阻率在1×108Ω·cm～1×1010Ω·cm范围内，完成此半绝缘多晶硅淀积后深槽被封闭或者填满，若存在深槽半绝缘填充空隙将对元胞结构有轻微影响，但不严重，此半绝缘多晶硅层作为的半绝缘材料104，然后使用CMP或干法刻蚀方式去掉硅片表面半绝缘多晶硅，再去掉表面氧化层，最后采用行业通行的溅射或者蒸发形成表面金属电极106和107，然后进行行业通用的合金处理，最终完成元胞结构的制作，如图5所示。
若是工艺能力，尤其是深槽刻蚀工艺能力很强，假设基本工艺能力进一步可以做到2μm宽、45μm的深槽刻蚀能力，则可以得到此高压低漂移区导通电阻半导体元胞结构另一套新的参数为：
1)深槽深度45μm，宽度2μm，深入高掺杂半导体材料区101的深度h为3μm；
2)外延层102厚度为42μm，N型掺杂浓度为1.68×1016cm-3；
3)外延层102横向宽度1μm；
4)介质绝缘层103厚度t为500nm。
此时，该二极管元胞结构可承受的耐压为628V，比导通电阻为5.44mΩ·cm2，比同样耐压的理想平行平面结比导通小13倍，远好于普通超结元胞结构的5倍性能。
需要说明的是，可以将上述半导体元胞结构应用到功率半导体器件中，以获得可以承受更高的漂移区击穿电压并兼具更低的导通电阻的功率半导体器件。
综上所述，本发明所提供的半导体元胞结构至少具有以下优点：
1)工艺相对其他现有高压低漂移区导通电阻半导体元胞结构更容易实现，成本相对较低；
2)因为其工作原理是电阻场板电势分布强制漂移区电场分布，对介质层中电荷有更好的抑制作用；
3)降低了现有普通超结电荷平衡工艺技术实施的难度，同样的电压因电荷失配导致的损失，包括介质层电荷引起的失配，举一个例子说明，对于600V的元胞结构，5％的普通超结元胞结构电压降低大约50～100V，而本方案元胞结构同样降低55V，可允许85％的电荷失配，这对降低工艺实施难度和工艺能力的要求，提高成品率有很大冗余度和好处，同时也提高了该结构工作的稳定性；
4)理论上保持了同等电压下比理想平行平面结漂移区小10～1000倍的比导通电阻性能，实际性能受制于工艺可实施能力。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (7)

1.一种半导体元胞结构，至少包括：
高掺杂半导体材料区(101)；
形成于高掺杂半导体材料区(101)上的外延层(102)；
形成于外延层(102)上的有源器件区(105)；
其特征在于：
在外延层(102)上具有一深槽(109)，深槽(109)垂直进入到高掺杂半导体材料区(101)里，于深槽(109)内的侧壁上形成有介质绝缘层(103)，且于深槽(109)内填有半绝缘材料(104)，半绝缘材料(104)的上方形成有一与半绝缘材料(104)接触的电极(106)，半绝缘材料(104)底部与高掺杂半导体材料区(101)接触；半绝缘材料(104)与介质绝缘层(103)的底部延伸进入到高掺杂半导体材料区(101)里，深入深度为h，其中h>0；介质绝缘层(103)和半绝缘材料(104)垂直进入高掺杂半导体材料区(101)的深度h与介质绝缘层(103)的厚度t相关。
2.根据权利要求1所述的半导体元胞结构，其特征在于，高掺杂半导体材料区(101)与外延层(102)为相同导电杂质类型。
3.根据权利要求1所述的半导体元胞结构，其特征在于，半绝缘材料(104)电阻率为1×104Ω·cm～1×1013Ω·cm。
4.根据权利要求1所述的半导体元胞结构，其特征在于，外延层(102)杂质浓度高于同等工作电压下平行平面结对应的漂移区杂质浓度。
5.根据权利要求1所述的半导体元胞结构，其特征在于，介质绝缘层(103)由单层介质或多层介质构成。
6.根据权利要求1所述的半导体元胞结构，其特征在于，于有源器件区(105)上方形成有源区低压电极(107)，作为所述半导体元胞结构的低压电极，其中，高掺杂半导体材料区(101)对应为所述半导体元胞结构的高压电极。
7.一种功率半导体器件，其特征在于：功率半导体器件包括上述权利要求1-6的半导体元胞结构。
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