CN105513960A - 氧化硅薄膜的沉积方法及低温多晶硅tft基板的制备方法 - Google Patents

氧化硅薄膜的沉积方法及低温多晶硅tft基板的制备方法 Download PDF

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CN105513960A
CN105513960A CN201610054751.0A CN201610054751A CN105513960A CN 105513960 A CN105513960 A CN 105513960A CN 201610054751 A CN201610054751 A CN 201610054751A CN 105513960 A CN105513960 A CN 105513960A
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silicon oxide
low temperature
oxide film
oxygen
thin film
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CN105513960B (zh
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马伟欣
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Changsha HKC Optoelectronics Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种氧化硅薄膜的沉积方法与低温多晶硅TFT基板的制备方法。该氧化硅薄膜的沉积方法通过引入紫外光作为沉积氧化硅反应的辅助能量,利用紫外光将氧气分解为游离氧,与有机硅烷气体反应生成氧化硅,从而在无等离子体环境中沉积形成氧化硅薄膜,避免了氧化硅薄膜表面被高能量的等离子体撞击所形成的界面缺陷和表面损伤,提高氧化硅薄膜的成膜质量。该低温多晶硅TFT基板的制备方法通过采用在紫外光照射环境中有机硅烷气体与氧气反应生成氧化硅的方法来制作栅极绝缘层中的氧化硅薄膜,避免了现有等离子体增强化学气相沉积方法中等离子体对氧化硅薄膜表面造成的表面缺陷和界面损伤,从而提高氧化硅薄膜的成膜质量,提升TFT电性。

Description

氧化硅薄膜的沉积方法及低温多晶硅TFT基板的制备方法
技术领域
本发明涉及显示技术领域,尤其涉及一种氧化硅薄膜的沉积方法及低温多晶硅TFT基板的制备方法。
背景技术
随着显示技术的发展,液晶显示器(LiquidCrystalDisplay,LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点,而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品,成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器,其包括液晶显示面板及背光模组(backlightmodule)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子,两片玻璃基板中间有许多垂直和水平的细小电线,通过通电与否来控制液晶分子改变方向,将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF,ColorFilter)基板、薄膜晶体管(TFT,ThinFilmTransistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC,LiquidCrystal)及密封胶框(Sealant)组成,其成型工艺一般包括:前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中,前段Array制程主要是形成TFT基板,以便于控制液晶分子的运动;中段Cell制程主要是在TFT基板与CF基板之间添加液晶;后段模组组装制程主要是驱动IC压合与印刷电路板的整合,进而驱动液晶分子转动,显示图像。
低温多晶硅(LowTemperaturePolySilicon,LTPS)是广泛用于中小电子产品中的一种液晶显示技术,传统的非晶硅材料的电子迁移率约0.5-1.0cm2/V.S,而低温多晶硅的电子迁移率可达30-300cm2/V.S,因此,低温多晶硅液晶显示器具有高解析度、反应速度快、高开口率等诸多优点,但是另一方面,由于LTPS半导体器件的体积小、集成度高,所以整个低温多晶硅TFT基板的制备工艺复杂,生产成本较高。
图1为现有的低温多晶硅TFT基板的部分膜层的结构示意图,所述低温多晶硅TFT基板包括衬底基板100、以及从下至上依次设于所述衬底基板100上的缓冲层200、多晶硅层300、栅极绝缘层400、及栅极500等膜层结构,在各膜层结构中,栅极绝缘层400是一层非常重要的半导体结构。栅极绝缘层400作为LTPSTFT的沟道与栅极(Gate)500之间的绝缘层,其通常由氧化硅(SiOx)薄膜401和氮化硅(SiNx)薄膜402构成,其中,氧化硅薄膜401的成膜质量好坏对于整个TFT的电性有着非常重要的影响,对于不同的沉积方法,氧化硅薄膜的成膜质量往往不同。
目前常用的沉积氧化硅薄膜的方法为等离子体增强化学气相沉积方法(PlasmaEnhancedChemicalVaporDeposition,PECVD),如图2所示,现有的氧化硅薄膜的等离子体增强化学气相沉积方法为:在化学气相沉积装置中通入氩气(Ar),在13.5MHz或27.12MHz的射频环境中产生氩离子(Ar+),利用Ar+作为离子源,在电场作用下轰击反应气体SiH4与N2O,使得反应气体受到轰击而活化,进而在基板(如低温多晶硅TFT基板的多晶硅层300)表面发生化学反应生成氧化硅,该化学反应的反应式为:SiH4+N2O→SiOx+N2+H2O,其中N2O中的氮成分,使得生成的氧化硅薄膜401与多晶硅层300的界面缺陷较多,造成平带电压漂移较大;其次,PECVD过程中Ar+作为等离子源撞击氧化硅薄膜401表面,容易形成界面缺陷和表面损伤。
因此有必要提出一种氧化硅薄膜的沉积方法及低温多晶硅TFT基板的制备方法,以解决上述问题。
发明内容
本发明的目的在于提供一种氧化硅薄膜的沉积方法,通过引入紫外光作为沉积氧化硅反应的辅助能量,在无等离子体环境中沉积形成氧化硅薄膜,提高氧化硅薄膜的成膜质量。
本发明的目的还在于提供一种低温多晶硅TFT基板的制备方法,通过采用在紫外光照射环境中有机硅烷气体与氧气反应生成氧化硅的方法来制作栅极绝缘层中的氧化硅薄膜,提高氧化硅薄膜的成膜质量,对TFT电性有较好的提升作用。
为实现上述目的,本发明提供一种氧化硅薄膜的沉积方法,包括如下步骤:
步骤1、提供一化学气相沉积装置,所述化学气相沉积装置具有一反应腔室,所述反应腔室的上方设有紫外光源;
步骤2、在所述反应腔室的底部放置一基板,向所述反应腔室中通入有机硅烷气体和氧气,打开所述紫外光源,所述氧气在紫外光的照射下分解产生游离氧,所述有机硅烷气体和游离氧发生化学反应生成氧化硅,沉积于基板上形成氧化硅薄膜。
所述有机硅烷气体为四乙氧基硅烷、四甲基硅烷、四甲基环四硅氧烷、八甲基环四硅氧烷、六甲基二硅氮烷、三乙氧基甲硅烷、或三二甲氨基硅烷。
所述有机硅烷气体为四乙氧基硅烷,所述四乙氧基硅烷与氧气在紫外光下反应生成氧化硅的反应式为:Si(OC2H5)4+O2→SiOx+2H2O+CO2
所述紫外光源发出的紫外光为波长在10nm到14nm之间的极紫外光。
本发明还提供一种低温多晶硅TFT基板的制备方法,包括如下步骤:
步骤1、提供一衬底基板,在所述衬底基板上依次形成缓冲层与多晶硅层;
步骤2、对所述多晶硅层进行图形化处理,形成多晶硅岛,对所述多晶硅岛的中间区域进行P型轻掺杂,得到沟道区,对所述多晶硅岛的两侧进行N型或P型重掺杂,得到源极接触区与漏极接触区;
步骤3、提供一化学气相沉积装置,所述化学气相沉积装置具有一反应腔室,所述反应腔室的上方设有紫外光源;
将所述具有多晶硅岛及缓冲层的基板放置于所述反应腔室的底部,向所述反应腔室中通入有机硅烷气体和氧气,打开所述紫外光源,所述氧气在紫外光的照射下分解产生游离氧,所述有机硅烷气体和游离氧发生化学反应生成氧化硅,沉积于多晶硅岛及缓冲层上形成氧化硅薄膜;
步骤4、在所述氧化硅薄膜上沉积氮化硅薄膜,得到由氧化硅薄膜与氮化硅薄膜叠加构成的栅极绝缘层;
步骤5、在所述栅极绝缘层上沉积第一金属层,对所述第一金属层进行图形化处理,得到栅极;
步骤6、在所述栅极、及栅极绝缘层上形成层间绝缘层,对所述层间绝缘层及栅极绝缘层进行图形化处理,得到对应于所述源极接触区与漏极接触区上方的过孔;
步骤7、在所述层间绝缘层上沉积第二金属层,对所述第二金属层进行图形化处理,得到源极与漏极,所述源极与漏极分别经由过孔与所述多晶硅岛上的源极接触区与漏极接触区相接触。
所述有机硅烷气体为四乙氧基硅烷、四甲基硅烷、四甲基环四硅氧烷、八甲基环四硅氧烷、六甲基二硅氮烷、三乙氧基甲硅烷、或三二甲氨基硅烷。
所述有机硅烷气体为四乙氧基硅烷,所述四乙氧基硅烷与氧气在紫外光下反应生成氧化硅的反应式为:Si(OC2H5)4+O2→SiOx+2H2O+CO2
所述紫外光源发出的紫外光为波长在10nm到14nm之间的极紫外光。
所述多晶硅层的制作过程为:在所述缓冲层上沉积非晶硅层,采用低温结晶工艺将所述非晶硅层转化为多晶硅层,所述低温结晶工艺为准分子激光退火法或金属诱导横向晶化法。
所述基板为玻璃基板;所述缓冲层、层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层;所述栅极、源极、漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果:本发明提供的一种氧化硅薄膜的沉积方法,通过引入紫外光作为沉积氧化硅反应的辅助能量,利用紫外光将氧气分解为游离氧,与有机硅烷气体反应生成氧化硅,从而在无等离子体环境中沉积形成氧化硅薄膜,避免了氧化硅薄膜表面被高能量的等离子体撞击所形成的界面缺陷和表面损伤,提高氧化硅薄膜的成膜质量。本发明提供的一种低温多晶硅TFT基板的制备方法,通过采用在紫外光照射环境中有机硅烷气体与氧气反应生成氧化硅的方法来制作栅极绝缘层中的氧化硅薄膜,避免了现有的等离子体增强化学气相沉积方法中等离子体对氧化硅薄膜表面造成的表面缺陷和界面损伤,从而提高氧化硅薄膜的成膜质量,对TFT电性有较好的提升作用。
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
附图中,
图1为现有的低温多晶硅TFT基板的部分膜层的结构示意图;
图2为现有的氧化硅薄膜的等离子体增强化学气相沉积方法的示意图;
图3为本发明的氧化硅薄膜的沉积方法的示意图;
图4为本发明的低温多晶硅TFT基板的制备方法步骤1的示意图;
图5为本发明的低温多晶硅TFT基板的制备方法步骤2的示意图;
图6为本发明的低温多晶硅TFT基板的制备方法步骤3的示意图;
图7为本发明的低温多晶硅TFT基板的制备方法步骤4的示意图;
图8为本发明的低温多晶硅TFT基板的制备方法步骤5的示意图;
图9为本发明的低温多晶硅TFT基板的制备方法步骤6的示意图;
图10为本发明的低温多晶硅TFT基板的制备方法步骤7的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3,本发明提供一种氧化硅薄膜的沉积方法,包括如下步骤:
步骤1、提供一化学气相沉积装置110,所述化学气相沉积装置110具有一反应腔室120,所述反应腔室120的上方设有紫外光源130。
步骤2、在所述反应腔室120的底部放置一基板210,向所述反应腔室120中通入有机硅烷气体和氧气,打开所述紫外光源130,所述氧气在紫外光的照射下分解产生游离氧,所述有机硅烷气体和游离氧发生化学反应生成氧化硅(SiOx),沉积于基板210上形成氧化硅薄膜250。
具体的,所述有机硅烷气体可以为四乙氧基硅烷(TEOS)(化学式:Si(OC2H5)4)、四甲基硅烷(TMS)(化学式:Si(CH3)4)、四甲基环四硅氧烷(TMCTS)、八甲基环四硅氧烷(OMCTS)、六甲基二硅氮烷(HMDS)、三乙氧基甲硅烷(SiH(OC2H5)3)、或三二甲氨基硅烷(trisdimethylaminosilane,SiH(N(CH3)2)3等等。
优选的,所述有机硅烷气体为四乙氧基硅烷,所述四乙氧基硅烷与氧气在紫外光下反应生成氧化硅的反应式为:Si(OC2H5)4+O2→SiOx+2H2O+CO2,其中,x=1或2。
优选的,所述紫外光源130发出的紫外光为波长在10nm到14nm之间的极紫外光(EUV),因为极紫外光(EUV)的波长较短,能量较高,可以让参与反应的有机硅烷气体在短时间内大量分解活化,使反应的时间缩短。
优选的,所述步骤2得到的氧化硅薄膜250的厚度为
请参阅图4-10,本发明还提供一种低温多晶硅TFT基板的制备方法,包括如下步骤:
步骤1、如图4所示,提供一衬底基板10,在所述衬底基板10上依次形成缓冲层20与多晶硅层30。
具体的,所述多晶硅层30的制作过程为:在所述缓冲层20上沉积非晶硅层,采用低温结晶工艺将所述非晶硅层转化为多晶硅层30,所述低温结晶工艺可以为准分子激光退火法(ExcimerLaserAnnealing,ELA)或金属诱导横向晶化法(MetalInducedlateralCrystallization,MILC)等等。
步骤2、如图5所示,对所述多晶硅层30进行图形化处理,形成多晶硅岛40,对所述多晶硅岛40的中间区域进行P型轻掺杂,得到沟道区41,对所述多晶硅岛40的两侧进行N型或P型重掺杂,得到源极接触区42与漏极接触区43。
具体的,所述N型掺杂掺入的离子为磷离子或砷离子;所述P型掺杂掺入的离子为硼离子或镓离子。
步骤3、如图6所示,提供一化学气相沉积装置110,所述化学气相沉积装置110具有一反应腔室120,所述反应腔室120的上方设有紫外光源130;
将所述具有多晶硅岛40及缓冲层20的基板10放置于所述反应腔室120的底部,向所述反应腔室120中通入有机硅烷气体和氧气,打开所述紫外光源130,所述氧气在紫外光的照射下分解产生游离氧,所述有机硅烷气体和游离氧发生化学反应生成氧化硅(SiOx),沉积于多晶硅岛40及缓冲层20上形成氧化硅薄膜250。
具体的,所述有机硅烷气体可以为四乙氧基硅烷(TEOS)(化学式:Si(OC2H5)4)、四甲基硅烷(TMS)(化学式:Si(CH3)4)、四甲基环四硅氧烷(TMCTS)、八甲基环四硅氧烷(OMCTS)、六甲基二硅氮烷(HMDS)、三乙氧基甲硅烷(SiH(OC2H5)3)、或三二甲氨基硅烷(trisdimethylaminosilane,SiH(N(CH3)2)3)等等。
优选的,所述有机硅烷气体为四乙氧基硅烷,所述四乙氧基硅烷与氧气在紫外光下反应生成氧化硅的反应式为:Si(OC2H5)4+O2→SiOx+2H2O+CO2,其中,x=1或2。
优选的,所述紫外光源130发出的紫外光为波长在10nm到14nm之间的极紫外光(EUV),因为极紫外光(EUV)的波长较短,能量较高,可以让参与反应的有机硅烷气体在短时间内大量分解活化,使反应的时间缩短。
优选的,所述步骤2得到的氧化硅薄膜250的厚度为
步骤4、如图7所示,在所述氧化硅薄膜250上沉积氮化硅薄膜260,得到由氧化硅薄膜250与氮化硅薄膜260叠加构成的栅极绝缘层50。
步骤5、如图8所示,在所述栅极绝缘层50上沉积第一金属层,对所述第一金属层进行图形化处理,得到栅极60。
步骤6、如图9所示,在所述栅极60、及栅极绝缘层50上形成层间绝缘层70,对所述层间绝缘层70及栅极绝缘层50进行图形化处理,得到对应于所述源极接触区42与漏极接触区43上方的过孔71。
步骤7、如图10所示,在所述层间绝缘层70上沉积第二金属层,对所述第二金属层进行图形化处理,得到源极81与漏极82,所述源极81与漏极82分别经由过孔71与所述多晶硅岛40上的源极接触区42与漏极接触区43相接触。
具体的,所述基板10为玻璃基板。
具体的,所述缓冲层20、层间绝缘层70可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的,所述栅极60、源极81、漏极82的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
综上所述,本发明提供的一种氧化硅薄膜的沉积方法,通过引入紫外光作为沉积氧化硅反应的辅助能量,利用紫外光将氧气分解为游离氧,与有机硅烷气体反应生成氧化硅,从而在无等离子体环境中沉积形成氧化硅薄膜,避免了氧化硅薄膜表面被高能量的等离子体撞击所形成的界面缺陷和表面损伤,提高氧化硅薄膜的成膜质量。本发明提供的一种低温多晶硅TFT基板的制备方法,通过采用在紫外光照射环境中有机硅烷气体与氧气反应生成氧化硅的方法来制作栅极绝缘层中的氧化硅薄膜,避免了现有的等离子体增强化学气相沉积方法中等离子体对氧化硅薄膜表面造成的表面缺陷和界面损伤,从而提高氧化硅薄膜的成膜质量,对TFT电性有较好的提升作用。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种氧化硅薄膜的沉积方法,其特征在于,包括如下步骤:
步骤1、提供一化学气相沉积装置(110),所述化学气相沉积装置(110)具有一反应腔室(120),所述反应腔室(120)的上方设有紫外光源(130);
步骤2、在所述反应腔室(120)的底部放置一基板(210),向所述反应腔室(120)中通入有机硅烷气体和氧气,打开所述紫外光源(130),所述氧气在紫外光的照射下分解产生游离氧,所述有机硅烷气体和游离氧发生化学反应生成氧化硅,沉积于基板(210)上形成氧化硅薄膜(250)。
2.如权利要求1所述的氧化硅薄膜的沉积方法,其特征在于,所述有机硅烷气体为四乙氧基硅烷、四甲基硅烷、四甲基环四硅氧烷、八甲基环四硅氧烷、六甲基二硅氮烷、三乙氧基甲硅烷、或三二甲氨基硅烷。
3.如权利要求2所述的氧化硅薄膜的沉积方法,其特征在于,所述有机硅烷气体为四乙氧基硅烷,所述四乙氧基硅烷与氧气在紫外光下反应生成氧化硅的反应式为:Si(OC2H5)4+O2→SiOx+2H2O+CO2
4.如权利要求1所述的氧化硅薄膜的沉积方法,其特征在于,所述紫外光源(130)发出的紫外光为波长在10nm到14nm之间的极紫外光。
5.一种低温多晶硅TFT基板的制备方法,其特征在于,包括如下步骤:
步骤1、提供一衬底基板(10),在所述衬底基板(10)上依次形成缓冲层(20)与多晶硅层(30);
步骤2、对所述多晶硅层(30)进行图形化处理,形成多晶硅岛(40),对所述多晶硅岛(40)的中间区域进行P型轻掺杂,得到沟道区(41),对所述多晶硅岛(40)的两侧进行N型或P型重掺杂,得到源极接触区(42)与漏极接触区(43);
步骤3、提供一化学气相沉积装置(110),所述化学气相沉积装置(110)具有一反应腔室(120),所述反应腔室(120)的上方设有紫外光源(130);
将所述具有多晶硅岛(40)及缓冲层(20)的基板(10)放置于所述反应腔室(120)的底部,向所述反应腔室(120)中通入有机硅烷气体和氧气,打开所述紫外光源(130),所述氧气在紫外光的照射下分解产生游离氧,所述有机硅烷气体和游离氧发生化学反应生成氧化硅,沉积于多晶硅岛(40)及缓冲层(20)上形成氧化硅薄膜(250);
步骤4、在所述氧化硅薄膜(250)上沉积氮化硅薄膜(260),得到由氧化硅薄膜(250)与氮化硅薄膜(260)叠加构成的栅极绝缘层(50);
步骤5、在所述栅极绝缘层(50)上沉积第一金属层,对所述第一金属层进行图形化处理,得到栅极(60);
步骤6、在所述栅极(60)、及栅极绝缘层(50)上形成层间绝缘层(70),对所述层间绝缘层(70)及栅极绝缘层(50)进行图形化处理,得到对应于所述源极接触区(42)与漏极接触区(43)上方的过孔(71);
步骤7、在所述层间绝缘层(70)上沉积第二金属层,对所述第二金属层进行图形化处理,得到源极(81)与漏极(82),所述源极(81)与漏极(82)分别经由过孔(71)与所述多晶硅岛(40)上的源极接触区(42)与漏极接触区(43)相接触。
6.如权利要求5所述的低温多晶硅TFT基板的制备方法,其特征在于,所述有机硅烷气体为四乙氧基硅烷、四甲基硅烷、四甲基环四硅氧烷、八甲基环四硅氧烷、六甲基二硅氮烷、三乙氧基甲硅烷、或三二甲氨基硅烷。
7.如权利要求6所述的低温多晶硅TFT基板的制备方法,其特征在于,所述有机硅烷气体为四乙氧基硅烷,所述四乙氧基硅烷与氧气在紫外光下反应生成氧化硅的反应式为:Si(OC2H5)4+O2→SiOx+2H2O+CO2
8.如权利要求5所述的低温多晶硅TFT基板的制备方法,其特征在于,所述紫外光源(130)发出的紫外光为波长在10nm到14nm之间的极紫外光。
9.如权利要求5所述的低温多晶硅TFT基板的制备方法,其特征在于,所述多晶硅层(30)的制作过程为:在所述缓冲层(20)上沉积非晶硅层,采用低温结晶工艺将所述非晶硅层转化为多晶硅层(30),所述低温结晶工艺为准分子激光退火法或金属诱导横向晶化法。
10.如权利要求5所述的低温多晶硅TFT基板的制备方法,其特征在于,所述基板(10)为玻璃基板;所述缓冲层(20)、层间绝缘层(70)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层;所述栅极(60)、源极(81)、漏极(82)的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106601997A (zh) * 2016-11-24 2017-04-26 天津大学 一种在负极集流体材料上激光溅射沉积渔网状SiOx薄膜的制备方法
WO2017128564A1 (zh) * 2016-01-27 2017-08-03 武汉华星光电技术有限公司 氧化硅薄膜的沉积方法及低温多晶硅tft基板的制备方法
CN108072989A (zh) * 2017-07-28 2018-05-25 武汉华星光电技术有限公司 液晶显示面板的处理方法
CN112383871A (zh) * 2021-01-15 2021-02-19 中芯集成电路制造(绍兴)有限公司 麦克风部件及其制作方法
WO2024007495A1 (zh) * 2022-07-07 2024-01-11 中国科学院宁波材料技术与工程研究所 改性隧穿氧化层及制备方法、TOPCon结构及制备方法和太阳电池

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7211969B2 (ja) * 2017-04-27 2023-01-24 アプライド マテリアルズ インコーポレイテッド 3d nandに適用するための低誘電率酸化物および低抵抗のopスタック
US11221359B2 (en) * 2019-03-15 2022-01-11 International Business Machines Corporation Determining device operability via metal-induced layer exchange
CN113979402A (zh) * 2021-09-30 2022-01-28 山东大学 一种mems红外光源及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5953674A (ja) * 1982-09-17 1984-03-28 Seiko Epson Corp 化学蒸着法
US4702936A (en) * 1984-09-20 1987-10-27 Applied Materials Japan, Inc. Gas-phase growth process
US20090183766A1 (en) * 2008-01-22 2009-07-23 Hidekazu Takahashi Semiconductor device and method of manufacturing semiconductor device
CN103972050A (zh) * 2014-05-14 2014-08-06 京东方科技集团股份有限公司 多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1326271A4 (en) * 2000-09-18 2005-08-24 Tokyo Electron Ltd METHOD FOR FILMING A GATE INSULATOR, DEVICE FOR FILMING A GATE INSULATOR AND A CLUSTER TOOL
JP5052071B2 (ja) * 2006-08-25 2012-10-17 株式会社明電舎 酸化膜形成方法とその装置
JP5953674B2 (ja) * 2010-08-26 2016-07-20 三菱化学株式会社 多孔質支持体―ゼオライト膜複合体およびそれを用いる分離方法
CN105070764A (zh) * 2015-08-31 2015-11-18 深圳市华星光电技术有限公司 Tft、阵列基板、显示装置及tft的制备方法
CN105513960B (zh) * 2016-01-27 2019-01-11 武汉华星光电技术有限公司 氧化硅薄膜的沉积方法及低温多晶硅tft基板的制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5953674A (ja) * 1982-09-17 1984-03-28 Seiko Epson Corp 化学蒸着法
US4702936A (en) * 1984-09-20 1987-10-27 Applied Materials Japan, Inc. Gas-phase growth process
US20090183766A1 (en) * 2008-01-22 2009-07-23 Hidekazu Takahashi Semiconductor device and method of manufacturing semiconductor device
CN103972050A (zh) * 2014-05-14 2014-08-06 京东方科技集团股份有限公司 多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017128564A1 (zh) * 2016-01-27 2017-08-03 武汉华星光电技术有限公司 氧化硅薄膜的沉积方法及低温多晶硅tft基板的制备方法
CN106601997A (zh) * 2016-11-24 2017-04-26 天津大学 一种在负极集流体材料上激光溅射沉积渔网状SiOx薄膜的制备方法
CN106601997B (zh) * 2016-11-24 2019-08-20 天津大学 一种在负极集流体材料上激光溅射沉积渔网状SiOx薄膜的制备方法
CN108072989A (zh) * 2017-07-28 2018-05-25 武汉华星光电技术有限公司 液晶显示面板的处理方法
CN108072989B (zh) * 2017-07-28 2020-12-29 武汉华星光电技术有限公司 液晶显示面板的处理方法
CN112383871A (zh) * 2021-01-15 2021-02-19 中芯集成电路制造(绍兴)有限公司 麦克风部件及其制作方法
WO2024007495A1 (zh) * 2022-07-07 2024-01-11 中国科学院宁波材料技术与工程研究所 改性隧穿氧化层及制备方法、TOPCon结构及制备方法和太阳电池

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