JP7211969B2 - 3d nandに適用するための低誘電率酸化物および低抵抗のopスタック - Google Patents
3d nandに適用するための低誘電率酸化物および低抵抗のopスタック Download PDFInfo
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Description
Claims (9)
- メモリデバイススタックを製造する方法であって、
基板をPECVDチャンバ内に配置することと、
オクタメチルシクロテトラシロキサン前駆体を前記PECVDチャンバに導入して、前記基板の上に酸化ケイ素層を堆積させることと、
300kHzから400kHzの間のRF周波数で前記酸化ケイ素層をボンバードすることと、
前記酸化ケイ素層の上にポリシリコン層を堆積させることと、
を含む方法。 - 前記酸化ケイ素層の上にポリシリコン層を堆積させることが、
シランとゲルマンを前記PECVDチャンバに導入して、前記ポリシリコン層を堆積させることを含む、請求項1に記載の方法。 - オクタメチルシクロテトラシロキサン前駆体を前記PECVDチャンバに導入して、前記基板の上に前記酸化ケイ素層を堆積させることが、27メガヘルツの周波数で行われる、請求項1に記載の方法。
- 前記方法が、前記酸化ケイ素層と前記ポリシリコン層との間の界面をプラズマ処理することを、さらに含み、前記プラズマ処理が、NH3またはN2を前記PECVDチャンバに導入することを含む、請求項1に記載の方法。
- 前記酸化ケイ素層の上に前記ポリシリコン層を堆積させることが、
シラン、アルゴン、およびヘリウムからなる群から選択された1つ以上の前駆体、ならびにホスフィンおよびジボランからなる群から選択された1つ以上のドーパント前駆体を、前記PECVDチャンバに導入して、前記酸化ケイ素層の上にアモルファスシリコン層を堆積させることと、
前記アモルファスシリコン層をアニーリングして、前記ポリシリコン層を形成することと、
を含む、請求項1に記載の方法。 - 前記酸化ケイ素層の上に前記ポリシリコン層を堆積させることが、
シランからなる群から選択された少なくとも1つのケイ素前駆体およびゲルマンを、前記PECVDチャンバに導入して、SixGe(1-x)膜を形成することを含む、請求項1に記載の方法。 - メモリデバイススタックを製造する方法であって、
基板をPECVDチャンバ内に配置することと、
前記基板の上に酸化ケイ素層を堆積させることと、
ケイ素前駆体とゲルマンを前記PECVDチャンバに導入して、前記酸化ケイ素層の上にポリシリコン層を堆積させることと、
300kHzから400kHzの間のRF周波数で前記酸化ケイ素層をボンバードすることと、
を含む方法。 - 前記基板の上に酸化ケイ素層を堆積させることが、
OMCTS前駆体を前記PECVDチャンバに導入して、前記酸化ケイ素層を堆積させることを含む、請求項7に記載の方法。 - 前記方法が、前記酸化ケイ素層と前記ポリシリコン層との間の界面をプラズマ処理することを、さらに含み、前記プラズマ処理が、NH3またはN2を前記PECVDチャンバに導入することを含む、請求項7に記載の方法。
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PCT/US2018/028632 WO2018200335A1 (en) | 2017-04-27 | 2018-04-20 | Low dielectric constant oxide and low resistance op stack for 3d nand application |
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