CN110235248B - 用于3d nand应用的低介电常数氧化物和低电阻op堆叠 - Google Patents

用于3d nand应用的低介电常数氧化物和低电阻op堆叠 Download PDF

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CN110235248B
CN110235248B CN201880009550.6A CN201880009550A CN110235248B CN 110235248 B CN110235248 B CN 110235248B CN 201880009550 A CN201880009550 A CN 201880009550A CN 110235248 B CN110235248 B CN 110235248B
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silicon oxide
oxide layer
layer
pecvd chamber
polysilicon layer
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CN110235248A (zh
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韩新海
K·S·伊姆
Z·江
D·帕德希
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Applied Materials Inc
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Abstract

本文所述的实施例大体涉及制造用于存储器器件(诸如NAND器件)的3D存储器单元的氧化物/多晶硅(OP)堆叠的方法。所述方法通常包括在PECVD工艺期间用前驱物处理所述氧化物和/或多晶硅材料，以降低所述氧化物的介电常数并降低所述多晶硅的电阻率。在一个实施例中，用八甲基环四硅氧烷(OMCTS)前驱物处理所述氧化物材料。在另一个实施例中，将锗烷(GeH4)引入PECVD工艺以形成具有掺杂剂的SixGe(1‑x)膜。在又一个实施例中，使用等离子体处理工艺来氮化所述OP堆叠的层之间的界面。所述前驱物和等离子体处理可以单独地使用或以任何组合使用，以产生具有低介电常数氧化物和低电阻率多晶硅的OP堆叠。

Description

用于3D NAND应用的低介电常数氧化物和低电阻OP堆叠
技术领域
本公开的实施例大体涉及存储器制造工艺，并且更具体地，涉及制造具有低介电常数和降低的电阻率的3D存储器单元的方法。
背景技术
不断增长的需求继续推动对具有更小几何尺寸并且成本更低的高容量、高性能计算机存储器器件的需求。为此，存储器单元的部件彼此堆叠以产生三维(3D)存储器单元，诸如竖直栅极3D存储器单元。一种这样的技术是NAND闪存存储器，其一般存在于存储卡、USB闪存驱动器、固态驱动器、以及用于数据存储和传输的其它类似的装置中。在NAND闪存存储器中，由晶体管制成的存储器单元串联连接并堆叠在竖直层中以产生密集封装的高容量存储器器件。闪存驱动器通常使用较少的功率并且比普通硬盘驱动器更耐用，因为它们不包含移动零件。因此，人们对增加闪存驱动器的容量而同时减小其尺寸和成本有很大兴趣。
随着闪存技术发展，如何小规模地产生高容量器件仍然存在限制。例如，在微观规模上组合的不同材料具有不同的物理性质，这导致闪存器件中的不均匀性。许多竖直3D存储器单元因它们的集成性质而包括氧化物/多晶硅(OP)堆叠和/或氧化物/氮化物(ON)堆叠。然而，问题是氧化物材料一般具有高介电常数和电阻-电容(RC)延迟，并且多晶硅材料具有高电阻率。
因此，需要制造具有低介电常数和降低的电阻率的存储器结构(诸如3D存储器单元)的改善的方法。
发明内容
本文所述的实施例大体涉及制造用于存储器器件(诸如NAND器件)的3D存储器单元的氧化物/多晶硅(OP)堆叠的方法。所述方法一般包括在PECVD工艺期间用前驱物处理氧化物和/或多晶硅材料，以降低所述氧化物的介电常数并降低所述多晶硅的电阻率。在一个实施例中，用八甲基环四硅氧烷(OMCTS)前驱物处理所述氧化物材料。在另一个实施例中，将锗烷(GeH4)引入PECVD工艺以形成具有掺杂剂的SixGe(1-x)膜。在又一个实施例中，使用等离子体处理工艺来氮化所述OP堆叠的层之间的界面。所述前驱物和等离子体处理可以单独地使用或以任何组合使用，以产生具有低介电常数氧化物和低电阻率多晶硅的OP堆叠。
在一个实施例中，描述了一种存储器单元制造方法。所述方法包括：将基板定位在PECVD腔室中；将八甲基环四硅氧烷前驱物引入所述PECVD腔室以在所述基板上方沉积氧化硅层；以及在所述氧化硅层上方沉积多晶硅层。
在另一个实施例中，描述了一种存储器单元制造方法。所述方法包括：将基板定位在PECVD腔室中；在基板上方沉积氧化硅层；以及将硅前驱物和锗烷引入所述PECVD腔室以在所述氧化硅层上方形成SixGe(1-x)膜。
在又一个实施例中，描述了一种存储器器件。所述存储器器件包括：基板；氧化硅层，所述氧化硅层设置在所述基板上方，所述氧化硅层具有在约2.5与约3.2之间的介电常数；以及多晶硅层，所述多晶硅层设置在所述氧化硅层上方。
附图说明
因此，为了能够详细地理解本公开的上述特征的方式，可以通过参考实施例获得上面简要地概述的本公开的更具体的描述，实施例中的一些在附图中示出。然而，应当注意，附图仅示出了本公开的典型实施例，并且因此不应视为对范围的限制，因为本公开可以允许其它等效实施例。
图1是根据本公开的实施例的存储器器件的横截面视图。
图2是根据本公开的实施例的概述方法的流程图。
图3是根据本公开的实施例的概述方法的流程图。
为了便于理解，尽可能地使用相同的附图标记来表示各图共有的相同元件。另外，一个实施例的元件可以有利地适于本文所述的其它实施例。
具体实施方式
本文所述的实施例大体涉及制造用于存储器器件(诸如NAND器件)的3D存储器单元的氧化物/多晶硅(OP)堆叠的方法。所述方法一般包括在PECVD工艺期间用前驱物处理氧化物和/或多晶硅材料，以降低所述氧化物的介电常数并降低所述多晶硅的电阻率。在一个诸如NAND器件中，用八甲基环四硅氧烷(OMCTS)前驱物处理所述氧化物材料。在另一个实施例中，将锗烷(GeH4)引入PECVD工艺以形成具有掺杂剂的SixGe(1-x)膜。在又一个实施例中，使用等离子体处理工艺来氮化所述OP堆叠的层之间的界面。所述前驱物和等离子体处理可以单独地使用或以任何组合使用，以产生具有低介电常数氧化物和低电阻率多晶硅的OP堆叠。本公开构想了OP堆叠存储器器件作为示例；然而，其它存储器堆叠也受益于本文所述的方法。
图1是根据本公开的实施例的存储器器件100。存储器器件100包括基板102，基板102上具有多个第一材料层104和多个第二材料层106。多个第一材料层104和多个第二材料层106构成存储器堆叠108。在OP堆叠存储器器件的实施例中，第一材料层104中的每个一般是氧化硅层(O层)，并且第二材料层106中的每个一般是非晶硅层，其在退火工艺之后形成多晶硅层(P层)。虽然图1描绘了第二材料层106沉积在第一材料层104上方，但是沉积次序可以颠倒，使得第一材料层104(O层)沉积在第二材料层106(P层)上方。
虽然如图所示的存储器器件100包括三个第一材料层104和三个第二材料层106，但是第一材料层104和第二材料层106的数量一般是层的任何合适数量，这取决于制造的存储器器件。例如，存储器器件通常包括8x、16x、24x甚至更高的堆叠数量。
在存储器器件100是NAND闪存存储器单元的实施例中，存储器器件100进一步包括设置在基板102的第一表面的相对端上的源极和漏极。为了用作闪存存储器，多个NAND闪存单元一般与共用源极或漏极的相邻单元串联连接，并且每个单元连接到位线和字线。在操作中，每个单元可以在其中存储数据，诸如“0”或“1”。
制造如下的存储器器件(诸如存储器器件100)的方法，一般是可用于在相对低的温度下形成硅膜的等离子体增强化学气相沉积(PECVD)工艺的一部分。该方法可以在任何合适的PECVD腔室(诸如可从加利福尼亚州圣克拉拉市应用材料公司(Applied Materials,Inc.Santa Clara,California)获得的PECVD腔室)中执行。
图2描绘了概述制造存储器器件(诸如存储器器件100)的方法200的流程图。方法200在操作210处由将基板102定位在PECVD腔室中开始。在操作220处，通过将OMCTS前驱物引入PECVD腔室来在基板102上方沉积第一材料层104或氧化硅层。OMCTS前驱物的化学结构在下面示出为结构1。在一个实施例中，第一材料层104沉积在基板102上并与基板102接触。
(结构1)
如结构1所示，OMCTS分子是除甲基(CH3)基团之外还具有氧化硅(Si-O)环状键合的化学结构。常规沉积的氧化硅层具有约3.9的介电常数。根据本公开的实施例，来自上述OMCTS前驱物的引入的碳(C)一般将氧化硅层的介电常数从其约3.9的当前值降低到约2.5与约3.2之间，例如，在约2.8与约3.0之间。另外，沉积的氧化硅层通过Si-O环状结构具有增加的氧化物质量。
调整PECVD工艺的处理条件将使OMCTS前驱物的C-H键断裂。例如，使等离子体密度在将OMCTS前驱物引入PECVD腔室期间从约25.56兆赫(MHz)增加到约27MHz会使前驱物的C-H键断裂。另外地或替代地，方法300还包括用约300kHz与约400kHz之间(诸如约350kHz)的射频(RF频率)轰击氧化硅层，以使OMCTS前驱物的C-H键断裂。
在操作230处，在第一材料层104或氧化硅层上方沉积第二材料层106或多晶硅层。可以通过任何合适的沉积装置沉积第二材料层106。通常，除了掺杂剂前驱物(包括但不限于磷烷(PH3)和乙硼烷(B2H6))之外，通过引入前驱物(包括但不限于硅烷(SiH4)、氩(Ar)和氦(He))来沉积非晶硅。在退火工艺(诸如热退火)之后，非晶硅变成多晶硅。在一个实施例中，第二材料层106沉积在第一材料层104上并与第一材料层104接触。
任选地重复操作220和230以形成具有任何数量的第一材料层104和任何数量的第二材料层106的OP堆叠。
图3描绘了概述制造存储器器件100的方法300的流程图。方法300在操作310处由将基板102定位在PECVD腔室中开始。在操作320处，在基板102上方沉积第一材料层104或氧化硅层。通常通过任何合适的沉积工艺沉积氧化硅层，诸如在方法200的操作220中描述的工艺。在一个实施例中，第一材料层104沉积在基板102上并与基板102接触。
在操作330处，在第一材料层104上方沉积第二材料层106或多晶硅层。更具体地，通过引入至少一种硅前驱物(包括但不限于硅烷(SiH4))和锗烷(GeH4)前驱物以形成其中有掺杂剂的SixGe(1-x)膜来沉积多晶硅层，其具有高迁移率和低电阻率。合适的掺杂剂的示例是磷烷(PH3)。可以在PECVD工艺期间的任何合适的时间引入GeH4前驱物。在一个实施例中，在PECVD腔室中产生等离子体之前引入GeH4。
沉积的多晶硅具有高迁移率和降低的电阻率，具有相同或基本上类似的载流子浓度。常规沉积的n型多晶硅(具有磷(P)掺杂的)具有约1×10-3ohm*cm的电阻率，并且常规沉积的p型多晶硅具有约3×10-3ohm*cm的电阻率。GeH4前驱物的引入将n型多晶硅膜的电阻率降低到约0.5×10-3ohm*cm，并且将p型多晶硅膜的电阻率降低到约1.5×10-3ohm*cm。
任选地重复操作320和330以形成具有任何数量的第一材料层104和任何数量的第二材料层106的OP堆叠。
另外地或替代地，本文所述的方法可以包括在第一材料层104或氧化硅层与第二材料层106或多晶硅层之间的界面处的等离子体处理。更具体地，氧化硅层中的每个与多晶硅层之间的界面可以经过等离子体处理以氮化和改善OP堆叠的层之间的粘附性。例如，可以在PECVD腔室中产生氨(NH3)/氮(N2)等离子体以氮化和改善氧化硅与多晶硅层之间的界面处的粘附性。
方法200和方法300的操作可以以任何组合使用。在另一个实施例中，通过引入OMCTS前驱物在基板102上方沉积第一材料层104或氧化硅层，并且通过引入至少一种硅前驱物(包括但不限于SiH4)和锗烷(GeH4)前驱物以形成具有掺杂剂的SixGe(1-x)膜来沉积第二材料层106。重复这些操作以形成具有任何合适数量的层的存储器器件。
本文所述的方法提供了具有低介电常数氧化物和低电阻率多晶硅而具有减小的厚度的改善的存储器器件，这改善了整体器件的可扩展性，同时保持整体存储器器件几何结构的继续缩小。
虽然前述内容针对本公开的实施例，但是可以在不脱离本公开的基本范围的情况下设计本公开的其它和进一步的实施例，并且本公开的范围由所附权利要求书确定。

Claims (18)

1.一种制造存储器器件堆叠的方法，包括：
将基板定位在PECVD腔室中；
将八甲基环四硅氧烷前驱物引入所述PECVD腔室以在所述基板上方沉积氧化硅层；
以300kHz与400kHz之间的RF频率轰击所述氧化硅层；以及
在所述氧化硅层上方沉积多晶硅层。
2.如权利要求1所述的方法，其中在所述氧化硅层上方沉积多晶硅层包括：
将硅烷和锗烷引入所述PECVD腔室以沉积所述多晶硅层。
3.如权利要求1所述的方法，其中所述将八甲基环四硅氧烷前驱物引入所述PECVD腔室以在所述基板上方沉积所述氧化硅层在约27兆赫的等离子体密度下发生。
4.如权利要求1所述的方法，进一步包括：
等离子体处理所述氧化硅层与所述多晶硅层之间的界面，其中所述等离子体处理包括将NH3和/或N2引入所述PECVD腔室。
5. 如权利要求1所述的方法，其中在所述氧化硅层上方沉积所述多晶硅层包括：
将选自由硅烷、氩和氦组成的组的一种或多种前驱物和选自由磷烷和乙硼烷组成的组的一种或多种掺杂剂前驱物引入所述PECVD腔室以在所述氧化硅层上方沉积非晶硅层；以及
将所述非晶硅层退火以形成所述多晶硅层。
6.如权利要求1所述的方法，其中在所述氧化硅层上方沉积所述多晶硅层包括：
将选自由硅烷组成的组的至少一种硅前驱物和锗烷引入所述PECVD腔室以形成SixGe(1-x)膜。
7.一种制造存储器器件堆叠的方法，包括：
将基板定位在PECVD腔室中；
将OMCTS前驱物引入所述PECVD腔室以在所述基板上方沉积氧化硅层；
以300kHz与400kHz之间的RF频率轰击所述氧化硅层；以及
将硅前驱物和锗烷引入所述PECVD腔室以在所述氧化硅层上方形成SixGe(1-x)膜。
8.一种存储器器件，包括：
基板；
氧化硅层，通过引入OMCTS前驱物来将所述氧化硅层设置在所述基板上方并且由300kHz与400kHz之间的RF频率轰击所述氧化硅层，所述氧化硅层具有在2.5与3.2之间的介电常数；以及
多晶硅层，所述多晶硅层设置在所述氧化硅层上方。
9.如权利要求8所述的存储器器件，其中所述氧化硅层具有在2.8与3.0之间的介电常数。
10.如权利要求8所述的存储器器件，其中所述氧化硅层沉积在所述基板上并与所述基板接触，并且其中所述多晶硅层沉积在所述氧化硅层上并与所述氧化硅层接触。
11. 如权利要求8所述的存储器器件，其中所述多晶硅层为n型多晶硅层，并且其中所述n型多晶硅层具有小于约0.5×10-3 ohm*cm的电阻率。
12. 如权利要求8所述的存储器器件，其中所述多晶硅层为p型多晶硅层，并且其中所述p型多晶硅层具有小于约1.5×10-3 ohm*cm的电阻率。
13.如权利要求7所述的方法，进一步包括：
将所述SixGe(1-x)膜退火以在所述氧化硅层上方形成多晶硅层。
14.如权利要求13所述的方法，进一步包括：
等离子体处理所述氧化硅层与所述多晶硅层之间的界面，其中，所述等离子体处理包括将NH3和/或N2引入所述PECVD腔室。
15.如权利要求7所述的方法，进一步包括：
在所述PECVD腔室中产生等离子体。
16.如权利要求15所述的方法，其中，将所述硅前驱物和锗烷引入所述PECVD腔室发生于在所述PECVD腔室中产生所述等离子体之前。
17.如权利要求7所述的方法，其中，所述SixGe(1-x)膜是经掺杂的。
18.如权利要求17所述的方法，其中，以磷烷掺杂所述SixGe(1-x)膜。
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