CN105448999B - 多晶硅薄膜晶体管元件及其制作方法 - Google Patents

多晶硅薄膜晶体管元件及其制作方法 Download PDF

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CN105448999B
CN105448999B CN201510872131.3A CN201510872131A CN105448999B CN 105448999 B CN105448999 B CN 105448999B CN 201510872131 A CN201510872131 A CN 201510872131A CN 105448999 B CN105448999 B CN 105448999B
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buffer layer
admixture
polycrystalline sitft
substrate
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CN105448999A (zh
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萧翔允
陈佳楷
林世亮
许庭毓
王培筠
黄雅琴
江丞伟
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AU Optronics Corp
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Abstract

一种制作多晶硅薄膜晶体管元件的方法，包括下列步骤。提供基板，并形成具有多个掺质的缓冲层于基板上。形成非晶硅层于具有掺质的缓冲层上。进行热制程，将非晶硅层多晶化以转换成多晶硅层，并同时将缓冲层内的一部分的掺质向外扩散至多晶硅层内以调整起始电压。图案化多晶硅层，以形成有源层。形成栅极绝缘层于有源层上。形成栅极于栅极绝缘层上。形成源极掺杂区与漏极掺杂区于有源层内。

Description

多晶硅薄膜晶体管元件及其制作方法
【技术领域】
本发明是关于一种多晶硅薄膜晶体管元件及其制作方法，尤指一种具有高电子迁移率(mobility)的多晶硅薄膜晶体管元件及其制作方法。
【背景技术】
低温多晶硅(low temperature polycrystalline silicon,LTPS)薄膜晶体管元件由于具有较高电子迁移率(mobility)的特性，因此理论上具有较非晶硅(amorphoussilicon)薄膜晶体管元件更佳的电性表现。然而，由于低温多晶硅薄膜晶体管元件的制程较为复杂，其相较于非晶硅薄膜晶体管元件而要更多道的光刻暨蚀刻(photolithographyand etching,PEP)制程，因此不仅制作成本较高，且良率也会下降。
【发明内容】
本发明的目的的一在于提供一种多晶硅薄膜晶体管元件及其制作方法，以简化制程步骤及制作成本并提升电子迁移率与元件特性。
本发明的一实施例提供一种制作多晶硅薄膜晶体管元件的方法，包括下列步骤。提供基板，并形成具有多个掺质的缓冲层于基板上。形成非晶硅层于具有掺质的缓冲层上。进行热制程，将非晶硅层多晶化以转换成多晶硅层，并同时将缓冲层内的一部分的掺质向外扩散至多晶硅层内以调整起始电压。图案化多晶硅层，以形成有源层。形成栅极绝缘层于有源层上。形成栅极于栅极绝缘层上。形成源极掺杂区与漏极掺杂区于有源层内。
本发明的另一实施例提供一种多晶硅薄膜晶体管元件，设置于基板上。多晶硅薄膜晶体管元件包括缓冲层、多晶硅层、栅极绝缘层与栅极。缓冲层设置于基板上，且缓冲层内具有多个掺质。多晶硅层设置于缓冲层上，其中，多晶硅层包括通道、源极掺杂区以及漏极掺杂区，且源极掺杂区与漏极掺杂区分别位于通道的两侧。栅极绝缘层设置于多晶硅层上。栅极设置于栅极绝缘层上并对应于多晶硅层的通道。
【附图说明】
图1绘示了本发明的制作多晶硅薄膜晶体管元件的方法流程图。
图2至图8绘示了本发明的第一实施例的制作多晶硅薄膜晶体管元件的方法示意图。
图9绘示本发明的一实施例的制作显示面板的示意图。
图10与图11绘示了本发明的第二实施例的制作多晶硅薄膜晶体管元件的方法示意图。
图12绘示对照实施例的多晶硅薄膜晶体管元件的漏极电流-栅极电压关系图及电子迁移率-栅极电压关系图。
图13绘示本发明的第一样本的多晶硅薄膜晶体管元件的漏极电流-栅极电压关系图及电子迁移率-栅极电压关系图。
图14绘示本发明的第二样本的多晶硅薄膜晶体管元件的漏极电流-栅极电压关系图及电子迁移率-栅极电压关系图。
【符号说明】
1,2 多晶硅薄膜晶体管元件 30 基板
32 缓冲层 32B 底缓冲层
32B1 第一底缓冲层 32B2 第二底缓冲层
32B3 第三底缓冲层 32T 顶缓冲层
34 掺质 37 激光光束
36 非晶硅层 38 多晶硅层
381 有源层 38C 通道
38S 源极掺杂区 38D 漏极掺杂区
38L 轻掺杂区 40 栅极绝缘层
42G 栅极 44 层间介电层
441 第一层间介电层 442 第二层间介电层
46S 源极电极 46D 漏极电极
48 保护层 PE 像素电极
50 基板 CE 共通电极
52 显示介质层 100 显示面板
【具体实施方式】
为使熟悉本发明所属技术领域的一般技艺者能更进一步了解本发明，下文特列举本发明的较佳实施例，并配合所附图式，详细说明本发明的构成内容及所欲达成的功效。
请参考图1。图1绘示了本发明的制作多晶硅薄膜晶体管元件的方法流程图。如图1所示，本发明的制作多晶硅薄膜晶体管元件的方法包括下列步骤。
步骤10：提供基板。
步骤12：形成具有多个掺质的缓冲层于基板上。
步骤14：形成非晶硅层于具有掺质的缓冲层上。
步骤16：进行热制程，将非晶硅层多晶化以转换成多晶硅层，并同时将缓冲层内的一部分的掺质向外扩散至多晶硅层内以调整起始电压。
步骤18：图案化多晶硅层以形成有源层。
步骤20：形成栅极绝缘层于有源层上。
步骤22：形成栅极于栅极绝缘层上。
步骤24：形成源极掺杂区与漏极掺杂区于有源层内。
请继续参考图2至图8，并一并参考图1。图2至图8绘示了本发明的第一实施例的制作多晶硅薄膜晶体管元件的方法示意图。如图2所示，首先提供基板30。基板30可包括透明基板例如玻璃基板、塑胶基板、石英基板、蓝宝石基板或其它适合基板，且基板30可选用硬质基板或可挠式基板。接着，形成具有多个掺质34的缓冲层32于基板30上。在本实施例中，缓冲层32为单层结构缓冲层，且其材料可包括无机绝缘材料例如氧化硅，但不以此为限。缓冲层32的材料也可包括氮化硅、氮氧化硅或其它适合的无机或有机绝缘材料。在其它实施例中，缓冲层32可为多层堆叠结构缓冲层。缓冲层32可利用沉积制程例如化学气相沉积(CVD)制程、物理气相沉积(PVD)或其它适合的沉积制程形成。此外，本实施例的方法可包括于形成缓冲层32的沉积制程中同时通入包含掺质34的气体，以于缓冲层32内形成掺质34，也就是说，缓冲层32与掺质34可于同一反应室内一并形成。缓冲层32内的掺质34可包括P型掺质例如硼离子或N型掺质例如磷离子，在此状况下，通入反应室的气体可为包含硼离子或磷离子的气体，但不以此为限。此外，在一变化实施例中，缓冲层32与掺质34钆可分别加以制作，亦即可先进行沉积制程以于基板30上沉积缓冲层32，接着再进行离子布植制程以于缓冲层32内形成掺质34。在本实施例中，缓冲层32内的掺质34的掺杂浓度例如可介于8x1014至4x1015atom/cm3之间，但不以此为限。掺质34的掺杂浓度可视多晶硅薄膜晶体管元件的起始电压规格与热制程的不同而加以变更。此外，掺质34在缓冲层32内可为均匀分布、或大部分分布在靠近缓冲层32的表面的区域，或为梯度分布。
如图3所示，接着形成非晶硅层36于具有掺质34的缓冲层32上。非晶硅层36可利用沉积制程例如化学气相沉积(CVD)制程、等离子增强化学气相沉积(PECVD)制程或其它适合的沉积制程形成。
如图4所示，随后进行热制程，将非晶硅层36多晶化以转换成多晶硅层38，并同时将缓冲层32内的一部分的掺质34向外扩散至多晶硅层38内以调整起始电压。本实施例的方法可为制作低温多晶硅薄膜晶体管元件的方法，其中，热制程可包括准分子激光退火(Excimer Laser Annealing,ELA)制程，其利用激光光束37以扫描方式依序对不同位置的非晶硅层36进行多晶化，以使非晶硅重新排列成多晶硅。在一变化实施例中，热制程也可包括固相结晶化(Solid Phase Crystallization,SPC)制程或其它适合的热制程。在准分子激光退火制程中，缓冲层32也会受到激光光束37的照射而受热而使得一部分的掺质34扩散至多晶硅层38内而使得多晶硅层38形成掺杂，达到调整起始电压的作用。值得说明的是，当缓冲层32内的掺质34扩散至多晶硅层38时，缓冲层32可能具有粗糙表面，且缓冲层32会形成多孔(porous)缓冲层，其中，此时，热制程后的缓冲层32的掺质34的掺杂浓度会小于热制程前的缓冲层32的掺质34的掺杂浓度。在此状况下，在经过激光光束37的照射后，热能会蓄积在缓冲层32的粗糙表面与孔洞内而使得多晶硅层38内的多晶硅的晶界尺寸(grainboundary size)加大(即多晶硅的管芯变大)而可优化晶种成长。也就是说，本实施例的热制程可以同时对非晶硅层36进行多晶化，以及一并对多晶硅层38进行掺杂以调整起始电压。此外，相较于分别利用离子布植制程直接对多晶硅层38进行掺杂的方式以及利用热制程对非晶硅层36进行多晶化的方式，本实施例利用缓冲层32内的掺质34对多晶硅层38进行掺杂的作法不仅只需要一道热制程即可达到调整起起电压及多晶化的作用，且缓冲层32内的孔洞更可发挥蓄积热能的作用使得多晶硅层38内的多晶硅的晶界尺寸加大而可优化晶种成长，而可有助于提升电子迁移率。
另外，为了进一步改善准分子激光退火制程的结晶化能力，本实施例的缓冲层32的厚度与折射率以及准分子激光的波长之间可以符合下式(1)的关系。
2nd＝mλ (1)
其中n是缓冲层32的折射率，d是缓冲层32的厚度，λ是准分子激光的波长，m为正整数。
在符合上述式(1)的条件下，准分子激光可以在缓冲层32内产生共振而放大能量，借此可以改善多晶硅的结晶状况并加大晶界尺寸，进而提升电子迁移率与元件特性。
值得说明的是于进行热制程之前，本实施例的方法可选择性地先对非晶硅层36进行去氢(dehydrogenation)制程，且在去氢制程时可同时将缓冲层32内的一部分的掺质34扩散至非晶硅层36内。
如图5所示，接着对多晶硅层38进行图案化，移除一部分的多晶硅层38以形成有源层381。上述图案化制程可为光刻暨蚀刻制程，但不以此为限。
如图6所示，于有源层381中形成通道38C、源极掺杂区38S与漏极掺杂区38D，其中，源极掺杂区38S与漏极掺杂区38D分别位于通道38C的两侧。此外，可选择性地于通道38C与源极掺杂区38S之间以及通道38C与漏极掺杂区38D之间分别形成轻掺杂区38L，其中，源极掺杂区38S与漏极掺杂区38D的掺杂浓度大于轻掺杂区38L的掺杂浓度，且通道38C的掺杂浓度小于源极掺杂区38S、漏极掺杂区38D与轻掺杂区38L。
在本实施例中，源极掺杂区38S、漏极掺杂区38D与轻掺杂区38L可利用离子布植制程并搭配遮罩(图未示)例如光阻图案形成。举例而言，可先于有源层381的表面形成光阻图案，其中，光阻图案覆盖通道38C及预定形成轻掺杂区38L的区域并暴露出预定形成源极掺杂区38S与漏极掺杂区38D的区域。接着，利用光阻图案作为遮罩对暴露出的有源层381进行离子布植制程以形成源极掺杂区38S与漏极掺杂区38D。随后，移除一部分的光阻图案例如利用灰化制程以进一步暴露出预定形成轻掺杂区38L的区域，并再利用缩减后光阻图案作为遮罩再进行离子布植制程以形成轻掺杂区38L。最后，移除剩余的光阻图案。本发明的源极掺杂区38S与漏极掺杂区38D以及轻掺杂区38L的制作方式不以上述实施例为限。在变化实施例中，源极掺杂区38S与漏极掺杂区38D可利用一离子布植制程并搭配一遮罩形成，而轻掺杂区38L可利用另一离子布植制程并搭配另一遮罩。或者，源极掺杂区38S与漏极掺杂区38D以及轻掺杂区38L可利用后续形成的栅极作为遮罩加以制作。之后，本实施例的方法可包括对多晶硅层38进行氢化制程，以修补多晶硅层38的缺陷。此外，本实施例的方法也可包括可对源极掺杂区38S与漏极掺杂区38D进行活化制程，例如热退火制程或激光退火制程，以降低源极掺杂区38S与漏极掺杂区38D的阻值。
如图7所示，接着形成栅极绝缘层40于有源层381上。栅极绝缘层40的材料可为无机材料例如氧化硅、氮化硅或氮氧化硅，但不以此为限。随后，形成栅极42G于栅极绝缘层40上，其中，栅极42G与通道38C在垂直投影方向上重叠。在本实施例中，栅极42G的材料可包括金属或合金，例如金、银、铜、铝、钛、钼等金属或其合金，或其它适合的导电材料。
如图8所示，接着形成层间介电层44于栅极42G上，并对层间介电层44与栅极绝缘层40进行图案化以暴露出源极掺杂区38S与漏极掺杂区38D。上述图案化制程可为光刻暨蚀刻制程，但不以此为限。在本实施例中，层间介电层44可为多重堆叠结构层间介电层，其可包括例如第一层间介电层441位于栅极42G上，以及第二层间介电层442堆叠于第一层间介电层441上，其中，第一层间介电层441可为无机介电层，例如氧化硅层、氮化硅层或氮氧化硅层，但不以此为限；第二层间介电层442可为有机介电层，但不以此为限。在变化实施例中，层间介电层44亦可为单层结构层。随后，形成源极电极46S与漏极电极46D于层间介电层44上，其中，源极电极46S与源极掺杂区38S电性连接，且漏极电极46D与漏极掺杂区38D电性连接。源极电极46S与漏极电极46D的材料可包括金属或合金，例如金、银、铜、铝、钛、钼等金属或其合金，或其它适合的导电材料。至此，可制作出本实施例的多晶硅薄膜晶体管元件1。本实施例中的层间介电层44可为多重堆叠结构设计，可增加激光退火制程中共振的效果，可使晶界尺寸加大而可优化晶种成长，进而提升电子迁移率与元件特性。
本实施例的多晶硅薄膜晶体管元件1可应用于显示面板例如液晶显示面板、电激发光显示板或其它各种类型的显示面板、触控面板或任何电子装置或光电装置上，作为开关元件或驱动元件的用。请接续图8参考图9。图9绘示本发明的一实施例的制作显示面板的示意图。如图9所示，接着依序形成一保护层48与一像素电极PE于多晶硅薄膜晶体管元件1上，其中，保护层48可部分暴露出漏极电极46D，而像素电极PE与漏极电极46D电性连接。接着，提供另一基板50，并于基板50上形成共通电极CE。接着，将基板30与基板50结合，并于基板30与基板50之间形成显示介质层52，以形成本实施例的显示面板100。本实施例显示面板100是以液晶显示面板为例，因此显示介质层52可包括液晶层，但不以此为限。在变化实施例中，显示面板也可是电激发光显示面板例如有机发光二极管显示面板，而显示介质层52可为电激发光层或其它适合的非自发光显示介质层或自发光显示介质层。本实施例的显示面板1是垂直电场驱动型液晶显示面板为例，例如向列扭转型(TN)液晶显示面板或垂直配向型(VA)液晶显示面板，但不以此为限。举例而言，本发明的显示面板也可为水平电场驱动型液晶显示面板例如平面切换型(IPS)液晶显示面板、边缘电场切换(FFS)液晶显示面板或其它型式的显示面板。在一变化实施例中，共通电极CE也可形成于基板30上并与像素电极PE位于同一平面上，作为平面电场切换型(IPS)液晶显示面板的应用。在另一变化实施例中，共通电极CE也可形成于基板30上但与像素电极PE位于不同平面上，作为边缘电场切换型(FFS)液晶显示面板的应用。
由上述可知，本发明的制作多晶硅薄膜晶体管元件的方法利用单一道热制程即可将非晶硅层转换成多晶硅层，并同时将缓冲层内的掺质扩散至多晶硅层内而调整起始电压，因此可简化制程步骤及制作成本。此外，当缓冲层内的掺质扩散至多晶硅层时，缓冲层会形成多孔缓冲层，因此在热制程中热能可蓄积在孔洞内而使得多晶硅层内的多晶硅的晶界尺寸加大而可优化晶种成长，进而提升电子迁移率与元件特性。
本发明的多晶硅薄膜晶体管元件及其制作方法并不以上述实施例为限。下文将依序介绍本发明的其它较佳实施例的多晶硅薄膜晶体管元件及其制作方法，且为了便于比较各实施例的相异处并简化说明，在下文的各实施例中使用相同的符号标注相同的元件，且主要针对各实施例的相异处进行说明，而不再对重复部分进行赘述。
请继续参考图10与图11，并一并参考图1。图10与图11绘示了本发明的第二实施例的制作多晶硅薄膜晶体管元件的方法示意图。如图10所示，在本实施例中，缓冲层32为多层堆叠结构缓冲层，其包括至少一底缓冲层32B位于基板30上，以及一顶缓冲层32T位于底缓冲层32B上。举例而言，本实施例的缓冲层32的底缓冲层32B可包括第一底缓冲层32B1、第二底缓冲层32B2以及第三底缓冲层32B3，依序形成于基板30上，而顶缓冲层32T可形成于第三底缓冲层32B3上。在本实施例中，第一底缓冲层32B1、第二底缓冲层32B2、第三底缓冲层32B3与顶缓冲层32T可为依序堆叠的不同材料膜层，例如第一底缓冲层32B1与第三底缓冲层32B3的材料可为氮化硅，而第二底缓冲层32B2与顶缓冲层32T的材料可为氧化硅，借此可增加与基板30的附着力并减少应力。另外，第一底缓冲层32B1、第二底缓冲层32B2、第三底缓冲层32B3与顶缓冲层32T的厚度可视附着力、应力与其它考量加以调整。在一实施样态中，第二底缓冲层32B2与顶缓冲层32T的厚度可大于第一底缓冲层32B1与第三底缓冲层32B3的厚度，例如第二底缓冲层32B2或顶缓冲层32T的厚度可为第一底缓冲层32B1或第三底缓冲层32B3的厚度的数倍，但不以此为限。
在本实施例中，掺质34可仅形成于多层堆叠结构缓冲层的顶缓冲层32T内，其中，于顶缓冲层32T内形成掺质34的方式可如前述实施例所述，例如形成顶缓冲层32T的沉积制程中同时通入包含掺质34的气体，以于顶缓冲层32T内形成掺质34，而底缓冲层32B内不形成掺质34；或是先形成顶缓冲层32T，接着再进行离子布植制程以于顶缓冲层32T内形成掺质34，而底缓冲层32B内不形成掺质34。在一变化实施例中，掺质34除了形成于顶缓冲层32T内，也可形成于底缓冲层32B内。
如图11所示，接着进行如第一实施例的图3至图8的制程，即可制作出本实施例的多晶硅薄膜晶体管元件2。
本实施例的多晶硅薄膜晶体管元件2可应用于显示面板例如液晶显示面板、电激发光显示板或其它各种类型的显示面板、触控面板或任何电子装置或光电装置上，作为开关元件或驱动元件的用，如上述实施例所示，在此不再赘述。
请参考图12至图14。图12绘示对照实施例的多晶硅薄膜晶体管元件的漏极电流-栅极电压关系图及电子迁移率-栅极电压关系图，图13绘示本发明的第一样本的多晶硅薄膜晶体管元件的漏极电流-栅极电压关系图及电子迁移率-栅极电压关系图，且图14绘示本发明的第二样本的多晶硅薄膜晶体管元件的漏极电流-栅极电压关系图及电子迁移率-栅极电压关系图。在对照实施例(图12)的方法中，多晶硅薄膜晶体管元件是利用离子布植制程直接对多晶硅层进行起始电压的调整，而缓冲层内没有掺质，并分别在漏极电压Vd为0.1V,5.1V,10.1V的条件下进行测试；本发明(第13与14图)的方法是先对缓冲层进行离子布植制程，再借由热制程同时进行多晶化并一并将掺质扩散至多晶硅薄膜晶体管元件的多晶硅层内，并分别在漏极电压Vd为0.1V,5.1V,10.1V的条件下进行测试，其中，图13的第一样本的离子布植制程的能量为60kev，掺质为硼离子，且掺杂浓度为5*1013atoms/cm3；图14的第二样本的离子布植制程的能量为60kev，掺质为磷离子，且掺杂浓度为2*1014atoms/cm3。如图12所示，对照实施例的多晶硅薄膜晶体管元件的起始电压(Vth)约为-2.71V。相较的下，如图13所示，第一样本的多晶硅薄膜晶体管元件的起始电压(Vth)约为-1.17V；如图14所示，第二样本的多晶硅薄膜晶体管元件的起始电压(Vth)约为-2.02V。由上述实验数据可知，借由在缓冲层内先形成掺质再借由热制程同时进行多晶化并一并将掺质扩散至多晶硅薄膜晶体管元件的多晶硅层内的作法确实可以有效将起始电压调整至预定的区间内。
另外，本发明针对多晶硅层的晶界尺寸所作的实验亦显示了借由在缓冲层内先形成掺质再借由热制程同时进行多晶化并一并将掺质扩散至多晶硅薄膜晶体管元件的多晶硅层内的作法可以有效增大晶界尺寸(即增大管芯尺寸)。请参考表1，表1列示了对照实施例与本发明的一实施例的晶界尺寸，其中，对照实施例是在缓冲层内没有掺质的条件下所实际量测出的晶界尺寸，而本实施例是在缓冲层内掺杂有氩(Ar)离子的条件下实际量测出的晶界尺寸。
表1
对照实施例 本实施例
晶界尺寸(grain boundary size) 0.3098微米 0.3432微米
由表1的结果可知，在缓冲层内没有掺质的条件下，对照实施例的晶界尺寸约为0.3098微米，而在缓冲层中形成掺质的条件下，本实施例的晶界尺寸约为0.3432微米，其晶界尺寸增加了约10.81％。
综上所述，本发明的制作多晶硅薄膜晶体管元件的方法利用单一道热制程即可将非晶硅层转换成多晶硅层，并一并将缓冲层内的掺质扩散至多晶硅层内而调整起始电压至预定区间，因此可简化制程步骤及制作成本。此外，当缓冲层内的掺质扩散至多晶硅层时，缓冲层会形成多孔缓冲层，因此在热制程中热能可蓄积在孔洞内而使得多晶硅层内的多晶硅的晶界尺寸加大而可优化晶种成长，进而提升电子迁移率与元件特性。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (17)

1.一种制作多晶硅薄膜晶体管元件的方法，其特征在于，包括：
提供一基板；
形成一具有多个掺质(dopant)的缓冲层于该基板上；
形成一非晶硅层于具有该多个掺质的该缓冲层上；
进行一热制程，将该非晶硅层多晶化以转换成一多晶硅层，并同时将该缓冲层内的一部分的该多个掺质向外扩散至该多晶硅层内以调整起始电压(threshold voltage)；
图案化该多晶硅层，以形成一有源层；
形成一栅极绝缘层于该有源层上；
形成一栅极于该栅极绝缘层上；以及
形成一源极掺杂区与一漏极掺杂区于该有源层内；其中，该缓冲层内的该多个掺质包括P型掺质或N型掺质。
2.如权利要求1所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，该缓冲层是为一单层结构缓冲层。
3.如权利要求2所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，于进行该热制程之前，该多个掺质是位于该单层结构缓冲层内。
4.如权利要求1所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，该缓冲层是为一多层堆叠结构缓冲层，其包括至少一底缓冲层位于该基板上以及一顶缓冲层位于该至少一底缓冲层上。
5.如权利要求4所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，于进行该热制程之前，该多个掺质是位于该多层堆叠结构缓冲层的该顶缓冲层内。
6.如权利要求1所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，于该基板上形成具有该多个掺质的缓冲层的步骤包括：
进行一沉积制程以于该基板上沉积该缓冲层，并于该沉积制程中同时通入包含该多个掺质的气体，以于该缓冲层内形成该多个掺质。
7.如权利要求1所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，于该基板上形成具有该多个掺质的缓冲层的步骤包括：
进行一沉积制程以于该基板上沉积该缓冲层；以及
进行一离子布植制程以于该缓冲层内形成该多个掺质。
8.如权利要求1所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，该热制程包括一准分子激光退火(Excimer Laser Annealing,ELA)制程。
9.如权利要求1所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，该热制程包括固相结晶化(Solid Phase Crystallization,SPC)制程。
10.如权利要求1所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，另包括于进行该热制程之前，先对该非晶硅层进行一去氢(dehydrogenation)制程，并同时进一步将该缓冲层内的一部分的该多个掺质扩散至该非晶硅层内。
11.如权利要求1所述的制作多晶硅薄膜晶体管元件的方法，其特征在于，另包括：
形成一层间介电层于该栅极上；以及
形成一源极电极与一漏极电极于该层间介电层上，其中该源极电极与该源极掺杂区电性连接，且该漏极电极与该漏极掺杂区电性连接。
12.一种多晶硅薄膜晶体管元件，设置于一基板上，其特征在于，该多晶硅薄膜晶体管元件包括：
一缓冲层，设置于该基板上，其中该缓冲层内具有多个掺质(dopant)；
一多晶硅层，设置于该缓冲层上，其中该多晶硅层包括一通道、一源极掺杂区以及一漏极掺杂区，且该源极掺杂区与该漏极掺杂区分别位于该通道的两侧；
一栅极绝缘层，设置于该多晶硅层上；以及
一栅极，设置于该栅极绝缘层上并对应于该多晶硅层的该通道；其中，该缓冲层内的该多个掺质包括P型掺质或N型掺质。
13.如权利要求12所述的多晶硅薄膜晶体管元件，其特征在于，该缓冲层是为一单层结构缓冲层，且该多个掺质是位于该单层结构缓冲层内。
14.如权利要求13所述的多晶硅薄膜晶体管元件，其特征在于，该单层结构缓冲层是为一多孔(porous)缓冲层。
15.如权利要求12所述的多晶硅薄膜晶体管元件，其特征在于，该缓冲层是为一多层堆叠结构缓冲层，其包括至少一底缓冲层位于该基板上以及一顶缓冲层位于该至少一底缓冲层上，且该多个掺质是位于该多层堆叠结构缓冲层的该顶缓冲层内。
16.如权利要求15所述的多晶硅薄膜晶体管元件，其特征在于，该顶缓冲层是为一多孔缓冲层。
17.如权利要求12所述的多晶硅薄膜晶体管元件，其特征在于，另包括：
一层间介电层位于该栅极上；以及
一源极电极与一漏极电极位于该层间介电层上，其中该源极电极与该源极掺杂区电性连接，且该漏极电极与该漏极掺杂区电性连接。
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