CN105448999B - Polysilicon thin film transistor element and manufacturing method thereof - Google Patents

Polysilicon thin film transistor element and manufacturing method thereof Download PDF

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Publication number
CN105448999B
CN105448999B CN201510872131.3A CN201510872131A CN105448999B CN 105448999 B CN105448999 B CN 105448999B CN 201510872131 A CN201510872131 A CN 201510872131A CN 105448999 B CN105448999 B CN 105448999B
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layer
buffer layer
admixture
polycrystalline sitft
substrate
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CN105448999A (en
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萧翔允
陈佳楷
林世亮
许庭毓
王培筠
黄雅琴
江丞伟
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AU Optronics Corp
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    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/361—Organic materials
    • G02F1/3618—Langmuir Blodgett Films
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Abstract

A method for fabricating a polysilicon thin film transistor device includes the following steps. A substrate is provided, and a buffer layer with a plurality of dopants is formed on the substrate. An amorphous silicon layer is formed on the buffer layer with the dopant. And performing a thermal process to polycrystallize the amorphous silicon layer to convert the amorphous silicon layer into a polycrystalline silicon layer, and simultaneously, diffusing a part of the dopants in the buffer layer out to the polycrystalline silicon layer to adjust the initial voltage. And patterning the polysilicon layer to form an active layer. A gate insulating layer is formed on the active layer. Forming a gate on the gate insulating layer. And forming a source electrode doped region and a drain electrode doped region in the active layer.

Description

Polycrystalline SiTFT element and preparation method thereof
[technical field]
The present invention relates to a kind of polycrystalline SiTFT elements and preparation method thereof, espespecially a kind of that there is high electronics to move The polycrystalline SiTFT element and preparation method thereof of shifting rate (mobility).
[background technique]
Low temperature polycrystalline silicon (low temperature polycrystalline silicon, LTPS) thin film transistor (TFT) member Part theoretically has more amorphous silicon (amorphous due to having the characteristic compared with high electron mobility (mobility) Silicon) thin-film transistor element more preferably electrical performance.However, due to the processing procedure of low-temperature polysilicon film transistor element It is complex, compared to amorphous silicon film transistor element will more multiple tracks photoetching and etching (photolithography And etching, PEP) processing procedure, therefore not only cost of manufacture is higher, and yield can also decline.
[summary of the invention]
The one of the purpose of the present invention is to provide a kind of polycrystalline SiTFT element and preparation method thereof, to simplify system Journey step and cost of manufacture simultaneously promote electron mobility and element characteristic.
One embodiment of the invention provides a kind of method for making polycrystalline SiTFT element, includes the following steps. Substrate is provided, and being formed has the buffer layer of multiple admixtures on substrate.Amorphous silicon layer is formed on the buffer layer with admixture. Carry out hot processing procedure, by amorphous silicon layer polycrystallization to be converted into polysilicon layer, and simultaneously by the admixture of a part in buffer layer to To adjust starting voltage in external diffusion to polysilicon layer.Patterned polysilicon layer, to form active layer.Formed gate insulating layer in On active layer.Grid is formed on gate insulating layer.Source doping region and drain doping region are formed in active layer.
Another embodiment of the present invention provides a kind of polycrystalline SiTFT element, is set on substrate.Polysilicon is thin Film transistor element includes buffer layer, polysilicon layer, gate insulating layer and grid.Buffer layer is set on substrate, and buffer layer It is interior that there are multiple admixtures.Polysilicon layer is set on buffer layer, wherein polysilicon layer includes channel, source doping region and leakage Pole doped region, and source doping region and drain doping region are located at the two sides in channel.Gate insulating layer is set to polysilicon layer On.Grid is set to the channel on gate insulating layer and corresponding to polysilicon layer.
[Detailed description of the invention]
Fig. 1 depicts the method flow diagram of production polycrystalline SiTFT element of the invention.
Fig. 2 to Fig. 8 depicts the method signal of the production polycrystalline SiTFT element of the first embodiment of the present invention Figure.
Fig. 9 is painted the schematic diagram of the production display panel of one embodiment of the invention.
The method that Figure 10 and Figure 11 depicts the production polycrystalline SiTFT element of the second embodiment of the present invention is shown It is intended to.
Figure 12 is painted the Drain current-Gate Voltage relational graph and electricity of the polycrystalline SiTFT element of comparative examples Transport factor-grid voltage relational graph.
Figure 13 is painted the Drain current-Gate Voltage relationship of the polycrystalline SiTFT element of first sample of the invention Figure and electron mobility-grid voltage relational graph.
Figure 14 is painted the Drain current-Gate Voltage relationship of the polycrystalline SiTFT element of the second sample of the invention Figure and electron mobility-grid voltage relational graph.
[symbol description]
1,2 polycrystalline SiTFT element, 30 substrate
32 buffer layer 32B bottom buffering layers
32B1 the first bottom buffering layer 32B2 the second bottom buffering layer
32B3 third bottom buffering layer 32T pushes up buffer layer
34 admixture, 37 laser beam
36 amorphous silicon layer, 38 polysilicon layer
381 channels active layer 38C
The source doping region the 38S drain doping region 38D
40 gate insulating layer of 38L lightly doped district
44 interlayer dielectric layer of 42G grid
441 first interlayer dielectric layer, 442 second interlayer dielectric layer
46S source electrode 46D drain electrode
48 protective layer PE pixel electrodes
50 substrate CE common electrodes
52 display dielectric layer, 100 display panel
[specific embodiment]
To enable the general those skilled in the art for being familiar with the technical field of the invention to be further understood that the present invention, hereafter spy is enumerated Presently preferred embodiments of the present invention, and cooperate institute's accompanying drawings, the constitution content that the present invention will be described in detail and it is to be reached the effect of.
Please refer to Fig. 1.Fig. 1 depicts the method flow diagram of production polycrystalline SiTFT element of the invention.Such as Fig. 1 Shown, the method for production polycrystalline SiTFT element of the invention includes the following steps.
Step 10: substrate is provided.
Step 12: being formed has the buffer layer of multiple admixtures on substrate.
Step 14: forming amorphous silicon layer on the buffer layer with admixture.
Step 16: hot processing procedure is carried out, by amorphous silicon layer polycrystallization to be converted into polysilicon layer, and simultaneously will be in buffer layer The admixture of a part is spread outward in polysilicon layer to adjust starting voltage.
Step 18: patterned polysilicon layer is to form active layer.
Step 20: forming gate insulating layer on active layer.
Step 22: forming grid on gate insulating layer.
Step 24: forming source doping region and drain doping region in active layer.
Please continue to refer to Fig. 2 to Fig. 8, and Fig. 1 is referred to together.Fig. 2 to Fig. 8 depicts the system of the first embodiment of the present invention Make the method schematic diagram of polycrystalline SiTFT element.As shown in Fig. 2, providing substrate 30 first.Substrate 30 may include transparent Substrate such as glass substrate, plastic substrate, quartz base plate, sapphire substrate or other suitable substrates, and substrate 30 can be selected firmly Matter substrate or flexible substrate.Then, being formed has the buffer layer 32 of multiple admixtures 34 on substrate 30.In the present embodiment, Buffer layer 32 is single layer structure buffer layer, and its material may include inorganic insulating material such as silica, and but not limited to this.It is slow The material for rushing layer 32 may also comprise silicon nitride, silicon oxynitride or other suitable inorganic or organic insulating material.In other implementations In example, buffer layer 32 can be multilayer lamination structure buffer layer.Buffer layer 32 can utilize deposition manufacture process such as chemical vapor deposition (CVD) processing procedure, physical vapour deposition (PVD) (PVD) or other suitable deposition manufacture process are formed.In addition, the method for the present embodiment may include In formed buffer layer 32 deposition manufacture process in simultaneously be passed through the gas comprising admixture 34, in buffer layer 32 formed admixture 34, That is, buffer layer 32 and admixture 34 can be in forming together in same reaction chamber.Admixture 34 in buffer layer 32 may include p-type Admixture such as boron ion or N-type admixture such as phosphonium ion, in this situation, be passed through reaction chamber gas can for comprising boron ion or The gas of phosphonium ion, but not limited to this.In addition, buffer layer 32 can be subject to respectively with 34 gadolinium of admixture in an alternate embodiment Production, also can advanced row deposition manufacture process in buffer layer 32 on substrate 30, then carry out again ion disposing process in Admixture 34 is formed in buffer layer 32.In the present embodiment, the doping concentration of the admixture 34 in buffer layer 32 for example can be between 8x1014 To 4x1015atom/cm3Between, but not limited to this.The visual polycrystalline SiTFT element of the doping concentration of admixture 34 rises The difference of beginning voltage specification and hot processing procedure and changed.In addition, admixture 34 can be to be uniformly distributed or big portion in buffer layer 32 It is distributed in the region close to the surface of buffer layer 32, or is gradient distribution.
As shown in figure 3, being subsequently formed amorphous silicon layer 36 on the buffer layer 32 with admixture 34.Amorphous silicon layer 36 is available Deposition manufacture process such as chemical vapor deposition (CVD) processing procedure, plasma reinforced chemical vapour deposition (PECVD) processing procedure or other suitable Deposition manufacture process formed.
As shown in figure 4, hot processing procedure is then carried out, by 36 polycrystallization of amorphous silicon layer to be converted into polysilicon layer 38, and simultaneously The admixture 34 of a part in buffer layer 32 is spread outward in polysilicon layer 38 to adjust starting voltage.The side of the present embodiment Method can be the method for production low-temperature polysilicon film transistor element, wherein hot processing procedure may include quasi-molecule laser annealing (Excimer Laser Annealing, ELA) processing procedure, using laser beam 37 with scanning mode sequentially to different location Amorphous silicon layer 36 carries out polycrystallization, so that amorphous silicon is rearranged into polysilicon.In an alternate embodiment, hot processing procedure can also be wrapped Include solid phase crystallization (Solid Phase Crystallization, SPC) processing procedure or other suitable hot processing procedure.In quasi-molecule In laser annealing processing procedure, buffer layer 32 also will receive the irradiation of laser beam 37 and admixture 34 that is heated and making a part is spread Make polysilicon layer 38 form doping in polysilicon layer 38, has the function that adjust starting voltage.It is worth noting that when When admixture 34 in buffer layer 32 diffuses to polysilicon layer 38, buffer layer 32 may have rough surface, and buffer layer 32 can shape At porous (porous) buffer layer, wherein at this point, the doping concentration of the admixture 34 of the buffer layer 32 after hot processing procedure can be less than heat system The doping concentration of the admixture 34 of the buffer layer 32 of Cheng Qian.In this situation, after the irradiation of laser beam 37, thermal energy can store Product makes the grain boundary size (grain of the polysilicon in polysilicon layer 38 in the rough surface and hole of buffer layer 32 Boundary size) it increases (i.e. the tube core of polysilicon becomes larger) and crystal seed growth can be optimized.That is, the heat of the present embodiment Processing procedure can carry out polycrystallization to amorphous silicon layer 36 simultaneously, and be doped to polysilicon layer 38 together to adjust starting electricity Pressure.In addition, compared to the mode and utilize heat system that ion disposing process is directly doped polysilicon layer 38 is utilized respectively Journey carries out the mode of polycrystallization to amorphous silicon layer 36, and the present embodiment carries out polysilicon layer 38 using the admixture 34 in buffer layer 32 The practice of doping do not need only together hot processing procedure can reach to adjust and play starting voltage and polycrystallization, and in buffer layer 32 Hole can more play the effect of accumulation thermal energy so that the grain boundary size of polysilicon in polysilicon layer 38 increases and can optimize crystalline substance Kind growth, and can help to promote electron mobility.
In addition, in order to further improve the crystallization ability of quasi-molecule laser annealing processing procedure, the buffer layer 32 of the present embodiment Thickness and refractive index and the wavelength of excimer laser between can meet the relationship of following formula (1).
2nd=m λ (1)
Wherein n is the refractive index of buffer layer 32, and d is the thickness of buffer layer 32, and λ is the wavelength of excimer laser, and m is positive whole Number.
Under conditions of meeting above-mentioned formula (1), excimer laser can generate in buffer layer 32 to resonate and amplified energy, The crystalline condition of polysilicon can be improved whereby and increase grain boundary size, and then promote electron mobility and element characteristic.
It is worth noting that before carrying out hot processing procedure, the method for the present embodiment optionally first to amorphous silicon layer 36 into Row dehydrogenation (dehydrogenation) processing procedure, and can be simultaneously by the admixture 34 of a part in buffer layer 32 in dehydrogenation processing procedure It diffuses in amorphous silicon layer 36.
As shown in figure 5, then patterning to polysilicon layer 38, the polysilicon layer 38 for removing a part is active to be formed Layer 381.Above-mentioned patterning process can be photoetching and etch process, and but not limited to this.
As shown in fig. 6, forming channel 38C, source doping region 38S and drain doping region 38D in active layer 381, wherein Source doping region 38S and drain doping region 38D is located at the two sides of channel 38C.In addition, optionally in channel 38C with Lightly doped district 38L is respectively formed between the 38S of source doping region and between channel 38C and drain doping region 38D, wherein source electrode The doping concentration of doped region 38S and drain doping region 38D is greater than the doping concentration of lightly doped district 38L, and the doping of channel 38C is dense Degree is less than source doping region 38S, drain doping region 38D and lightly doped district 38L.
In the present embodiment, source doping region 38S, drain doping region 38D and lightly doped district 38L can utilize ion implant system Journey and mask (not shown) such as photoresist pattern of arranging in pairs or groups is formed.For example, photoresist figure can be formed prior to the surface of active layer 381 Case, wherein photoresist pattern covering channel 38C and the predetermined region for forming lightly doped district 38L simultaneously expose and predetermined form source electrode and mix The region of miscellaneous area 38S and drain doping region 38D.Then, the active layer 381 exposed is carried out as mask using photoresist pattern Ion disposing process is to form source doping region 38S and drain doping region 38D.Then, the photoresist pattern of a part is removed for example Using ashing processes further to expose the predetermined region for forming lightly doped district 38L, and photoresist pattern after reduction is recycled to make Carry out ion disposing process again for mask to form lightly doped district 38L.Finally, removing remaining photoresist pattern.Source of the invention Pole doped region 38S is not limited with the production method of drain doping region 38D and lightly doped district 38L with above-described embodiment.Changing In embodiment, source doping region 38S and drain doping region 38D is formed using an ion disposing process and a mask of arranging in pairs or groups, and Lightly doped district 38L can utilize another ion disposing process and another mask of arranging in pairs or groups.Alternatively, source doping region 38S and drain implants Area 38D and lightly doped district 38L is made using the grid being subsequently formed as mask.Later, the method for the present embodiment It may include that hydrogenation processing procedure is carried out to polysilicon layer 38, to repair the defect of polysilicon layer 38.In addition, the method for the present embodiment can also Including activation process, such as thermal annealing processing procedure or laser annealing system can be carried out to source doping region 38S and drain doping region 38D Journey, to reduce the resistance value of source doping region 38S Yu drain doping region 38D.
As shown in fig. 7, being subsequently formed gate insulating layer 40 on active layer 381.The material of gate insulating layer 40 can be nothing Machine material such as silica, silicon nitride or silicon oxynitride, but not limited to this.Then, grid 42G is formed in gate insulating layer 40 On, wherein grid 42G is be overlapped on upright projection direction with channel 38C.In the present embodiment, the material of grid 42G may include The metals such as metal or alloy, such as gold, silver, copper, aluminium, titanium, molybdenum or its alloy or other suitable conductive material.
As shown in figure 8, being subsequently formed interlayer dielectric layer 44 on grid 42G, and to interlayer dielectric layer 44 and gate insulator Layer 40 is patterned to expose source doping region 38S and drain doping region 38D.Above-mentioned patterning process can be photoetching and erosion Journey is scribed, but not limited to this.In the present embodiment, interlayer dielectric layer 44 can be multiple stacked structure interlayer dielectric layer, can It is located on grid 42G including such as the first interlayer dielectric layer 441 and the second interlayer dielectric layer 442 is stacked in the first interlayer Jie In electric layer 441, wherein the first interlayer dielectric layer 441 can be inorganic dielectric layer, such as silicon oxide layer, silicon nitride layer or nitrogen oxidation Silicon layer, but not limited to this；Second interlayer dielectric layer 442 can be organic dielectric layer, and but not limited to this.In alternate embodiment In, interlayer dielectric layer 44 also can be single layer structure layer.Then, source electrode 46S and drain electrode 46D are formed in interlayer dielectric layer On 44, wherein source electrode 46S and source doping region 38S is electrically connected, and drain electrode 46D and drain doping region 38D is electrical Connection.The material of source electrode 46S and drain electrode 46D may include the gold such as metal or alloy, such as gold, silver, copper, aluminium, titanium, molybdenum Category or its alloy or other suitable conductive material.So far, the polycrystalline SiTFT element 1 of the present embodiment can be produced. Interlayer dielectric layer 44 in the present embodiment can design for multiple stacked structure, can increase the effect to resonate in laser annealing processing procedure, Grain boundary size can be made to increase and crystal seed growth can be optimized, and then promote electron mobility and element characteristic.
The polycrystalline SiTFT element 1 of the present embodiment can be applied to display panel such as liquid crystal display panel, electric shock On luminescence display panel or the display panel of various other types, touch panel or any electronic device or electrooptical device, as opening Close the use of element or driving element.Please hookup 8 refer to Fig. 9.Fig. 9 is painted the production display panel of one embodiment of the invention Schematic diagram.As shown in figure 9, then sequentially forming a protective layer 48 and a pixel electrode PE in polycrystalline SiTFT element 1 On, wherein protective layer 48 can partially expose drain electrode 46D, and pixel electrode PE and drain electrode 46D is electrically connected.It connects , another substrate 50 is provided, and in formation common electrode CE on substrate 50.Then, substrate 30 is combined with substrate 50, and in base Display dielectric layer 52 is formed between plate 30 and substrate 50, to form the display panel 100 of the present embodiment.The present embodiment display panel 100 be by taking liquid crystal display panel as an example, therefore display dielectric layer 52 may include liquid crystal layer, and but not limited to this.In change In example, display panel can also be electric exciting light emitting display panel such as organic LED display panel, and display dielectric layer 52 It can be to be electrically excited photosphere or other suitable non-spontaneous smooth display dielectric layer or self-luminous display dielectric layer.The display of the present embodiment For panel 1 is the driving liquid crystal display panel of vertical electric field, such as nematic twist mode (TN) liquid crystal display panel or vertically match To type (VA) liquid crystal display panel, but not limited to this.For example, display panel of the invention can also drive for horizontal component of electric field Type liquid crystal display panel for example plane switch type (IPS) liquid crystal display panel, fringe field switching (FFS) liquid crystal display panel or The display panel of other patterns.In an alternate embodiment, common electrode CE can also be formed on substrate 30 and and pixel electrode PE is in the same plane, the application as plane electric fields switch type (IPS) liquid crystal display panel.In another alternate embodiment In, common electrode CE can also be formed on substrate 30 but be located in Different Plane with pixel electrode PE, switch as fringe field The application of type (FFS) liquid crystal display panel.
It can be seen from the above, the method for production polycrystalline SiTFT element of the invention utilizes the hot processing procedure in single road Amorphous silicon layer is converted into polysilicon layer, and starting electricity will be adjusted in the dopant diffusion to polysilicon layer in buffer layer simultaneously Pressure, therefore fabrication steps and cost of manufacture can be simplified.In addition, when the dopant diffusion in buffer layer to polysilicon layer, buffer layer It will form multi-hole buffer layer, therefore thermal energy can be accumulated in the crystalline substance in hole and making the polysilicon in polysilicon layer in hot processing procedure Boundary's larger and crystal seed growth can be optimized, and then promote electron mobility and element characteristic.
Polycrystalline SiTFT element of the invention and preparation method thereof is not limited with above-described embodiment.It hereafter will be according to Sequence introduces the polycrystalline SiTFT element of other preferred embodiments and preparation method thereof of the invention, and for the ease of comparing The deviation of each embodiment simultaneously simplifies explanation, marks identical element using identical symbol in the following embodiments, and It is illustrated mainly for the deviation of each embodiment, and no longer counterweight is partially repeated again.
Please continue to refer to Figure 10 and Figure 11, and Fig. 1 is referred to together.Figure 10 and Figure 11 depict the second embodiment of the present invention Production polycrystalline SiTFT element method schematic diagram.As shown in Figure 10, in the present embodiment, buffer layer 32 is multilayer Stacked structure buffer layer comprising an at least bottom buffering layer 32B is located on substrate 30 and a top buffer layer 32T is slow the bottom of positioned at It rushes on layer 32B.For example, the bottom buffering layer 32B of the buffer layer 32 of the present embodiment may include the first bottom buffering layer 32B1, second Bottom buffering layer 32B2 and third bottom buffering layer 32B3, is sequentially formed on substrate 30, and third can be formed in by pushing up buffer layer 32T On bottom buffering layer 32B3.In the present embodiment, the first bottom buffering layer 32B1, the second bottom buffering layer 32B2, third bottom buffering layer 32B3 and top buffer layer 32T can be the different materials film layer sequentially stacked, such as the first bottom buffering layer 32B1 and third bottom buffering The material of layer 32B3 can be silicon nitride, and the material of the second bottom buffering layer 32B2 and top buffer layer 32T can be silica, whereby may be used Increase the adhesive force with substrate 30 and reduces stress.In addition, the first bottom buffering layer 32B1, the second bottom buffering layer 32B2, third bottom The visual adhesive force of thickness, the stress of buffer layer 32B3 and top buffer layer 32T is adjusted with other consider.Implement pattern one In, the thickness of the second bottom buffering layer 32B2 and top buffer layer 32T can be greater than the first bottom buffering layer 32B1 and third bottom buffering layer The thickness of 32B3, such as the thickness of the second bottom buffering layer 32B2 or top buffer layer 32T can be the first bottom buffering layer 32B1 or third The several times of the thickness of bottom buffering layer 32B3, but not limited to this.
In the present embodiment, admixture 34 can be only formed in the top buffer layer 32T of multilayer lamination structure buffer layer, wherein Can be as in the foregoing embodiment in the mode for forming admixture 34 in the buffer layer 32T of top, such as form the deposition system of top buffer layer 32T It is passed through the gas comprising admixture 34 simultaneously in journey, in forming admixture 34, and not shape in bottom buffering layer 32B in the buffer layer 32T of top At admixture 34；Or it is initially formed top buffer layer 32T, carry out ion disposing process again then to be formed and mixed in the buffer layer 32T of top Matter 34, and admixture 34 is not formed in bottom buffering layer 32B.In an alternate embodiment, admixture 34 is in addition to being formed in top buffer layer 32T It is interior, it can also be formed in bottom buffering layer 32B.
As shown in figure 11, the processing procedure for then carrying out Fig. 3 to Fig. 8 such as first embodiment, can produce the present embodiment Polycrystalline SiTFT element 2.
The polycrystalline SiTFT element 2 of the present embodiment can be applied to display panel such as liquid crystal display panel, electric shock On luminescence display panel or the display panel of various other types, touch panel or any electronic device or electrooptical device, as opening The use of element or driving element is closed, as shown in above-described embodiment, details are not described herein.
Figure 12 is please referred to Figure 14.Figure 12 is painted the drain current-of the polycrystalline SiTFT element of comparative examples Grid voltage relational graph and electron mobility-grid voltage relational graph, the polysilicon that Figure 13 is painted first sample of the invention are thin Drain current-Gate Voltage relational graph and electron mobility-grid voltage relational graph of film transistor element, and Figure 14 is painted this The Drain current-Gate Voltage relational graph and electron mobility-grid of the polycrystalline SiTFT element of second sample of invention Pole tension relational graph.In the method for comparative examples (Figure 12), polycrystalline SiTFT element is to utilize ion implant system Journey directly carries out the adjustment of starting voltage to polysilicon layer, and without admixture in buffer layer, and be in drain voltage Vd respectively It is tested under conditions of 0.1V, 5.1V, 10.1V；The method of (the 13rd and 14 figure) of the invention is first to carry out ion to buffer layer Implant processing procedure, then polycrystallization is carried out and together by the more of dopant diffusion to polysilicon membrane transistor unit simultaneously by hot processing procedure In crystal silicon layer, and it is respectively 0.1V in drain voltage Vd, is tested under conditions of 5.1V, 10.1V, wherein the first of Figure 13 The energy of the ion disposing process of sample is 60kev, and admixture is boron ion, and doping concentration is 5*1013atoms/cm3；Figure 14 The energy of ion disposing process of the second sample be 60kev, admixture is phosphonium ion, and doping concentration is 2*1014atoms/ cm3.As shown in figure 12, the starting voltage (Vth) of the polycrystalline SiTFT element of comparative examples is about -2.71V.It compares Under, as shown in figure 13, the starting voltage (Vth) of the polycrystalline SiTFT element of first sample is about -1.17V；Such as figure Shown in 14, the starting voltage (Vth) of the polycrystalline SiTFT element of the second sample is about -2.02V.By above-mentioned experimental data It is found that by hot processing procedure while carrying out polycrystallization and together by dopant diffusion to polycrystalline again by admixture is initially formed in buffer layer The practice in the polysilicon layer of silicon thin film transistor element can effectively adjust starting voltage to scheduled section really.
In addition, experiment made by grain boundary size of the present invention for polysilicon layer is also shown by shape first in buffer layer Polycrystallization and the together polycrystalline by dopant diffusion to polysilicon membrane transistor unit are carried out simultaneously by hot processing procedure again at admixture The practice in silicon layer can effectively increase grain boundary size (i.e. increase die-size).Table 1 is please referred to, table 1, which has listed control, to be implemented The grain boundary size of example and one embodiment of the invention, wherein comparative examples are in buffer layer without admixture under conditions of institute The grain boundary size actually measured, and the present embodiment be in buffer layer doped with argon (Ar) ion under conditions of practical measure Grain boundary size.
Table 1
Comparative examples The present embodiment
Grain boundary size (grain boundary size) 0.3098 micron 0.3432 micron
As shown in Table 1, under conditions of in buffer layer without admixture, the grain boundary size of comparative examples is about 0.3098 micron, and in buffer layer under conditions of formation admixture, the grain boundary size of the present embodiment is about 0.3432 micron, brilliant Ungraduated ruler cun increases about 10.81%.
In conclusion the method for production polycrystalline SiTFT element of the invention can be incited somebody to action using the hot processing procedure in single road Amorphous silicon layer is converted into polysilicon layer, and will adjust starting voltage extremely in the dopant diffusion to polysilicon layer in buffer layer together Predetermined interval, therefore fabrication steps and cost of manufacture can be simplified.In addition, when the dopant diffusion in buffer layer to polysilicon layer, Buffer layer will form multi-hole buffer layer, therefore thermal energy can be accumulated in hole and make the polycrystalline in polysilicon layer in hot processing procedure The grain boundary size of silicon increases and can optimize crystal seed growth, and then promotes electron mobility and element characteristic.
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with Modification, is all covered by the present invention.

Claims (17)

1. a kind of method for making polycrystalline SiTFT element characterized by comprising
One substrate is provided；
A buffer layer with multiple admixtures (dopant) is formed on the substrate；
An amorphous silicon layer is formed on the buffer layer with multiple admixture；
A hot processing procedure is carried out, by the amorphous silicon layer polycrystallization to be converted into a polysilicon layer, and simultaneously by one in the buffer layer Partial multiple admixture is spread outward in the polysilicon layer to adjust starting voltage (threshold voltage)；
The polysilicon layer is patterned, to form an active layer；
A gate insulating layer is formed on the active layer；
A grid is formed on the gate insulating layer；And
A source doping region and a drain doping region are formed in the active layer；Wherein, multiple admixture packet in the buffer layer Include p-type admixture or N-type admixture.
2. as described in claim 1 production polycrystalline SiTFT element method, which is characterized in that the buffer layer be for One single layer structure buffer layer.
3. the method for production polycrystalline SiTFT element as claimed in claim 2, which is characterized in that in carrying out the heat system Before journey, multiple admixture is located in the single layer structure buffer layer.
4. as described in claim 1 production polycrystalline SiTFT element method, which is characterized in that the buffer layer be for One multilayer lamination structure buffer layer comprising an at least bottom buffering layer is located on the substrate and a top buffer layer is located at this at least On one bottom buffering layer.
5. the method for production polycrystalline SiTFT element as claimed in claim 4, which is characterized in that in carrying out the heat system Before journey, multiple admixture is in the top buffer layer of the multilayer lamination structure buffer layer.
6. the method for production polycrystalline SiTFT element as described in claim 1, which is characterized in that in shape on the substrate Include: at the step of buffer layer with multiple admixture
A deposition manufacture process is carried out to be passed through simultaneously comprising multiple in depositing the buffer layer on the substrate, and in the deposition manufacture process The gas of admixture, in forming multiple admixture in the buffer layer.
7. the method for production polycrystalline SiTFT element as described in claim 1, which is characterized in that in shape on the substrate Include: at the step of buffer layer with multiple admixture
A deposition manufacture process is carried out in depositing the buffer layer on the substrate；And
An ion disposing process is carried out in forming multiple admixture in the buffer layer.
8. the method for production polycrystalline SiTFT element as described in claim 1, which is characterized in that the hot processing procedure includes One quasi-molecule laser annealing (Excimer Laser Annealing, ELA) processing procedure.
9. the method for production polycrystalline SiTFT element as described in claim 1, which is characterized in that the hot processing procedure includes Solid phase crystallization (Solid Phase Crystallization, SPC) processing procedure.
10. as described in claim 1 production polycrystalline SiTFT element method, which is characterized in that separately be included in into Before the row hot processing procedure, a dehydrogenation (dehydrogenation) processing procedure first is carried out to the amorphous silicon layer, and further should simultaneously In multiple dopant diffusion to the amorphous silicon layer of a part in buffer layer.
11. the method for production polycrystalline SiTFT element as described in claim 1, which is characterized in that separately include:
An interlayer dielectric layer is formed on the grid；And
A source electrode and a drain electrode are formed on the interlayer dielectric layer, wherein the source electrode and the source doping region are electric Property connection, and the drain electrode and the drain doping region are electrically connected.
12. a kind of polycrystalline SiTFT element, is set on a substrate, which is characterized in that the polycrystalline SiTFT Element includes:
One buffer layer is set on the substrate, wherein has multiple admixtures (dopant) in the buffer layer；
One polysilicon layer is set on the buffer layer, and wherein the polysilicon layer includes a channel, a source doping region and a leakage Pole doped region, and the source doping region and the drain doping region are located at the two sides in the channel；
One gate insulating layer is set on the polysilicon layer；And
One grid is set on the gate insulating layer and corresponds to the channel of the polysilicon layer；Wherein, being somebody's turn to do in the buffer layer Multiple admixtures include p-type admixture or N-type admixture.
13. polycrystalline SiTFT element as claimed in claim 12, which is characterized in that the buffer layer is for a single layer knot Structure buffer layer, and multiple admixture is located in the single layer structure buffer layer.
14. polycrystalline SiTFT element as claimed in claim 13, which is characterized in that the single layer structure buffer layer be for One porous (porous) buffer layer.
15. polycrystalline SiTFT element as claimed in claim 12, which is characterized in that the buffer layer is for a multilayer heap Stack structure buffer layer comprising an at least bottom buffering layer is located on the substrate and a top buffer layer is located at an at least bottom buffering On layer, and multiple admixture is in the top buffer layer of the multilayer lamination structure buffer layer.
16. polycrystalline SiTFT element as claimed in claim 15, which is characterized in that the top buffer layer is porous for one Buffer layer.
17. polycrystalline SiTFT element as claimed in claim 12, which is characterized in that separately include:
One interlayer dielectric layer is located on the grid；And
One source electrode and a drain electrode are located on the interlayer dielectric layer, and wherein the source electrode and the source doping region are electrical Connection, and the drain electrode and the drain doping region are electrically connected.
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