CN1967876A - Thin film transistor and method of manufacturing the same - Google Patents
Thin film transistor and method of manufacturing the same Download PDFInfo
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- CN1967876A CN1967876A CN 200610138192 CN200610138192A CN1967876A CN 1967876 A CN1967876 A CN 1967876A CN 200610138192 CN200610138192 CN 200610138192 CN 200610138192 A CN200610138192 A CN 200610138192A CN 1967876 A CN1967876 A CN 1967876A
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Abstract
A thin film transistor (TFT) and a method of manufacturing the same, and more particularly, a TFT for reducing leakage current and a method of manufacturing the same are provided. The TFT includes a flexible substrate, a diffusion preventing layer formed on the flexible substrate, a buffer layer formed of at least two insulated materials on the diffusion preventing layer, a semiconductor layer formed on a region of the buffer layer to include a channel layer and a source and drain region, a gate insulating layer formed on the buffer layer including the semiconductor layer, a gate electrode formed on the gate insulating layer in a region corresponding to the channel layer, an interlayer insulating layer formed on the gate insulating layer including the gate electrode, and source and drain electrodes formed in the interlayer insulating layer to include a predetermined contact hole that exposes at least a region of the source and drain region and to be connected to the source and drain region.
Description
The application advocates priority to the following patent application of submitting in Korea S Department of Intellectual Property, that is: the application number of submitting on November 16th, 2005 is the korean patent application of 10-2005-0109826; The application number of submitting on November 29th, 2005 is the korean patent application of 10-2005-0115112; The application number of submitting on November 30th, 2005 is the korean patent application of 10-2005-0115969; With the application number of submitting on December 9th, 2005 be the korean patent application of 10-2005-0120898, the disclosure of above-described patent application is merged in by reference at this.
Technical field
The present invention relates to a kind of thin-film transistor (TFT) and manufacture method thereof, and relate more specifically to a kind of thin-film transistor (TFT).
Background technology
Usually, can be made into flexibility such as organic light emitting display (OLED) and Thin Film Transistor-LCD flat-panel monitors (FPD) such as (TFT-LCD).In order to make display have flexibility, used flexible substrate.Flexible substrate can be plastic or metal foil substrate.
Plastic is typically made by synthetic resin.Yet when TFT was formed on the plastic, this substrate may deform.Be formed at the film on the substrate owing to for example apply moisture and oxygen, also can deform.
On the other hand, the flexibility such as metal foil substrate such as stainless steel (SUS) or Ti is weaker than plastic.Yet among the TFT on being formed at metal foil substrate, organic luminous layer can not worsen owing to the transmission of moisture and oxygen.In addition, metal foil substrate can be born high temperature process.Therefore, metal foil substrate can be used for having the TFT of the polysilicon semiconductor layer that forms by high temperature process.
Usually, be formed on the conductive substrates, particularly be formed on the conductive film that forms by SUS or Ti, can between conductive film and TFT, adopt the buffer insulation layer in order to make TFT.The TFT and the silicon-on-insulator (SOI) that are formed at the resilient coating top on the conductive film have similar electrology characteristic and architectural characteristic.At this moment, make this amorphous si-layer crystallization or the amorphous si-layer LTPS that obtains that anneals is used as the semiconductor layer that forms TFT by the low-temperature heat amorphous si-layer by excimer laser.
When making traditional TFT, during the thermal annealing processing of being scheduled on the LTPS, meetings such as the impurity of substrate such as Cr, Fe, Ni and C are diffused in the semiconductor layer by resilient coating.
Summary of the invention
An aspect of of the present present invention provides a kind of electronic device that comprises thin-film transistor.Described device comprises: flexible substrate, and it comprises sheet metal; Semiconductor layer, it is formed at the top of described flexible substrate, and described semiconductor layer comprises source region, drain region and the channel region between described source region and described drain region; Gate electrode, it is formed at the top of described semiconductor layer; Gate insulator, it is between described gate electrode and described semiconductor layer; Source electrode, it contacts described semiconductor layer; Drain electrode, it contacts described semiconductor layer; Resilient coating, it is between described flexible substrate and described semiconductor layer; And diffusion impervious layer, it comprises Ti or Ta and between described flexible substrate and described resilient coating.
Described sheet metal can comprise one or more materials of selecting from the group of being made of stainless steel (SUS) and Ti.Described diffusion impervious layer can comprise one or more materials of selecting from the group of being made of TiN, TaSiN, TiSiN and TiAlN.The thickness of described diffusion impervious layer can be approximately between 100nm and the about 500nm.Described resilient coating can comprise from by SiO
2, one or more materials of selecting in the group formed of SiNx and SiNO.The thickness of described resilient coating can be approximately between 50nm and the about 2 μ m.Described resilient coating can comprise two or more layers, and each layer all comprises from by SiO
2, the material selected in the group formed of SiNx and SiNO.Described resilient coating can comprise and contains SiO
2Ground floor and contain the second layer of SiNx.Described resilient coating may further include and contains SiO
2The 3rd layer and contain the 4th layer of SiNx.Described semiconductor layer can comprise organic semiconducting materials.
Another aspect of the present invention provides a kind of manufacturing to comprise the method for the electronic device of thin-film transistor.Described method comprises: the flexible substrate that comprises sheet metal is provided; Form diffusion impervious layer above described flexible substrate, described diffusion impervious layer comprises Ti or Ta; Above described diffusion impervious layer, form resilient coating; Above described resilient coating, form semiconductor layer; And described semiconductor layer carried out thermal annealing.
Described sheet metal can comprise one or more materials of selecting from the group of being made of stainless steel (SUS) and Ti.Described diffusion impervious layer can comprise one or more materials of selecting from the group of being made of TiN, TaSiN, TiSiN and TiAlN.Described resilient coating can comprise one or more materials of selecting from the group of being made of SiO2, SiNx and SiNO.Described resilient coating can comprise two or more layers, and each layer all comprises from by SiO
2, the material selected in the group formed of SiNx and SiNO.Described thermal annealing can be in the time period of implementing under the temperature between about 350 ℃ and about 450 ℃ between about 10 minutes and about 1 hour.Described method may further include before described semiconductor layer is carried out described thermal annealing, and impurity is mixed into one or more parts of described semiconductor layer.
Described method can further comprise successively: form cover layer above described semiconductor layer; And after forming described semiconductor layer and before described semiconductor layer is carried out described thermal annealing, form metal catalytic layer above tectal described.Described metal catalytic layer can comprise select at least a from the group of being made of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd and Pt.Described thermal annealing can comprise rapid thermal annealing (RTA).
Another aspect of the present invention provides a kind of electronic device of making by method mentioned above.
Another aspect of the present invention provides a kind of thin-film transistor (TFT) and makes this transistorized method, in this transistor, is prevented from being diffused in the semiconductor layer such as impurity such as metal ions in the flexible substrate, thereby has reduced leakage current.
Another aspect of the present invention provides a kind of thin-film transistor, and it comprises: flexible substrate; Barrier layer, it is formed on the described flexible substrate; Resilient coating, it is formed on the described barrier layer and forms double-deck at least; Semiconductor layer, it is formed on the zone of described resilient coating, comprises channel layer, source region and drain region; Gate insulator, it is formed on described resilient coating and the described semiconductor layer; Gate electrode, it is formed on the described gate insulator in the zone corresponding to described channel layer; Interlayer insulative layer, it is formed on described gate insulator and the gate electrode; And source electrode and drain electrode, it is formed in the described interlayer insulative layer, comprises predetermined contact hole and is connected to described source electrode and drain region, at least one zone of described source electrode of described contact holes exposing and drain region.
Another aspect of the present invention provides a kind of TFT, and it comprises: flexible substrate; The amorphous barrier layer of three-phase, it forms and is formed on the described flexible substrate by nonmetal; Resilient coating, it is formed on the described barrier layer and forms double-deck at least; Semiconductor layer, it is formed on the zone of described resilient coating, comprises channel layer, source region and drain region; Gate insulator, it is formed on described resilient coating and the described semiconductor layer; Gate electrode, it is formed on the described gate insulator in the zone corresponding to described channel layer; Interlayer insulative layer, it is formed on described gate insulator and the described gate electrode; And source electrode and drain electrode, it is formed in the described interlayer insulative layer, comprises predetermined contact hole and is connected to described source electrode and drain region, at least one zone in described source electrode of described contact holes exposing and the drain region.
Another aspect of the present invention provides a kind of TFT, and it comprises: flexible substrate; Barrier layer, it is formed on the described flexible substrate; Resilient coating, it is formed on the described barrier layer and forms double-deck at least; Semiconductor layer, it is formed on the zone of described resilient coating, comprises channel layer, source region and drain region, and described like this source electrode and drain region are activated by rapid thermal annealing (RTA) method; Gate insulator, it is formed on described resilient coating and the described semiconductor layer; Gate electrode, it is formed on the described gate insulator in the zone corresponding to described channel layer; Interlayer insulative layer, it is formed on described gate insulator and the described gate electrode; And source electrode and drain electrode, it is formed in the described interlayer insulative layer, comprises predetermined contact hole and is connected to described source electrode and drain region, at least one zone in described source electrode of described contact holes exposing and the drain region.
Another aspect of the present invention provides a kind of TFT, and it comprises: flexible substrate; Multi-buffering-layer, it is formed on the described substrate and forms double-deck at least; Semiconductor layer, it is formed on the described resilient coating, comprises source electrode and drain region, channel region and low-density doped region; First insulating barrier, it is formed on the described semiconductor layer; Gate electrode, it is formed on described first insulating barrier and corresponding to described semiconductor layer; Second insulating barrier, it is formed on the described gate electrode; And source electrode and drain electrode, it is electrically connected to described semiconductor layer by contact hole, and described contact hole is formed in described first insulating barrier and described second insulating barrier.
Another aspect of the present invention provides the method for a kind of TFT of manufacturing.Said method comprising the steps of: on flexible substrate, form barrier layer; Form resilient coating on described barrier layer, this resilient coating forms double-deck at least; On described resilient coating, form amorphous si-layer, described amorphous si-layer is crystallized into polysilicon layer and pattern changes into predetermined profile, thereby form semiconductor layer; On described resilient coating and described semiconductor layer, form gate insulator; On the zone of described gate insulator, form gate electrode; Use gate electrode as mask, the extra-regional remaining area except corresponding to described gate electrode of described semiconductor layer is carried out ion doping, thereby described semiconductor layer is divided into channel layer and source electrode and drain region; On described gate insulator and described gate electrode, form interlayer insulative layer; In stove, carried out thermal anneal process 10 minutes to 1 hour for about 350 ℃ to about 450 ℃, thereby activate described semiconductor layer in temperature; And the predetermined contact hole that exposes at least one zone in described source electrode and the drain region is provided, to form source electrode and drain electrode, described source electrode and drain electrode are connected to described source electrode and drain region by described contact hole.
Another aspect of the present invention provides the method for a kind of TFT of manufacturing, said method comprising the steps of: a kind of flexible substrate is provided; On described flexible substrate, form by the amorphous barrier layer of the nonmetal three-phase that forms; On described barrier layer, form resilient coating; On described resilient coating, form amorphous si-layer; On described amorphous si-layer, form cover layer; On described cover layer, form metal catalytic layer; On described substrate, carry out thermal anneal process, described amorphous si-layer is crystallized into polysilicon layer; Remove described metal catalytic layer and described cover layer; With described polysilicon layer one patterned to form semiconductor layer; And form gate insulator, gate electrode, interlayer insulative layer and source electrode and drain electrode being formed with on the described flexible substrate of described semiconductor layer.
Another aspect of the present invention provides the method for a kind of TFT of manufacturing, said method comprising the steps of: form barrier layer on flexible substrate; Form resilient coating on described barrier layer, this resilient coating forms double-deck at least; On described resilient coating, form amorphous si-layer, described amorphous si-layer is crystallized into polysilicon layer and pattern changes into predetermined profile, thereby form semiconductor layer; On described resilient coating and described semiconductor layer, form gate insulator; On the zone of described gate insulator, form gate electrode; Use gate electrode as mask, the extra-regional remaining area except corresponding to described gate electrode of described semiconductor layer is carried out ion doping, thereby described semiconductor layer is divided into channel layer and ohmic contact layer; On described gate insulator and described gate electrode, form interlayer insulative layer; Activate described semiconductor layer by the RTA method; And the predetermined contact hole that exposes at least one zone in the described ohmic contact layer is provided, to form source electrode and drain electrode, described source electrode and drain electrode are connected to described ohmic contact layer by described contact hole.
Another aspect of the present invention provides the method for a kind of TFT of manufacturing, said method comprising the steps of: form resilient coating on flexible substrate, it obtains by two insulating barriers of lamination at least; On described resilient coating, form the semiconductor layer of one patterned; On described semiconductor layer, form first insulating barrier; On described first insulating barrier, form gate electrode, with corresponding to described semiconductor layer with described gate electrode one patterned; Use described gate electrode as mask, the low density impurity ion is injected in the described semiconductor layer pattern and forms the low-density doped region; On described semiconductor layer, apply photoresist; Determine contact hole by photolithography; Source electrode that the injection of high density foreign ion is unlimited and drain region are to form source electrode and drain region; Remove described photoresist; On described gate electrode, form second insulating barrier; The contact hole of described first insulating barrier and described second insulating barrier is passed in formation; Depositing electrode; And with source electrode and drain electrode one patterned.
Description of drawings
In conjunction with the following drawings and to the description that execution mode carries out, will make above-mentioned these and/or other purpose of the present invention and advantage becomes obviously and easy to understand more, described accompanying drawing is as follows:
Figure 1A is that illustration is according to the thin-film transistor (TFT) of first execution mode and the sectional view of manufacture method thereof to 1G;
Fig. 2 A is the sectional view of illustration according to the leakage current characteristic of first execution mode to 2C;
Fig. 3 A is that illustration is according to the TFT of second execution mode and the sectional view of manufacture method thereof to 3D;
Fig. 4 A and 4B are that illustration is according to the TFT of the 3rd execution mode and the sectional view of manufacture method thereof; And
Fig. 5 A is the sectional view of illustration according to the TFT of the 4th execution mode to 5C.
Embodiment
Hereinafter, with reference to the accompanying drawings embodiments of the present invention are described.
Figure 1A to the 1F illustration according to the thin-film transistor (TFT) and the manufacture method thereof of first execution mode.To 1F, in TFT, on flexible substrate 100, be formed with barrier layer 110 with reference to Figure 1A.At this moment, flexible substrate 100 can comprise metal forming.This metal forming can comprise stainless steel (SUS) or Ti.
In one embodiment, barrier layer 110 can be made to the TiN of about 400nm by the about 100nm of thickness.Formed barrier layer 110 is used for preventing to be diffused into the semiconductor layer 130 (Figure 1A) through resilient coating 120 from substrate 100 during predetermined thermal anneal process such as impurity such as Cr, Fe, Ni and C.
In addition, shown in Fig. 1 G, can pass through lamination the one SiO
2Layer 120a, a SiNx layer 120b, the 2nd SiO
2Layer 120c and the 2nd SiNx layer 120d obtain resilient coating 120.In one embodiment, a SiO
2The thickness that layer 120a has is that about 200nm is to about 1 μ m.The thickness that the one SiNx layer 120b can have is that about 50nm is to about 200nm.The 2nd SiO
2The thickness that layer 120c can have is that about 50nm is to about 1 μ m.The thickness that the 2nd SiNx layer 120b can have is that about 50nm is to about 200nm.SiO
2The position of layer 120a and 120c and SiNx layer 120b and 120d can exchange (Figure 1B).
Then, on the zone of resilient coating 120, form the semiconductor layer 130 that comprises channel layer 130a and source electrode and drain region 130b.In one embodiment, semiconductor layer 130 comprises polysilicon.In order to form polysilicon, at first, on resilient coating 120, form amorphous si-layer.Then, after carrying out the dehydrogenation processing, by the amorphous si-layer crystallization after the dehydrogenation, it is by removing the hydrogen component at about 430 ℃ temperature heating amorphous si-layer and from this amorphous si-layer that described dehydrogenation is handled.In one embodiment, use excimer laser annealing (ELA) method to make the amorphous si-layer crystallization.When amorphous si-layer was crystallized into polysilicon layer, the polysilicon layer of crystallization was patterned and forms semiconductor layer 130 (Fig. 1 C).
Then, on resilient coating 120 and semiconductor layer 130, form gate insulator 140 (Fig. 1 D).Metal level (not shown) is formed on the gate insulator 140, and this metal level is patterned and forms gate electrode 150 (Fig. 1 E).Then, use gate electrode 150 as mask, to the remaining area doping except that channel layer 130a of semiconductor layer 130 with n type dopant (n+) or p type dopant (p+).
Then, on resilient coating 120, gate electrode 150 and semiconductor layer 130, form interlayer insulative layer 160.After interlayer insulative layer 160 forms, on semiconductor layer 130, carry out activation processing.On the other hand, when amorphous semiconductor layer 130 is formed polysilicon semiconductor layer by crystallization, and this polysilicon semiconductor layer 130 is when adopting ion showers to mix, the high energy dopant barrier rib that damage is annealed with the barrier rib collision.Like this, semiconductor layer 130 can become amorphous semiconductor layer and have the calking foreign atom, thereby dopant can not play a role well.Thereby, carrying out thermal anneal process so that semiconductor layer 130 is annealed, dopant becomes alternative formula like this, and this process is called as activation processing.In this case, activation processing was carried out 10 minutes to 1 hour to about 450 ℃ temperature at about 350 ℃ in stove.
Then, pass interlayer insulative layer 160 and form contact hole 170, this contact hole 170 has exposed source electrode and drain region 130b.In follow-up processing, form source electrode 180a and drain electrode 180b, these two electrodes are electrically connected to source electrode and drain region 130b (Fig. 2 F) by contact hole 170.
In the process of manufacturing TFT mentioned above,, require to carry out high thermal anneal process for the activation processing of semiconductor layer 130.At this moment, for example the distance that is diffused in the semiconductor layer 130 of metal ion can be by equation 1 expression for the impurity in the flexible substrate 100.
Equation 1
x＝(D
0exp(-E*/RT)t)
1/2
Wherein, x, D0, t, T and E* represent diffusion length, constant, diffusion time, temperature and energy barrier respectively.
Can notice that from equation 1 diffusion length x is temperature T in proportion to exponentially, and with time t
1/2Proportional.Therefore, temperature T when carrying out activation processing and time, can reduce the diffusion length x of impurity by reduction.
Fig. 2 A is the sectional view of illustration according to the leakage current of first execution mode to 2C.Table 1 illustration the video data of Fig. 2 A to 2C.With reference to Fig. 2 A to 2C instruction card 1.
Table 1
| Activation condition | Mobility (cm 2/Vs ) | The s-factor | I off，min | Vth(V) |
| 450 ℃, 2 hours | 43.0 | 2.19 | 1.160e -11 | -3.7 |
| 400 ℃, 2 hours | 38.0 | 1.65 | 6.31e -12 | -4.6 |
| 400 ℃, 0.5 hour | 49.3 | 1.08 | 2.51e -12 | -5.0 |
From Fig. 2 A to 2C and table 1 can notice, when the activation semiconductor layer processing under 450 ℃ temperature, carried out 2 hours, leakage current is 1.160e
-11Carried out under 400 ℃ temperature 2 hours when the processing of activation semiconductor layer, leakage current is 6.31e
-12In addition, when the processing of activation semiconductor layer was carried out 30 minutes under 400 ℃ temperature, leakage current was 2.51e
-12That is to say, shown in Fig. 2 C, when the processing of activation semiconductor layer is carried out 30 minutes under 400 ℃ temperature, the leakage current minimum.In one embodiment, annealing can carry out reducing in about 30 minutes leakage current under about 400 ℃ temperature.
Fig. 3 A is the sectional view of illustration according to the TFT of second execution mode to 3D.To 3D, at first provide flexible substrate 200 with reference to Fig. 3 A.In one embodiment, flexible substrate 200 is formed by SUS or Ti.
Then, on flexible substrate 200, form barrier layer or diffusion impervious layer 210.In one embodiment, barrier layer 210 can be by forming such as three-phase amorphous materialses such as TaSiN or TiSiN.Can form thickness by sputtering method is the diffusion impervious layer 210 of about 100nm to about 500nm.
Then, semiconductor layer 230 is formed on the resilient coating 220.At first, semiconductor layer 230 is formed by amorphous silicon.Then, thus carry out dehydrogenation and handle to make and do not have hydrogen in the amorphous si-layer.
Metal catalytic layer 250 is formed on the cover layer 240.Metal catalytic layer 250 can be formed on the cover layer 240.Metal catalytic layer 250 is annealed inductive material Ni deposition.The superficial density of Ni can be about 10
13With about 10
14Between atomicity/square centimeter.The Ni of metal catalytic layer 250 is used as the annealing inductive material, and forms the seed of examining as annealing on the interface of semiconductor layer 230, thereby forms crystal grain.In illustrated execution mode, Ni is used as metal catalytic layer 250.In other embodiments, metal catalytic layer 250 can comprise at least a (Fig. 3 A) that selects from the group of being made up of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd and Pt.
Then, flexible substrate 200 is by heating such as heater elements such as stove and rapid thermal annealing (RTA) or laser.Thermal anneal process is used to spread or permeate the Ni as the annealing inductive material of metal catalytic layer 250, thereby Ni is moved to interface between cover layer 240 and the semiconductor layer 230.Therefore, seed 231 is formed, thereby amorphous si-layer is crystallized into the polysilicon layer with crystal grain 232 by seed 231.
As indicated above, amorphous si-layer can be crystallized into polysilicon layer by the SGS method, and in the SGS method, cover layer and metal catalytic material are formed on the amorphous si-layer so that be annealed.In such execution mode, the size of crystal grain is between several microns and hundreds of microns, and crystal grain is very coarse.In addition, in crystal grain, be formed with as preventing the crystal boundary on the barrier layer that move in electronics or hole, thereby, along with the increase of crystallite dimension, electronics or hole can be easily by moving therebetween, and the speed in electronics or hole can increase.
After by thermal anneal process amorphous si-layer being crystallized into polysilicon layer, cover layer 240 and metal catalytic layer 250 are removed (Fig. 3 C).
Then, semiconductor layer 230 is patterned and gate insulator 260 is formed on the semiconductor layer 230.At this moment, gate insulator 260 can be formed by oxidation film or nitride film by the PECVD method.In one embodiment, gate insulator 260 can form about 500 to about 1000 thickness.
Gate electrode 270 is formed on the gate insulator 260.Gate electrode 270 has a kind of conducting metal that is selected among Al, Mo, Ta, Cr, Ti and the Cu, is formed on the gate insulator 260 by sputtering method.In one embodiment, the thickness of formed gate electrode 270 can be about 2000 to about 4000 , and is patterned into predetermined profile.
Then, interlayer insulative layer 280 is formed on the gate electrode 270.Form identical that the material therefor of interlayer insulative layer 280 and the method for being taked can be with formation gate insulator 260.
Source electrode 290a and drain electrode 290b are formed on the interlayer insulative layer 280, thereby are electrically connected to the source electrode and the drain region 230b of semiconductor layer 230 by being formed at contact hole 265 in gate insulator 260 and the interlayer insulative layer 280.Source electrode and drain electrode 290 can form by adopt photoresist on metal level, thereby are patterned into predetermined profile (Fig. 3 D).
Fig. 4 A and 4B are the sectional view of illustration according to the TFT of the 3rd execution mode.With reference to Fig. 4 A and 4B, this TFT comprises flexible substrate 300, barrier layer 310, resilient coating 320, semiconductor layer 330, gate insulator 340, gate electrode 350, interlayer insulative layer 360 and source electrode 370a and drain electrode 370b.
Because present embodiment is except the processing of activation semiconductor layer 330, therefore all the other structures hereinafter will only describe activation processing with identical to the execution mode that 1F describes above with reference to Figure 1A.The processing of activation semiconductor layer 330 was carried out about 30 seconds to about 2 minutes from about 500 ℃ to about 650 ℃ in temperature by rapid thermal annealing (RTA) method.The RTA method can use the IR lamp to carry out.When metal substrate by transient heating, metal substrate can within the several seconds, not be destroyed ground thermal annealing, even temperature is higher than the flow of metal point.
Shown in Fig. 4 A, resilient coating 320 can pass through lamination the one SiO
2Layer 320a and a SiNx layer 320b obtain.In another embodiment, shown in Fig. 4 B, resilient coating 320 can pass through lamination the one SiO
2Layer 320a, a SiNx layer 320b, the 2nd SiO
2Layer 320c and the 2nd SiNx layer 320d obtain.In one embodiment, a formed SiO
2The thickness of layer 320a can arrive about 1 μ m for about 200nm.The thickness of a formed SiNx layer 320b can arrive about 200nm for about 50nm.Formed the 2nd SiO
2The thickness of layer 320c can arrive about 1 μ m for about 50nm.The thickness of formed the 2nd SiNx layer 320d can arrive about 200nm for about 50nm.SiO
2The position of layer 320a and 320c and SiNx layer 320b and 320d can exchange.
Fig. 5 A is the sectional view of illustration according to the TFT of the 4th execution mode to 5C.To 5C, this TFT comprises flexible substrate 400, resilient coating 410, semiconductor layer 420, first insulating barrier 430, gate electrode 440, second insulating barrier 450 and source electrode 460a and drain electrode 460b with reference to Fig. 5 A.
In one embodiment, flexible substrate is by forming such as metal formings such as SUS or Ti.When flexible substrate 400 when forming such as the SUS metal forming, prevent resilient coating 120 then formation after forming TFT of diffusion of impurities.
In one embodiment, resilient coating 410 has two or more layers above flexible substrate 400.By using a kind of (for example ELA method) in the different method for annealing will be formed at the processing that amorphous si-layer on the flexible substrate 400 is transformed into polysilicon layer, resilient coating 410 prevents that diffusion of impurities is in semiconductor layer 420.Resilient coating 410 is by SiO
2Layer 410a and SiNx layer 410b form, like this, and formed SiO
2The thickness of layer 410a is that about 200nm arrives about 1 μ m, and the thickness of formed SiNx layer 410b is that about 50nm is to about 200nm.In another embodiment, SiO
2The position of layer 410a and SiNx layer 410b can exchange.
After forming LDD420b, photoresist (not shown) is used to by photolithography determines the contact hole doped region.Then, source electrode and the drain region 420c that is doped to semiconductor layer 420 at high density impurity reaches per unit area about 10
11To about 10
12Behind number of ions/square centimeter, photoresist is removed.Therefore, highly doped source electrode and drain region 420c and LDD420b are formed in the semiconductor layer 420.Comprise as final semiconductor layer 420: channel region 420a, there is not impurity substantially in it; LDD420b; And source electrode and drain region 420c, it is used to receive the signal of telecommunication.
The LDD420b of semiconductor layer 420 prevents that unexpected impurity from destroying the performance of TFT, even this impurity is diffused into the channel region 420a from flexible substrate 100.In addition, because LDD420b separates with gate electrode 440, be lowered to the electric field influence that gate electrode 440 is applied from source electrode and drain region 420c with homogeneous electromotive force.Therefore, when TFT was in closed condition, the leakage current that flows between source electrode and drain region 420c was lowered, and this has improved the close current performance of TFT.
First insulating barrier 430 is formed on the semiconductor layer 420.First insulating barrier 430 makes semiconductor layer 420 and gate electrode 440 insulated from each other.In one embodiment, oxidation film or nitride film are used as the insulating material of first insulating barrier 430.Yet this is not limited to material mentioned above.
Second insulating barrier 450 is formed on first insulating barrier 430 and the gate electrode 440.The formation material of second insulating barrier 450 can be identical with first insulating barrier 430.
On the other hand, can further between flexible substrate 400 and resilient coating 410, form barrier layer 405.When amorphous si-layer was crystallized into polysilicon layer, barrier layer 405 had prevented that effectively impurity is diffused in the semiconductor layer 420 by flexible substrate 400.In one embodiment, barrier layer 405 is formed by TiN, TiAlN and TaSiN, and thickness is that about 100nm is to about 400nm.In addition, can further form the 3rd insulating barrier 415, be received from the outside by the lower surface of flexible substrate 400 to prevent unexpected voltage and external noise.Therefore, even impurity is diffused into the channel region 420a from flexible substrate 100, LDD420b can prevent the mis-behave (Fig. 5 B) of TFT.
According to above-described execution mode, barrier layer and be introduced into by the two-layer at least resilient coating that obtains of lamination, activating treatment temperature and time are lowered.This structure has prevented that the impurity of flexible substrate is diffused in the semiconductor layer during the activation semiconductor layer.Therefore, leakage current can be lowered.
Though plurality of embodiments of the present invention is shown and describes, but can be understood that by those skilled in the art, can transform this execution mode, only otherwise exceed principle of the present invention and spirit, get final product by claims institute's restricted portion and their equivalent method.
Claims (21)
1, a kind of electronic device that comprises thin-film transistor, described device comprises:
Flexible substrate, it comprises sheet metal;
Semiconductor layer, it is formed at the top of described flexible substrate, and described semiconductor layer comprises source region, drain region and the channel region between described source region and described drain region;
Gate electrode, it is formed at the top of described semiconductor layer;
Gate insulator, it is between described gate electrode and described semiconductor layer;
Source electrode, it contacts described semiconductor layer;
Drain electrode, it contacts described semiconductor layer;
Resilient coating, it is between described flexible substrate and described semiconductor layer; And
Diffusion impervious layer, it comprises Ti or Ta, and between described flexible substrate and described resilient coating.
2, device according to claim 1, wherein, described sheet metal comprises one or more materials of selecting from the group of being made up of stainless steel (SUS) and Ti.
3, device according to claim 1, wherein, described diffusion impervious layer comprises one or more materials of selecting from the group of being made up of TiN, TaSiN, TiSiN and TiAlN.
4, device according to claim 1, wherein, the thickness of described diffusion impervious layer is approximately between 100nm and the about 500nm.
5, device according to claim 1, wherein, described resilient coating comprises from by SiO
2, one or more materials of selecting in the group formed of SiNx and SiNO.
6, device according to claim 1, wherein, the thickness of described resilient coating is approximately between 50nm and the about 2 μ m.
7, device according to claim 1, wherein, described resilient coating comprises two-layer or more multi-layered, every layer all comprises from by SiO
2, the material selected in the group formed of SiNx and SiNO.
8, device according to claim 7, wherein, described resilient coating comprises and comprises SiO
2Ground floor and comprise the second layer of SiNx.
9, device according to claim 8, wherein, described resilient coating further comprises and comprises SiO
2The 3rd layer and comprise the 4th layer of SiNx.
10, device according to claim 1, wherein, described semiconductor layer comprises organic semiconducting materials.
11, a kind of manufacturing comprises the method for the electronic device of thin-film transistor, and described method comprises:
The flexible substrate that comprises sheet metal is provided;
Form diffusion impervious layer above described flexible substrate, described diffusion impervious layer comprises Ti or Ta;
Above described diffusion impervious layer, form resilient coating;
Above described resilient coating, form semiconductor layer; And
Described semiconductor layer is carried out thermal annealing.
12, method according to claim 11, wherein, described sheet metal comprises one or more materials of selecting from the group of being made up of stainless steel (SUS) and Ti.
13, method according to claim 11, described diffusion impervious layer comprise one or more materials of selecting from the group of being made of TiN, TaSiN, TiSiN and TiAlN.
14, method according to claim 11, wherein, described resilient coating comprises from by SiO
2, one or more materials of selecting in the group formed of SiNx and SiNO.
15, method according to claim 11, wherein, described resilient coating comprises two-layer or more multi-layered, every layer all comprises from by SiO
2, the material selected in the group formed of SiNx and SiNO.
16, method according to claim 11, wherein, the temperature of described thermal annealing between about 350 ℃ and about 450 ℃ implemented about 10 minutes to about 1 hour time period.
17, method according to claim 11 further is included in described semiconductor layer is carried out before the thermal annealing, with doping impurity in one or more parts of described semiconductor layer.
18, method according to claim 11 further comprises successively:
Above described semiconductor layer, form cover layer; And
After forming described semiconductor layer, and before described semiconductor layer is carried out thermal annealing, form metal catalytic layer above tectal described.
19, method according to claim 18, wherein, described metal catalytic layer comprises select at least a from the group of being made up of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd and Pt.
20, method according to claim 11, wherein, described thermal annealing comprises rapid thermal annealing (RTA).
21, the electronic device that produces of a kind of method according to claim 11.
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| KR1020050109826A KR100729054B1 (en) | 2005-11-16 | 2005-11-16 | thin film transistor and fabricating method of the same |
| KR1020050109826 | 2005-11-16 | ||
| KR1020050115112 | 2005-11-29 | ||
| KR1020050115969 | 2005-11-30 | ||
| KR1020050120898 | 2005-12-09 |
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| US5112764A (en) | 1990-09-04 | 1992-05-12 | North American Philips Corporation | Method for the fabrication of low leakage polysilicon thin film transistors |
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| KR20040054441A (en) * | 2002-12-18 | 2004-06-25 | 한국전자통신연구원 | Method of forming a buffer dielectric layer in a semiconductor device and a manufacturing a thin film transistor using the same |
| KR100623228B1 (en) * | 2003-11-27 | 2006-09-18 | 삼성에스디아이 주식회사 | TFT, OLED having the TFT and fabrication method of the TFT |
| KR100611751B1 (en) * | 2004-05-03 | 2006-08-10 | 삼성에스디아이 주식회사 | fabrication method of Thin Film Transitor |
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Also Published As
| Publication number | Publication date |
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| KR100729054B1 (en) | 2007-06-14 |
| KR20070052137A (en) | 2007-05-21 |
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