CN1054469C - Method for forming a semiconductor device - Google Patents

Method for forming a semiconductor device Download PDF

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CN1054469C
CN1054469C CN93105438A CN93105438A CN1054469C CN 1054469 C CN1054469 C CN 1054469C CN 93105438 A CN93105438 A CN 93105438A CN 93105438 A CN93105438 A CN 93105438A CN 1054469 C CN1054469 C CN 1054469C
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film
gate electrode
semiconductor island
electrolyte
semiconductor
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CN1078068A (en
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山崎舜平
张宏勇
鱼地秀贵
安达广树
竹村保彦
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority claimed from JP4115503A external-priority patent/JP3071940B2/en
Priority claimed from JP5089117A external-priority patent/JPH06275646A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

An improved method for manufacturing an insulated gate field effect transistor is described. The method comprises the steps of forming a semiconductor film on an insulating substrate, forming a gate insulating film on said semiconductor film, forming a gate electrode on said gate insulating film with said gate insulating film inbetween, anoding said gate electrode in order to coat an external surface of said gate electrode with an oxide film thereof and applying a negative or positive voltage to said gate electrode with respect to said semiconductor film. Lattice defects and interfacial states caused by the application of a positive voltage during the anoding are effectively eliminated by the negative voltage application.

Description

Form the method for semiconductor device
The present invention relates to form a kind of method of semiconductor device, particularly make a kind of method of film-insulated grid field effect transistor.Can on glassy dielectric substrate, form thin-film transistor on the substrate on the monocrystalline silicon Semiconductor substrate and similarly.
Recently, have in the insulated-gate semiconductor device of film active layer (active area) in research.Make earnest efforts to study a kind of thin-film insulated gate transistor that is called thin-film transistor especially.It is defined as non-crystalline silicon tft, crystalline silicon TFT according to used semi-conductive material crystallization condition.
Crystalline semiconductor is compared with non-crystalline semiconductor, has bigger field mobility and high speed operation.NMOS TFT can not only be made by crystalline silicon, also PMOSTFT can be made.Owing to can form cmos circuit, make TFT so make earnest efforts the research and utilization crystalline silicon now.
See by the achievement that obtains at present, in forming this insulated gate device, make grid insulating film with the silicon thermal oxidation film and can obtain only characteristic.Yet will obtain thermal oxide film needs under about 1000 ℃ film to be heated.Backing material used under of this sort temperature is restricted.In the formation of similar this TFT, adopt sputtering method and various chemical vapor deposition method (CVD) to form insulation film.
Do not need such high temperature owing to form this insulation film, therefore unrestricted to backing material.On the other hand, the problem of existence is that this insulation film made from vapor deposition method has high interface state density and many defectives that resembles this class of pin hole.Remedying and, not being to take, but mainly adopting only deposition conditions to solve this class defective in the thin film deposition reprocessing to the improvement of performance.
Recently, researcher's interest is to improve the exhausted grid field effect transistor (TFT) of film.For example, in the flat 4-38637 of another Japanese patent application NO. of flat 4-30220 of Japanese patent application NO. or same applicant, recommended, used Al, Ti, Cr, Ta, or silicon makes gate electrode, and with their outer surface of sull covering grid electrode.Make mask with anodised gate electrode, with the source region and the drain region of ion implantation formation device, like this, source region and drain region are positioned at from the laying backward of gate electrode edge, make and form so-called off-set construction between them.Then laser annealing being carried out in the source region of device and drain region handles and makes its recrystallization.
Transistor AND gate with this off-set construction has with silicon, tantalum or chromium makes gate electrode and those transistors of not having an off-set construction are compared, and has good characteristic.Yet it is not so high using the repeatability in this case of off-set construction.The reason of low repeatability is, high voltage is added to makes it on the gate electrode in the anodised process, semiconductor region also is under the high electric field, thereby many trap energy level attitudes in semiconductor, have been produced, although will not be added on the semiconductor region in the electric field reality, yet the high-tension influence owing to being added on the gate electrode has also produced one 20 to 150V film voltage on semiconductor.
With reference now to the Fig. 1 (A) that shows existing transistor cutaway view, the problem that exists is described.Transistor comprises glass substrate 101, the semiconductive thin film 102 that on glass substrate 101, forms, the gate electrode 104 that on semiconductive thin film 102, forms and with gate electrode 104 anodic oxidations of aluminum aluminum oxide film 105 with covering grid electrode 104 by gate insulating film 103.Anodic oxidation is achieved in that the gate electrode 104 to being in the electrolyte adds a high positive voltage, and electrolyte is by a suitable electrode grounding.At first, anodic oxidation just begun the electric field that will be produced in electrolyte mainly around gate electrode.In this stage, the voltage that is connected in parallel on the semiconductive thin film 102 is not so high, and when the oxide thickness thickening, electric field concentrates on the oxide film, thereby the voltage that is connected in parallel on the grid insulating film increases, and makes electronics inject the grid insulating film 106 below gate electrode 104 just.
When the described method of flat 4-30220 of Japanese patent application NO. or the flat 4-38637 of NO. of pressing formed oxide-film, the thickness of oxide-film 105 for example was 300 to 400nm.The thickness of gate insulating film 103 for example is 100nm.In this case, suppose that the resistivity of silica and the resistivity of aluminium oxide are equal to each other, even the semiconductor region 102 of supposition below grid insulating film 103 is intrinsics, and has certain resistivity, thereby produced voltage drop thereon, made the electric field in the grid insulating film 103 surpass the voltage drop that is connected in parallel on the aluminum oxide film 105.Because this high electric field can not continue anodization under the situation of not damaging grid insulating film 103.
In addition, for preventing undesirable influence to the glass substrate under the semiconductive thin film 102, the bottoming insulation film of shape one deck between glass substrate 101 and semiconductive thin film 102 as the silicon oxide film, must pay special attention to the silicon oxide film of bottoming and the structure of semiconductive thin film, for example, must form silicon oxide film in order not contain removable ion.Bigger harm is the existence of capturing attitude.With clean removable ion is limited to a certain degree.But, can not solve the problem relevant with capturing attitude at all.Because this problem is that the total restriction to technology causes.Silicon oxide film 103 and the interface state density between following semiconductor layer 102 are the key factors of decision transistor characteristic.Carrying out on the single crystal semiconductor substrate under the situation of MOS technology, single crystal semiconductor and the interface state density between the grid oxidation film that thermal oxidation method on the semiconductor forms are 10 10Cm -2The order of magnitude.On the other hand, under the situation of thin-film transistor,, corresponding semiconductor is deposited on the oxide film that forms with plasma CVD, atmospheric pressure CVD or low pressure chemical vapor deposition method, so interface state density is up to 10 because being form with polysilicon 12Cm -2Or it is higher.The too high transistor that causes of this interface state density can not be practical.That is to say,, make and capture some charge carriers at the interface, and make the conduction type of semiconductor region and gate voltage irrelevant, the leakage conductance electric current is increased if interphase density is so high.Therefore, for grid insulating film, must constitute and have desired high-quality bottoming silicon oxide film, using sputtering method, or ecr plasma CVD method forms under the situation of silicon oxide film, can not carry out thermal oxidation with middle temperature or low temperature, interface state density is than the high order of magnitude of interface state density with the thermal oxidation situation, thereby similar problem is inevitable.
The purpose of this invention is to provide a kind of method of making the film-insulated grid field effect transistor of improvement.
Another object of the present invention provides a kind of method of film-insulated grid field effect transistor of the manufacturing improvement with high qualification rate.
Further purpose of the present invention provides the method for film-insulated grid field effect transistor that a kind of manufacturing has the improvement of highly reliable grid insulating film.
Of the present invention more further purpose provide a kind of method of making the film-insulated field-effect transistor of the improvement that trapped electron and lattice defect got rid of from grid insulating film.
Other purposes of the present invention, the advantage and the new feature of invention will be described hereinafter, and the those of ordinary skill of the industry is after through checking, and the part that has can become apparent or by practice of the present invention being understood the purpose and the advantage of invention.Purpose of the present invention can by means of and realize in conjunction with the content that particularly points out in the appending claims.
For realizing above-mentioned purpose of the present invention and other purposes, here it is done specifically and widely to describe, a kind of method of making isolated-gate field effect transistor (IGFET) comprises operation: form semiconductive thin film on a dielectric substrate, on said semiconductor, form grid insulating film, on said gate insulating film, form gate electrode, said grid insulating film is between semiconductor film and gate electrode, be outer surface with the oxide film covering grid electrode of gate electrode, gate electrode is carried out anodic oxidation, and add a negative voltage for said gate electrode with respect to semiconductive thin film.As hereinafter being described in detail, adding the negative electricity pressure energy and eliminate effectively and in anodic oxidation, add lattice defect and the interfacial state that positive voltage causes.
With reference now to showing that institute's making alive concerns on band structure and the gate electrode Fig. 1 (B) illustrates basic mechanism of the present invention to 1 (E).The voltage level of gate electrode is very high in the anode oxidation process, so energy level is very low, makes it produce a high electric field that is connected in parallel on the grid insulating film, shown in Fig. 1 (B).Because high electric field makes electronics and grid insulating film collision, produces lattice defect, and in grid insulating film, special being captured at the interface between semiconductor region and gate insulating film.When gate insulating film was made with silica, the generation of capturing with lattice defect of electronics was tangible.
Even being removed back electron capture and lattice defect from gate electrode, high voltage still keeps, shown in Fig. 1 (C).Transistorized channel characteristic is influenced by trapped electron mainly.For example, if device is the P-channel transistor, semiconductor region just below grid insulating film, that is to say that channel region is transformed into P-type district and allows drain circuit to pass through thus.If device is the N-channel transistor, threshold voltage is to positive excursion.
According to the present invention, be parallel on the grid insulating film for producing a reversed electric field, after anodization, add a negative voltage to gate electrode.Because the electronics that the effect of negative voltage makes in the grid insulating film and captured is disengaged, shown in Fig. 1 (D).Meanwhile, the hole of being introduced by negative voltage is cancelled lattice defect.According to said method, band structure is recovered normal condition after removing negative voltage, shown in Fig. 1 (E).The work that adds negative voltage after the anodic oxidation can be repeated several times if desired.Become under the situation about also can remedy basically before serious adding damage that positive voltage causes for semiconductor region and grid insulating film, add negative voltage and can eliminate this damage.
Adding negative voltage can carry out in the electrolyte that the gate electrode anodic oxidation is used.In this case, semiconductor region is electrically connected with negative electrode fully by electrolyte, finishes the special wiring required with being connected of semiconductor region because of not forming at needs.In addition, adding negative voltage can carry out after substrate is removed from electrolyte.Yet, under the situation that forms a plurality of semiconductor regions that separate on the substrate, in adding the process of negative voltage, must semiconductor region integrally be connected on the positive level with respect to gate electrode with the i.e. wiring of a three-dimensional of special jockey.In addition, from production cost and qualification rate viewpoint, it is desirable adding negative voltage in electrolyte.And if add negative voltage to gate electrode in electrolyte, then hydrogen ion can enter in semiconductor region and the grid insulating film.For example, connect dangling bonds to reduce lattice defect with hydrogen ion.
By the preferred embodiments of the present invention, because gate electrode remains in the electrolyte under negative voltage, electrolyte helps to reduce oxide film that anodization generates and dissolve gate electrode, therefore, the most handy aluminium of gate electrode, titanium, tantalum form, make it not have enough anti-reduction abilities, but can not form gate electrode with those metal such as copper, zinc and silver that is difficult for reduction.When forming gate electrode, should add negative voltage at electrolyte with the said metal in back.
In another kind of method of the present invention, be the voltage V on the gate electrode that to be added to below the gate electrode oxide film CGRemain to a suitable value, to realize current processing, for example voltage V CGBe 30 to 80V.
Find that when adding positive voltage or negative voltage between gate electrode and transistor, the characteristic of TFT has very big improvement in inventor's research.This acting on hereinafter is referred to as current processing or current annealing.With regard to institute's making alive, not the effect that the voltage of both positive and negative type can both play current processing.For example, (source, leakage are the N types) just must add positive voltage to gate electrode under the situation of N channel TFT.P-channel TFT (source, leakage are under the situation of P type, and gate electrode is preferably added negative voltage).
There are two factors to play this current processing effect.Factor is electrochemical action and buried the pin hole of oxide-film.This is the ion transport phenomena (mainly being oxonium ion) in grid insulating film.If grid insulating film is inhomogeneous, make the ion migration with alive method, make inhomogeneous part smooth.Consequently the uniformity of grid insulating film improves among the TFT.
Another factor is to use current flow heats, and in fact annealing down with high temperature has same effect.In this state, fixed charge is removed, and the dangling bonds of ion and the dangling bonds of silicon are connected with each other, and interface state density is reduced.This high annealing effect need make temperature on the entire substrate at about 1000 ℃ high temperature, but will realize that current processing only need make entire substrate in room temperature or in cold liquid.Yet, the energy level (about 0.1ev) that insulation film carries out among a small circle on a small scale corresponding to 1000 ℃ is handled.
Figure 10 is that source, the leak of a TFT depressed and alive state diagram between source, leakage and gate electrode in same electrical.[Figure 10 (A)-(D)].Figure 10 (A) and (C) be the energy band diagram of locating along A-A ' among Fig. 5 (A).Figure 10 (B) and (D) be the energy band diagram of locating along B-B ' among Fig. 5 (A).Source and leak is not doped, and the same with active area below the gate electrode is Intrinsical.Figure 10 (A) and (B) expression added the gate electrode of positive voltage.Figure 10 (C) and (D) expression added the gate electrode of negative voltage.In both cases, because alive effect enables band crooked near the precipitous ground of gate electrode and grid insulating film place.Can be with formation one degree of depth to reverse in a side near the silicon at the interface of silica and silicon.As Figure 10 (A) with (C), can be with precipitous portions of electronics and hole to be accelerated; And it is compound mutually by the complex centre.They are by this compound function and local luminous that loses then.The compound mutually or counteracting of dangling bonds then.As Figure 10 (B) with (D), the interface into grid insulating film of crashing is passed in high energy electron and hole from semiconductor inside.These electronics and hole and lattice collision also produce a large amount of amount of localized heat.
This effect is clearly confirmed by experiment, but realizes that as the basis a large amount of production is difficult with this.Problem is how voltage to be added on semiconductor region and the gate electrode.
In the experiment gate electrode is connected respectively with electric wire with semiconductor region.And this method just can not be used in a large amount of production.About this problem, the present invention has found out an idea with room temperature electrolyte or cold electrolyte.This electrolyte also has cold acupoints (cold medium), to prevent local overheating and permanent the puncture.This operation brief description is as follows.Fig. 5 (A) illustrates a TFT element.This TFT is formed on the insulation film 2 of substrate 1 and bottoming, comprises an island shape semiconductor region 3, one deck grid insulating film 4 and a gate electrode 5.One deck insulation film 6 is arranged on the gate electrode 5.This insulation film 6 is extremely important in the electrolyte of usefulness.These insulation film 6 common oxide-films that preferably gate electrode carried out anodic oxidation and form.
Although only draw a TFT among the figure, many TFT independent of each other can be arranged on same substrate.Making alive makes between the top of grid insulating film and the bottom and produces potential difference on the gate electrode.Realize current processing with this method.
Fig. 5 (B) has provided the equivalent electric circuit of this TFT.Gate electrode potential is VG.Seen two loops from gate electrode: a loop is to pass insulation film 6 (resistance R 1) arrival electrolyte; Another loop is by grid insulating film 4 (resistance R 2) following gate electrode, semiconductor region 3 (resistance R 4), grid insulating film 4 (resistance R 3) reach electrolyte again.Obviously, controlling resistance R 1, R 2, R 3And R 4Resistance value can select to be added to voltage V on the gate electrode below the grid insulating film CGOptimum value.
If do not have insulation film 6, then R 1=0, because R 1=0, V CG=0, that is to say not have making alive on the grid insulating film.Thereby insulation film 6 must be arranged.As shown in circuit, if R 1＜R 2+ R 3+ R 4, V CGJust less than the voltage that is added on the insulation film 6.Learn from experiment, for obtaining big like this voltage, V CGMust can increase R on demand at 30-80V 1With reduce R 3
More particularly, the insulation film 4 on the semiconductor region 3 should integrally be done thinly, or can partially or completely be removed, except the following zone that gate electrode arranged.For example, if all be removed R 3=0, V CGThe a large amount of increase.It also is effective making insulation film 6 thickenings.Consequently be added to the voltage V on the gate electrode GDo not increase and much just can carry out processing of circuit effectively.N channel-type TFT must add positive voltage, and P channel-type TFT must add negative voltage.
If make insulation film 6 with the anode oxide film of gate material, then should make gate electrode with aluminium, tantalum, silicon, titanium, tungsten, chromium and analog.Want to guide equably reaction, this electrolyte should be remained under the constant temperature.Because electrolyte has heat diffusion capabilities (cooling), thereby can prevent the puncture that causes because of local overheating.
Figure 11 carries out the employed device schematic diagram of current processing for the present invention.Filled with electrolyte 8 in the electrolysis tank 7.Substrate 9 and the electrode 10 made with oxidation resistant platinum, palladium and analog thereof are immersed in the electrolyte 8.The immersion method of substrate has two kinds.A kind of is directly to immerse in the electrolyte, shown in Figure 11 (A); Another kind method is substrate 9 to be fixed on substrate support plate 9A go up in the immersion electrolyte, shown in Figure 11 (B).On the exit A, the B that stretch out by this electrode and substrate, add positive voltage or negative voltage.
Accompanying drawing comprises in the present invention and constitutes the part of invention, and accompanying drawing and specification one are used from the principle of explanation invention.
Fig. 1 (A) is the profile of the film-insulated grid field effect transistor of prior art.
Fig. 1 (B) is the band structure schematic diagram of the film-insulated grid field effect transistor made by the inventive method to 1 (E).
Fig. 2 (A) is the profile of the film-insulated grid field effect transistor made by first embodiment of the present invention to 2 (D).
Fig. 3 (A) is the profile of the film-insulated grid field effect transistor made of second embodiment of the present invention to 3 (D).
Fig. 4 (A) to 4 (E) be profile by the 3rd the film-insulated grid field effect transistor that embodiment makes of the present invention.
Fig. 5 is a schematic diagram of the present invention.
Fig. 6 is the profile of the manufacturing process of the 4th embodiment of expression.
Fig. 7 is the profile of the manufacturing process of the 5th embodiment of expression.
Fig. 8 is the profile of expression through the manufacturing process of six embodiment.
Fig. 9 is the profile of the manufacturing process of the 7th embodiment of expression.
Figure 10 is the energy band diagram of expression current processing.
Figure 11 is the installation drawing that carries out current processing.
With reference now to Fig. 2 (A), the manufacture method of the complementary thin-film isolated-gate field effect transistor (IGFET) of pressing first embodiment of the present invention is described to 2 (D).
Make substrate 201 with an inexpensive glass plate, glass plate is the N-O glass plate of being made by Nippon electric glass Co., Ltd.Glass plate is the glass with high deformation temperature and the rich sodium of rich lithium.For stopping lithium ion and sodium ion, on substrate, form one deck silicon nitride film 202.With silicon nitride film 202 thickness of plasma CVD method deposit is 10 to 50nm.On silicon nitride film be one deck silicon oxide film 203 of 100 to 800nm then by same mode deposition thickness with sputtering method.It with plasma CVD method deposition thickness on silicon oxide film 203 20 to 100nm the armorphous semiconductive thin film of one deck.Then semiconductive thin film thermal anneal process through 12 to 72 hours under 600 ℃ is made its recrystallization, and constitute a plurality of semiconductor island 204 and 205 figures with photoetching process and reactive ion etching (RIE).With silica is that target sputtering deposit thickness in oxygen atmosphere is one deck silicon oxide film 206 of 50 to 200nm.Is 2 to 20nm with plasma CVD method or low pressure chemical vapor deposition method by same mode deposition thickness,, preferably thickness is one deck silicon nitride film 207 of 8 to 11nm, makes it constitute a pair of grid insulating film with silicon oxide film 206.On silicon nitride film 207, form the layer of aluminum film with sputtering method or electron-beam vapor deposition method, and be that etching agent is made gate electrode 209 and 210 and essential lead 208 and 211 figure with the mixed acid that the nitric acid that adds 5% in the phosphoric acid is made.On substrate, make transistorized essential member with said method.
In order to form aluminum oxide film 212,213,214 and 215, to the outer surface anodic oxidation of gate electrode 209,210 and lead 208,211.That is to say that the substrate that will have gate electrode 209,210 and lead 208,211 is made anode, is immersed in the electrolytic cell with the suitable electrode as negative electrode.Japanese patent application NO, flat 4-30220 antianode oxidizing process has been made detailed description.The practical structures of anodization system and anodic process are by the transistor desirable characteristics, and factors such as technological requirement, scale of investment determine.How negative voltage is added on gate electrode 209,210 and the lead 208,211 with following this embodiment explanation of the present invention.
At first, the speed with 10 volts of per minutes makes the voltage on gate electrode 209,210 and the lead 208,211 rise to 300 volts from 0.Kept 1 hour when the voltage on being added to gate electrode 209,210 and lead 208,211 reaches 300 volts, make gate electrode 209,210 and lead 208,211 anodic oxidations, forming the thickness that covers on it is the aluminum oxide film 212,213,214 and 215 of 350nm.Then the voltage on gate electrode 209,210 and the lead 208,211 is reduced negative voltages-30 volts extremely-100 volts from 300 volts.Preferably-35 volt to-50 volts, pressure decay rate is 10 volts of per minutes.Electron capture that causes in the anodic oxidation and lattice defect are being eliminated with the method that adds negative voltage subsequently.
Secondly, in semiconductor island district 204 and 205, form source region and drain region 216 and 217 according to known CMOS manufacturing technology with ion implantation.That is, the phosphonium ion with 110Kev (kilo electron volt) injects semiconductor island district 204.And gate electrode 209 and aluminum oxide film 213 coverings are semiconductor island mid portions of channel region.The boron fluoride ion-implanted semiconductor island 205 that uses the same method and to have 80Kev.Do not cover at aluminum oxide film 213 and 214, have apart from the gate electrode edge in the so-called off-set construction of certain distance to form source region and drain region 216 and 217, shown in Fig. 2 (C).
Owing to ion injects destroyed basically amorphous state or the very approaching amorphous polycrystalline attitude of becoming of degree of crystallinity that makes source region and drain region 216 and 217, therefore it is carried out laser annealing and make it at source region and drain region recrystallization.The flat 4-30220 of Japanese patent application NO. is described the condition of laser annealing.The heating anneal that can be used under 600 ℃ to 850 ℃ replaces laser annealing.Annealing after annealed substrate put into again hydrogen (air pressure is 1 to 700 torr, preferably 500 to 700 torrs) under 250 to 450 ℃ through 30 minutes to 3 hours again annealing.Make hydrogen atom enter semiconductor region with this hydrogen annealing method, reducing lattice defect, as if dangling bonds is stopped.
Silica interlayer film 218 with sputtering deposit covers this structure then.Open suitable contact hole with photoetching process, pass silicon oxide film 218, silicon nitride film 207 and silicon oxide film 206 expose source region and drain region 216 and 217.Last deposit aluminium or chromium thin film and needle drawing constitute the essential lead that comprises source electrode and drain electrode 220 that is connected with the drain region by contact hole and source region.
With reference now to Fig. 3 (A), the manufacture method of the complementary thin-film isolated-gate field effect transistor (IGFET) of pressing second embodiment of the present invention is described to 3 (D).
Make substrate 301 with a kind of inexpensive glass plate.Glass plate is the Corning7059 glass of being made by Corning Co., Ltd.On substrate, form one deck silicon nitride film 302 to suppress removable ion.The thickness of the silicon nitride film 302 of institute's deposit is 5nm to 200nm.For example use the thick silicon nitride film of RF plasma CVD method deposit 10nm.Being the silicon oxide film 303 of 200nm to 1000nm with identical method deposition thickness on silicon nitride film then, is the silicon oxide film of 50nm with RF plasma CVD method deposition thickness for example.Should and determine according to the tendency of the removable ion that prevents to pass it thickness of silicon nitride film 302 and silicon oxide film 303 influence of the semiconductive thin film on next procedure is formed on it.Certainly, these films 302 and 303 can be used the other technologies deposit.Low pressure chemical vapor deposition for example, sputter and similar deposition technology, but should be according to scale of investment, factors such as mass-produced efficient are selected.These films can deposit continuously in same deposition chamber.
At first, deposit one layer thickness is 20 to 200nm amorphous semiconductor film 304 on silicon oxide film 303, for example, be 430 to 450 ℃ at underlayer temperature, using the low pressure chemical vapor deposition deposition thickness of the reacting gas of forming with single silane is the amorphous semiconductor layer of 100nm.On ground floor semiconductive thin film 304, under 520 ℃ to 560 ℃ different temperatures,, form thickness and be 5 at underlayer temperature to 200nm for example at 550 ℃ of following consecutive depositions, for example be the second layer amorphous semiconductor film 305 of 10nm, shown in Fig. 3 (A).Studies confirm that through the inventor underlayer temperature mainly influences the crystallization process again of semiconductive thin film subsequently.For example, semiconductive thin film be not higher than deposit on 480 ℃ the substrate, then semiconductive thin film recrystallization difficulty.On the contrary, when semiconductive thin film is to be not less than deposit under 520 ℃ the underlayer temperature, then realize recrystallization easily.
Then semiconductive thin film 305 is made its recrystallization through 24 hours thermal anneal process under 600 ℃, make it be transformed into so-called half amorphous semiconductor film.Yet, be embedded in following semiconductive thin film 304 and remain amorphous state.In order to make semiconductive thin film 305 realize recrystallization effectively, the carbon atom that exists in the semiconductive thin film 305, the density of nitrogen-atoms and oxygen atom should not be higher than 7 * 10 respectively 19Cm -3The density that records respectively in the test is not higher than 1 * 10 17Cm -3These semiconductive thin films 304 and 305 usefulness photoetching and corrosion technology composition form a plurality of semiconductor islands 306 and 307.Use the top film of each semiconductor island of intrinsic semiconductor main composition then.Deposition thickness is the silicon oxide film 310 of 50-300nm, for example, makes the target silicon oxide film that sputter 150nm is thick in oxygen atmosphere with silica and constitutes grid insulating film.On silicon oxide film 310, form the aluminium film with sputtering method or electron beam evaporation, and form the lead of not drawing among gate electrode 311,312 and the essential figure with adding mixed acid corrosion composition that 5% nitric acid forms in the phosphoric acid.40 ℃ of following corrosion rates is 225 mm/min.To determine to be arranged in the channel length and the channel width of 8 millimeters of the length of following semiconductor island 306 and 307 be 20 microns to the gate electrode of Xing Chenging then, shown in Fig. 3 (B).
For forming the outer surface anodic oxidation of the aluminum oxide film 313 and the 314 pairs of gate electrodes 311,312 and lead.The substrate that is about to have gate electrode 311,312 and lead is made anode, immerses in the electrolyte with the suitable electrode as negative electrode.Anode oxidation method describes in detail in flat 3-231188 of Japanese patent application NO or the flat 3-238713 of NO..The practical structures of anodic oxidation system and technical process depend on transistorized desirable characteristics, technological requirement and scale of investment or the like factor.Add negative voltage for gate electrode 311,312 and lead by this embodiment of the present invention subsequently.
At first, adding 10 volts speed by per minute makes the voltage on gate electrode 311,312 and the lead increase to 300 volts from 0.Voltage on gate electrode 311,312 and lead reaches 300 volts, keeps 1 hour under this state, and making gate electrode 311,312 and lead anodic oxidation form the thickness that covers on it is the aluminum oxide film 313 and 314 of 350nm.Then, make voltage on gate electrode 311,312 and the lead from 300 volts of negative voltages that are reduced to-30 volts to-100 volts, preferably-35 volt to-50 volts with the speed of 10 volts of per minutes.Electron capture that produces in the anodic oxidation and lattice defect have been eliminated with added negative voltage.
Secondly, in semiconductor island 306 and 307, form source region and drain region 315 and 316 by known CMOS manufacturing technology with ion implantation, promptly, phosphonium ion with 110Kev injects semiconductor island 306, and gate electrode 311 and aluminum oxide film 313 cover the mid portion of the semiconductor island that is channel region.To have in the same way in the boron fluoride ion-implanted semiconductor island 307 of 80Kev.Do not cover at aluminum oxide film 313 and 314, have apart from the gate electrode edge in the so-called off-set construction of certain distance to form source region and drain region 315 and 316, shown in Fig. 3 (C).
Can replace ion to inject with ion doping technique and form source region and drain region 315 and 316.And the situation of big substrate is handled without ion implantation usually.Handle with ion doping equipment for 30 inches of diagonal angle line lengths or bigger substrate.In ion doping technique, do not need hydrogen ion is quickened and introduces in the film, thereby substrate temperature tends to raise widely, thereby be difficult to select photoresist mask to be used as the ion injecting mask.
Because injecting, ion make the degree of crystallinity of source region and drain region 315 and 316 destroyed basically, therefore become amorphous state or approached amorphous polycrystalline attitude, therefore laser annealing be need carry out, the source region and the drain region recrystallization that have the gate electrode 311,312 that covers with oxide film 313,314 made.The condition of laser annealing is open in the flat 3-231188 of Japanese patent application NO. and 238713.This structure covers with the silica interlayer film 319 of RF plasma CVD deposit.Open suitable connecting hole with photoetching process, expose source region and drain region 315 and 316 by silicon oxide film 319 and silicon oxide film 310.Last deposit and composition aluminium film form and pass the essential lead that comprises source electrode and drain electrode 320 to 322 that connecting hole and source region and drain region 315 link to each other with 316.
The energy of laser annealing should be high to making second layer semiconductor film 304 recrystallizations, constitutes the homogeneously crystallized source and the leakage of full thickness as ground floor semiconductor film 305.Yet, by second embodiment of the present invention, the thickness of source region and drain region 316 and 315 is about 100nm, because exist the irrelevant ground floor semiconductive thin film 304 of gate electrode and laser annealing still to be amorphous state, therefore the thickness of the channel region below gate electrode 312 and 311 is that 10nm is so little just.Consequently, the face resistance value of source region and drain region 316 and 315 reduces, and the cut-off current that passes channel region is limited basically.In addition, can avoid undesirable influence of capturing attitude of producing in interfacial state between semiconductive thin film and the following silicon oxide film and the silicon oxide film below in this case.The semiconductive thin film 305 that promptly plays the channel region effect does not directly contact with silicon oxide film 303, but does not directly contact contacting between the semiconductor film that only do not play the raceway groove effect between the right and wrong crystalline state semiconductive thin film 304 and the silicon oxide film.The inventor's experiment shows, unless the interface state density between silicon oxide film 303 and the amorphous semiconductor film 304 surpasses 5 * 10 12Cm -2, otherwise undesirable influence can not appear.
With reference now to Fig. 4 (A), the manufacture method of the complementary thin-film isolated-gate field effect transistor (IGFET) of pressing the 3rd embodiment of the present invention is described to 4 (E).
Make substrate 401 with the inexpensive glass plate, for example glass plate is the N-O glass plate of being made by Nippon electric glass Co., Ltd.On substrate, form silicon oxide film 402.It with plasma CVD or low pressure chemical vapor deposition deposition thickness 100 to 800nm silicon oxide film 402.On silicon oxide film 402, be 20 to 100nm amorphous semiconductor films with the plasma CVD deposition thickness.Then semiconductive thin film is made its recrystallization through 12 to 72 hours thermal annealings under 600 ℃, form a plurality of semiconductor island 403 that N-raceway groove and P-channel fet use and 404 figure with photoetching and reactive ion etching (RIE).In order to form grid insulating film, be that target sputtering deposit thickness in oxygen is 50 to 200nm silicon oxide film 405 with the silica.On silicon oxide film 405, form the aluminium film with sputtering method or electron beam evaporation, and be etched into composition shape gate electrode 406 and 407 and essential lead (not drawing among the figure) with the mixed acid that the nitric acid that adds 5% in the phosphoric acid is made.On substrate, make transistorized requisite component part with above-mentioned technology, shown in Fig. 4 (A).
In order to form the aluminum oxide film 408 and the 409 pairs of gate electrodes 406 and 407 and the outer surface anodic oxidation of lead, shown in Fig. 4 (B).That is, the substrate that has gate electrode 406,407 and lead is made anode, immerses in the electrolyte with the suitable electrode of making negative electrode.The antianode method has been done detailed description among the flat 4-30220 of Japanese patent application NO..The practical structures of anodization system and anodic process depend on transistorized desirable characteristics, technological requirement, scale of investment or the like factor.
Open the connecting hole of peroxidating silicon thin film 405 then.Structurally deposit chromium thin film and composition are so that the electrode 411 and 412 that is electrically connected with semiconductor island 403,404 to be provided, shown in Fig. 4 (C).Give 30 volts to 100 volts of electrode 411 and grounding electrode 412 making alives respectively, preferably 35 volts to 50 volts, making the electric current by semiconductor island 403 is 1 hour.Self-heating that electric current causes and electromigration make semiconductor island annealing.In self-heating and electromigration annealing, on gate electrode 406 and 407, add negative voltage-30 to-100 volts.Preferably-35 volt to-50 volts one hour.Adding in the process of negative voltage with wavelength is 300 to 350nm the ultraviolet ray lower surface irradiating structure by substrate.Ultraviolet power density be 100 to 300 milliwatts/centimetre 2Electron capture that causes in the anodic oxidation and lattice defect add negative voltage with method same as the previously described embodiments to be eliminated.Make it better with ultraviolet irradiation under this situation.
Secondly, in semiconductor island 403 and 404, form source region and drain region 403 and 404 by known CMOS manufacturing technology.That is, inject semiconductor island 403, and gate electrode 406 and aluminum oxide film 408 cover the mid portion of the semiconductor island that is channel region with phosphonium ion with 110Kev.Use the same method in the boron fluoride ion-implanted semiconductor island 404 that will have 80Kev, unshielded at aluminum oxide film 408 and 409, in the so-called off-set construction that the gate electrode edge has, form source region and drain region 413 and 414, shown in Fig. 4 (D).
Substantially destroy and become amorphous state or approach amorphous polycrystalline attitude owing to ion injects the degree of crystallinity make source region and drain region, use the mode identical that laser annealing is carried out in source region and drain region and make its recrystallization with first embodiment.The flat 4-30220 of Japanese patent application NO. openly sends out the condition of laser annealing.After the annealing, substrate is in hydrogen (pressure is 1 to 700 torr, is preferably 500 to 700 torrs) again, at 250 to 450 ℃ through 30 minutes to 3 hours annealing in process.Make hydrogen atom enter semiconductor region and reduced lattice defect with this method for annealing in hydrogen, make unsettled strong termination as resembling.
Sputtering deposit one deck silica interlayer film 415 covered structures then.Open the suitable connecting hole of peroxidating silicon thin film 415 and 405 with photoetching process, expose source region and drain region 413 and 414 and the grid lead.Last deposit aluminium film or chromium thin film and composition form the essential lead that comprises source electrode and drain electrode 417 and 416 that is connected with the drain region by connecting hole and source region.
With reference now to Fig. 6 (A), the manufacture method of the semiconductor device of pressing the 4th embodiment of the present invention is described to 6 (F).This embodiment is the Production Example of N channel TFT.At first, go up the silica bottom layer film 12 of thick 2000 of deposit at substrate 11 (Corning 7059 glass) with sputtering method.In addition, be for example intrinsic of 1500 (I type) amorphous silicon films of 500 to 1500 with the plasma CVD method deposition thickness, and with the silicon oxide film of sputter or thick 200 of similar approach deposit thereon.Amorphous silicon film under 600 ℃ in nitrogen through 48 hours crystallization treatment.
After the Crystallization Procedure,, form island silicon area 13 to the silicon thin film composition.Then sputtering deposit thickness be the silicon oxide film of 1000 as grid insulating film, be target with the silica in the sputter.Underlayer temperature in the sputter is 200 to 400 ℃, for example is 250 ℃, and sputtering atmosphere is oxygen and argon, and argon/oxygen=0-0.5 for example is 0.1 or littler.
Deposition thickness is 1000 to 10000 , for example is the siliceous 0.5 to 3% of 5000 , for example 2% aluminium film.Wish silicon oxide deposition film and aluminium film continuously.Corrode this aluminium film with the mixed acid that mainly is phosphoric acid, form gate electrode 15 (Fig. 6 (A)).
Substrate is immersed in the ethylene glycol solution that contains tartaric acid (1-5% neutralizes with ammoniacal liquor).Add positive voltage to gate electrode, feed electric current, the anodic oxidation film (aluminium oxide) 16 of on surface gate electrode, growing.Current potential on the gate electrode with 2-5 volt/minute speed increase, for example increase to the 200-300 volt, for example 250 volts, and maintenance two hours under this current potential by 4 volts/minute speed.The thickness of preferred anodic oxidation film is 1000 to 5000 , preferably 2000 to 3000 .In the 4th embodiment, make 2500 .
Use the dry etching grid insulating film, an etching 500 .(CF4) makes etching gas with carbon tetrafluoride.Substrate is immersed in the ethylene glycol solution that contains Tartaric acid (1-5% neutralizes with ammoniacal liquor).Add positive voltage to gate electrode and carry out current processing.Because gate electrode is for just, electric current press the middle arrow direction of Fig. 6 (C) and is circulated, and carries out Fig. 6 (A), the current processing shown in 6 (B) and 6 (C).The current potential of gate electrode at first with 2-5 volt/minute speed increase.For example increase to the 30-80 volt with 4 volts/minute speed, for example 60 volts, and at 1 hour (Fig. 6 (C)) of this current potential maintenance.
Use the plasma doping method, make mask with gate electrode and the anode oxide film that surrounds it thereof impurity (phosphorus) is injected silicon area.Make impurity gas with hydrogen phosphide.Accelerating voltage is 60-90KV, 80KV for example, and incorporation is 1 * 10 15To 8 * 10 15Cm -2, for example 2 * 10 15Cm -2N type impurity range 17a and 17b have consequently been formed.Impurity range 17 and gate electrode are in the skew attitude as shown in the figure, geometric position do not overlap each other (as Fig. 6 (D)).
Carry out laser annealing with laser radiation afterwards, (wavelength is 248nm with the KrF excimer laser, pulse duration is 20nsec), the laser of the other types that can use and KeF excimer laser (wavelength 353nm), XeCl quasi-molecule laser (wavelength 308nm), ArF excimer laser (wavelength 193nm).The energy density of laser is 200-500mJ/cm 2, 250mJ/cm for example 2,, for example shine 2 times local irradiation 2-10 time.Substrate is heated to 100-450 ℃ in laser radiation, for example 250 ℃.Activator impurity (Fig. 6 (E)) in this way.
Forming thickness with plasma CVD method is that the silicon oxide film of 6000 is made interlevel insulator.Form connecting hole therein, form the source region of TFT and the contact conductor 19a and the 19b in drain region with metal level.This metal level is the sandwich construction of forming with titanium nitride and aluminium.At last, in an atmospheric hydrogen, under 350 ℃ of temperature through 30 minutes annealing in process.Form thin-film transistor (Fig. 6 (F)) with the method.
Here the field-effect mobility of the thin-film transistor of Xing Chenging when gate voltage is 10 volts is 70-100cm 2/ vs, the threshold voltage when gate voltage is-20 volts is 2.5-4V, leakage current is 10 -13A or littler.
Because about being the positive voltage that adds in the current processing operation among this embodiment of N channel TFT manufacture method.Therefore, in the TFT that makes the P raceway groove, should add onesize negative voltage, promptly should add-30 to-80 volts.
With reference now to Fig. 7 (A), the manufacture method of the semiconductor device of pressing the 5th embodiment of the present invention is described to 7 (F).Forming thickness with sputtering method on substrate (Corning 7059 glass) 21 is the silica counterdie 22 of 2000 .And, be 200-1500 with plasma CVD method deposit one layer thickness, for example be intrinsic (I type) amorphous silicon film of 500 , to this silicon thin film composition, form island semiconductor film 23.Make the silicon area crystallization with laser annealing.With KrF excimer laser (wavelength is 248nm).The energy density that makes laser is 200 to 500mJ/cm 2, for example be 350mJ/cm 2, the irradiation number of times in a place is 2-10 time, for example is 2 times.Substrate temperature is 100-450 ℃ in the laser radiation, for example is 350 ℃.
With plasma CVD method with tetraethoxy-silicane (Si (OC 2H 5) 4.TEOS) and oxygen be that to form thickness be the grid insulating film that the silicon oxide film 24 of 1000 is made crystalline silicon TFT to raw material.Also available trichloroethylene except that above-mentioned gas.Feed the oxygen of 400SCCM before the deposit to deposition chamber, produce plasma when underlayer temperature is 300 ℃, total gas pressure is 5Pa, and radio-frequency power is 150 watts.This state was kept 10 minutes, give the oxygen of input 300SCCM in the deposition chamber then, the TEOS of 15SCCM, the trichloroethylene of 2SCCM, and deposit becomes silicon oxide film.Underlayer temperature, radio-frequency power, pressure are respectively 300 ℃, 75 watts and 5Pa.After deposit finishes, feed 100 torr hydrogen to deposition chamber, under 350 ℃ through 35 minutes hydrogen annealings.
Deposition thickness is 1000-10000 , for example the aluminium film of the silicon that contains 0.5-3% of 5000 .Form gate electrode 25 with the mixed acid etching aluminium film that is mainly phosphoric acid.
Substrate is immersed in the tartrated ethylene glycol solution (1-5% neutralizes with ammoniacal liquor), give the gate electrode galvanization, form anode oxide film (aluminium oxide) layer 26 at surface gate electrode.The thickness of anode oxide film is 1000-5000 , preferably 2000-3000 .In the 5th embodiment 2500 (Fig. 4 (A)).
Make mask 27 with photoresist, expose the part semiconductor district of TFT.With this mask etching silicon oxide film 24.Corrosive agent is with 10% hydrofluoric acid (Fig. 7 (B)).
Usually, under the situation of large-area substrate, the silicon oxide film of technical etching equably shown in the 4th embodiment.Have thick and thin part in the silicon oxide film.This voltage that rises on the gate electrode plate that is added to below the silicon oxide film (grid insulating film) of this silicon oxide film is uneven, and this is worthless.Owing to do not have this problem among the 5th embodiment, be desirable therefore.
Substrate is immersed in the tartrated ethylene glycol solution (1-5% neutralizes with ammoniacal liquor), adds positive voltage to gate electrode and carries out current processing.Electric current feeds silicon thin film, particularly feed the channel structure district (active area carries out current processing, as Figure 10 (A) to shown in 10 (B).Make raceway groove in the boundary layer of insulation film and silicon thin film constitute that district, particularly complex centre are cancelled and eliminating makes its partly pinch off in this way.At first with 2-5 volt/minute speed, for example 4 volts/minute speed increases to 30 volts to 80 volts, for example 60 volts, this maintenance 1 hour.
Use the plasma doping method, make mask with gate electrode and the anode oxide film around it impurity (phosphorus) is injected silicon area.With hydrogen phosphide (PH 3) make impurity gas, accelerating voltage is 60-90KV, for example is 80KV, dopant dose is 1 * 10 15-8 * 10 15Cm -2, for example be 2 * 10 15Cm -2Consequently, form N type impurity range 25a and 28b (Fig. 7 (D)).
Then, carry out laser annealing with laser radiation.Used laser is KrF excimer laser (wavelength is 248nm, and pulse duration is 20nsec).Laser energy density is 200-500mJ/cm 2, 250mJ/cm for example 2, a place is shone for example 2 times 2-10 time.Substrate is heated to 100-450 ℃ in the laser radiation, and for example 250 ℃ with this method activated impurity (Fig. 7 (E)).
Forming thickness with plasma CVD method is that the silicon oxide film of 6000 is made interlevel insulator.Form connecting hole therein, constitute the source region of TFT and the electrode wiring 30a and the 30b in drain region, the sandwich construction that metal level is made up of titanium nitride membrane and aluminium film with metal level.At last, in an atmospheric hydrogen, under 350 ℃, annealed through 30 minutes.Make thin-film transistor (Fig. 7 (F)) with this technology.
With reference now to Fig. 8 (A), the manufacture method of the semiconductor device of pressing the 6th embodiment of the present invention is described to 8 (F).The complementary TFT that N-channel TFT that this embodiment forms on same substrate and P channel TFT are formed.(CTFT) example.
At first, forming thickness with sputtering method on substrate (Corning 7059 glass) 31 is the silica bottom layer film 32 of 2000 .Forming thickness with plasma CVD method is 500-1500 , and for example the intrinsic of 1500 (I type) amorphous silicon film is the silicon oxide film of 200 with sputtering method formation thickness, in nitrogen, makes this amorphous silicon membrane crystallization at 600 ℃ through 48 hours annealing in process.
After the crystallization step,, form island shape silicon area 33P (being used for the P channel TFT) and 33n (being used for the N-channel TFT) to the silicon thin film needle drawing.Be that the silicon oxide film 34 of 1000 is made grid insulating film with the sputtering method deposition thickness then.Make target with silica in the sputter, underlayer temperature is 200-400 ℃, for example is 250 ℃, and sputtering atmosphere is oxygen and argon, argon/oxygen=0-0.5, for example 0.1 or lower.
Deposition thickness be 1000-10000 for example 5000 contain the aluminium film that 0.5-3% for example is 2% silicon.Wish that the deposit of silicon oxide film and aluminium film carries out continuously.With this aluminium film of mixed acid etching of main phosphoric acid, form gate electrode 35P (being used for the P channel TFT) and 35n (being used for the N channel TFT).
Substrate immerses (1-5% neutralizes with ammoniacal liquor) in the tartrated ethylene glycol solution.Add positive voltage to grid and make deposit anodization layer 36P and 36n (alumina layer) on each gate electrode.The thickness of anodization layer is 2500 (Fig. 8 (F)).
Make mask 37n with photoresist, expose the semiconductor region of N channel TFT.With this mask etching silica 34, the hydrofluoric acid with 10% is corrosive agent.Substrate immerses (1-5% neutralizes with ammoniacal liquor) in the tartaric ethylene glycol solution once more, carries out current processing after adding positive voltage to gate electrode.Current potential on the gate electrode increases to the 30-80 volt with 4 volts/minute speed, and for example 60 volts, and this maintenance 1 hour.
Under the alive situation of gate electrode of P-channel-type TFT, because all being insulated material, gate electrode covers, effective voltage adds less than on the electrode below the dielectric film.In this operation, can not make the P-channel TFT carry out current processing.This current processing is used for the P channel TFT, when being added on the gate insulating film transistor performance is degenerated owing to positive voltage.(Fig. 8 (B)).
Use mask 37n, make the silicon area 33n that mask injects impurity (phosphorus) the N channel TFT with the anode oxide film 36 of gate electrode 35n and encirclement gate electrode.With hydrogen phosphide (PH 3) make foreign gas, accelerating voltage is 60-90KV, 80KV for example, dosage is 1 * 10 15Cm -2-8 * 10 15Cm -2, for example 2 * 10 15Cm -2, consequently formed N type impurity range 38n (Fig. 8 (C)).
The mask 37P that makes with photoresist covers the N channel TFT, exposes the semiconductor region 33P of P channel TFT, with this mask etching silicon oxide film 34.Hydrofluoric acid with 10% is made corrosive agent.Substrate immerses (1-5% neutralizes with ammoniacal liquor) in the tartaric ethylene glycol solution once more.Carry out current processing to adding negative voltage on the grid.Gate electrode potential at first increases to-30 to-80 volts with-4 volts/minute speed, for example-60 volt, and keeps 1 hour.
Voltage also is to be added on the gate electrode of N channel-type TFT in this case since gate electrode all to be insulated material topped, virtual voltage adds less than on the gate electrode below the insulation film (Fig. 8 (D)).
With mask 37P and gate electrode 35P, reach the anode oxide film 36P that surrounds gate electrode and make mask, impurity (hydrogen) is injected the silicon area 33P of P-raceway groove TPT with the plasma doping method.With diborane (B 2H 6) make foreign gas, accelerating voltage is 40-80KV, 65KV for example, dosage is 1 * 10 15Cm -2-8 * 10 15Cm -2, for example 5 * 10 15Cm -2Consequently formed impurity range 38P (Fig. 8 (E)).
Then, carry out laser annealing with laser radiation.With KrF excimer laser (wavelength 248nm, pulse duration is 20nsec).The energy density of laser is 200-500mJ/cm 2, 250mJ/cm for example 2, each local irradiation 2-10 time, for example 2 times, substrate is heated to 100-450 ℃, for example 250 ℃, makes impurity activation in this way.
Forming thickness with plasma CVD method is that the silicon oxide film 39 of 6000 is made interlevel insulator, forms connecting hole therein.Form the source region of TFT and the electrode wiring 40a in drain region with metal film, 40b, 40c, 40d, metal film are the sandwich constructions that is made of titanium nitride membrane and aluminium film.At last, in an atmospheric hydrogen, under 350 ℃ through 30 minutes annealing in process.Form thin-film transistor (Fig. 8 (F)) with this method.
Constitute displacement resistor with the thin-film transistor that forms herein, prove when drain voltage is 15 volts and can work, when drain voltage is 18 volts, can under 20MHz, work at 11MHz.
If as present embodiment, CTFT is carried out current processing,, also should separate for the voltage that adds on each gate electrode owing to form the gate electrode of P channel TFT and N channel TFT respectively.Yet, in the CTFT circuit, many times be that the grid of P channel TFT and the grid of N channel TFT are linked together.If the picture system that said usefulness is different comes making alive, then need to reconstruct a figure who connects them here.
On the other hand, be to solve this problem among the present invention with mask 37P and 37n.This mask also can be used as doping mask, and manufacturing process is not increased.
With reference now to Fig. 9 (A), the manufacture method of the semiconductor device of pressing seventh embodiment of the invention is described to 9 (F).This embodiment is an example making CTFT.Forming thickness with sputtering method on substrate (Corning 7059 glass) 41 is the silica bottom layer film 42 of 2000 .Forming thickness with plasma CVD method is 500-1500 , and for example the intrinsic of 1500 (I type) amorphous silicon film is the silicon oxide film of 200 with sputtering method deposit one layer thickness on it.In nitrogen atmosphere, through 48 hours amorphous silicon film is carried out crystallization treatment at 600 ℃.
After the crystallization treatment, the silicon thin film composition is made island semiconductor district 43n (the N channel TFT is used) and 43P (the P channel TFT is used), forming thickness with sputtering method is the silicon oxide film 44 of 1000 .Deposition thickness is 1000-10000 , for example the siliceous 0.5-3% of 5000 , for example 2% aluminium film.Etching aluminium film forms gate electrode 45n (the N channel TFT is used) and 45P (the P-channel TFT is used).
Substrate immerses (1-5%, ammoniacal liquor neutralization) in the tartrated ethylene glycol solution, and galvanization adds positive voltage to gate electrode, at surface gate electrode growth anodic oxidation film (aluminium oxide) 46n and 46p.Anodic oxidation thickness 1000-5000 is preferably 2000-3000 , is 2500 in the 7th embodiment.(Fig. 9 (A)).
With dry etching method etching gate insulating film, only corrode 500 .With carbon tetrafluoride (CF 4) do corrosion body.Substrate is immersed (1-5%, ammoniacal liquor neutralization) in the tartrated ethylene glycol solution, add positive voltage and carry out current processing for gate electrode 45n.Gate electrode potential is so that 2-5 volt/minute for example 4 volts/minute speed increases to the 30-80 volt, for example to 60 volts, this current potential maintenance 1 hour.The current potential of another gate electrode 45p is 0, consequently only the N channel TFT has been carried out current processing.(Fig. 9 (B)).
Another gate electrode 45P is added negative voltage carry out current processing.The current potential of gate electrode is at first with-2 to-5 volts/minute speed, and for example ,-4 volts/minute speed increases to-30 to-80V.For example-and 60V, kept this current potential 1 hour.This moment, the current potential of gate electrode 45n was 0, and consequently two TFT have all finished current processing (Fig. 9 (C)).
With general CMOS manufacturing technology, impurity (phosphorus and boron) is injected silicon area with the plasma doping method.Dosage is 2 * 10 15Cm -2Phosphorus, 5 * 10 15Cm -2Boron, constituted N type impurity range 47n and p type impurity district 47P.(Fig. 9 (D)).
Then, carry out laser annealing with laser radiation.Laser is with KrF excimer laser (wavelength is 248nm, and pulse duration is 20nsec).The energy density of laser is 200-500mJ/cm 2, for example, 250mJ/cm 2, a place is shone for example 2 times 2-10 time.100-450 ℃ of substrate heating, for example 250 ℃, with this method activated impurity.(Fig. 9 (E)).
With the plasma CVD method deposition thickness is that the silicon oxide film 48 of 6000 is made interlevel insulator.Open connecting hole therein, constitute the source region of TFT and the electric former wiring 49a in drain region with metal level, 49b, 49c and 49d, metal level are the sandwich constructions that is made of titanium nitride and aluminium film.In an atmospheric hydrogen, under 350 ℃,, made the TFT circuit (Fig. 9 (F)) of CMOS (CTFT) with this method at last through 30 minutes annealing in process.
The front with figure and explanatory note most preferred embodiment.Described accurate configuration be not of the present invention all, neither limitation of the present invention, obviously also can make various improvement and variation by above-mentioned technology.Select these embodiment just for essence of an invention very clearly is described, others skilled in the art person can come the most effective utilization invention with various embodiment and various remodeling in actual applications.

Claims (25)

1, a kind of method of making semiconductor device comprises the following steps:
On dielectric substrate, form semiconductor region;
On said semiconductor region, form insulation film as grid insulating film;
Form conductive film on said insulation film, this conductive film is with a kind of the making in aluminium, chromium, titanium, tantalum and the silicon, or made by at least a alloy that mainly comprises in these metals, or the multiple layer metal film of these metals;
Formation covers the lip-deep oxide film of said conductive film, and this oxide film adds positive voltage to conductive film and forms in electrolyte;
Add after the positive voltage for said conductive film, add negative voltage or positive voltage for said conductive film, improving said semiconductor region, or the interface between said semiconductor region and the said insulation film.
2, according to the method for claim 1, it is characterized in that, when adding said negative voltage or positive voltage, make electric current pass through semiconductor region.
3, according to the method for claim 1, it is characterized in that, saidly add negative voltage or positive voltage adds in electrolyte.
4, according to the method for claim 1, it is characterized in that, in adding the process of negative voltage, give the back side ultraviolet irradiation of said substrate.
5, a kind of method of making semiconductor device comprises the following steps:
On a dielectric substrate, form semiconductor region;
On said semiconductor region, formed one deck insulation film of grid insulating film effect;
Form conductive film on said insulation film, this conductive film is made with a kind of metal in aluminium, chromium, titanium, tantalum and the silicon, or at least a alloy that mainly comprises in these metals makes, or the plural layers of these metals are made
In electrolyte, said conductive film is alternately added positive voltage and negative voltage, form oxide film on the conductive film surface.
6, a kind of method of making semiconductor device comprises the following steps:
On substrate, form semiconductor island;
On said semiconductor island, form insulation film;
On said insulation film, form gate electrode;
The said gate electrode of anodic oxidation is to form the anodic oxide coating on the surface of said gate electrode;
At least remove the top of said insulation film, and do not remove the said insulation film that a part is covered by said gate electrode and said anodic oxide coating;
Said remove step after, when substrate immerses in the electrolyte, give said gate electrode making alive; And
After said making alive step, impurity is mixed said semiconductor island,
Wherein said voltage is born, and forms p channel transistor by said doping step.
According to the method for claim 6, it is characterized in that 7, said voltage is positive, form the N channel transistor with said doping process.
According to the method for claim 6, it is characterized in that 8, said voltage is born, form p channel transistor with said doping process.
According to the method for claim 6, it is characterized in that 9, said covering dielectric film is to be made of anode oxide film.
According to the method for claim 6, it is characterized in that 10, the degree of depth of removing the dielectric film that operation removes equates with the thickness of this dielectric film.
According to the method for claim 6, it is characterized in that 11, said electrolyte remains on the room temperature or the state of cooling in the making alive process.
According to the method for claim 6, it is characterized in that 12, the voltage that is added in the making alive operation on the said insulation film is 30 to 80 volts.
According to the method for claim 6, it is characterized in that 13, said gate electrode constituent material is to select from the metal group that aluminium, tantalum, silicon, titanium, tungsten and chromium are formed.
According to the method for claim 9, it is characterized in that 14, the thickness of said anode oxide film is 1000 to 5000 .
15, a kind of method of making semiconductor device comprises step:
On a substrate, form at least two semiconductor island;
Form an insulation film and cover said semiconductor island;
Also on said each semiconductor island, forming gate electrode respectively on the said insulation film;
Said substrate is immersed in the electrolyte, make anode, give said gate electrode galvanization, form anode oxide film at said surface gate electrode with said gate electrode;
Cover all surfaces of at least one said semiconductor island with one deck insulating material;
Remove at least a portion insulation film with said exhausted level material as mask;
Remove after the operation of insulation film, said substrate is immersed in the electrolyte, give said gate electrode making alive;
With the insulating material be mask give in the said semiconductor island at least one doping and
Remove said insulating material.
According to the method for claim 15, it is characterized in that 16, the N-channel transistor institute making alive that forms with said doping operation is for just.
According to the method for claim 15, it is characterized in that 17, the P-channel transistor institute making alive that forms with said doping operation is negative.
According to the method for claim 15, it is characterized in that 18, in said making alive operation, said electrolyte remains on the room temperature or the state of cooling.
Very according to the method for claim 15, it is characterized in that 19, the voltage that is added by said making alive operation is 30 to 80 volts.
According to the method for claim 15, it is characterized in that 20, said gate electrode constitutes.Material is selected from the metal group of being made up of aluminium, tantalum, silicon, titanium, tungsten and chromium.
21, a kind of method of making semiconductor device comprises the following steps:
On a substrate, form semiconductor island;
On said semiconductor island, formed the insulation film of grid insulating film effect;
Form gate electrode on said insulation film, this gate electrode is with a kind of the making in aluminium, chromium, titanium, tantalum and the silicon, or the alloy that mainly comprises a kind of metal in these metals makes, or these metal sandwich constructions;
Add positive voltage in electrolyte, for said gate electrode and form the sull that covers said gate electrode;
Immerse in the said electrolyte said substrate when forming said sull or afterwards, feed electric current, make electric current pass said grid insulating film to said electrolyte, improve the interface between said semiconductor island or said semiconductor island and the said insulation film from said gate electrode; With
Impurity is mixed said semiconductor island, formation source and leakage in semiconductor island.
22, a kind of method of making semiconductor device comprises the following steps:
On a dielectric substrate, form semiconductor island;
On said semiconductor island, formed the insulation film of grid insulating film function;
Form gate electrode on said insulation film, gate electrode is made by a kind of metal in aluminium, chromium, titanium, tantalum and the silicon, or is made by the metal alloy that mainly comprises at least a metal in these metals, or is made of the multiple layer metal of these metals;
Add positive voltage in electrolyte, for said gate electrode and form the sull that covers said surface gate electrode;
Said substrate is immersed in the electrolyte form said sull in or afterwards, feed electric current, make electric current enter gate electrode by said grid insulating film and said semiconductor island, to improve the interface between semiconductor island or said semiconductor island and the said insulation film from electrolyte; With
Give said semiconductor island implanted dopant, formation source or leakage in semiconductor island.
23, a kind of method of making semiconductor device comprises the following steps:
On dielectric substrate, form semiconductor island;
On semiconductor island, form insulation film as grid insulating film;
But formation one comprises the gate electrode of anodic oxidation material on insulation film;
In electrolyte, apply voltage to form the oxide-film on covering grid electrode surface to gate electrode;
After oxide-film forms step, substrate is stayed in the electrolyte, make electric current flow to electrolyte and semiconductor island to improve semiconductor island or the interface of semiconductor island and the character of insulation film by grid insulating film from gate electrode; And
Impurity is mixed semiconductor island wherein form source and leakage.
24, a kind of method of making semiconductor device comprises the following steps:
On dielectric substrate, form semiconductor island;
On semiconductor island, form insulation film as grid insulating film;
But formation one comprises the gate electrode of anodic oxidation material on insulation film;
In electrolyte, apply voltage to form the oxide-film on covering grid electrode surface to gate electrode;
After oxide-film forms step, substrate is stayed in the electrolyte, make electric current flow to gate electrode to improve the character of semiconductor island or semiconductor island interface and insulation film by grid insulating film from electrolyte; And
Impurity is mixed semiconductor island to form source and leakage therein.
According to the method for claim 5, it is characterized in that 25, the step that forms oxide film comprises to conductive film and applies voltage and negative voltage continuously.
CN93105438A 1992-04-07 1993-04-07 Method for forming a semiconductor device Expired - Fee Related CN1054469C (en)

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CN105637646A (en) * 2013-10-28 2016-06-01 富士电机株式会社 Silicon carbide semiconductor device and manufacturing method for same
CN107799605A (en) * 2017-10-27 2018-03-13 合肥鑫晟光电科技有限公司 A kind of thin film transistor (TFT) and preparation method thereof, array base palte, display device

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JP3469337B2 (en) * 1994-12-16 2003-11-25 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
CN102569053B (en) * 2012-01-18 2014-12-24 上海华力微电子有限公司 Method for forming high-dielectric constant metal grid
CN105977306A (en) * 2016-06-21 2016-09-28 北京大学深圳研究生院 Self-aligned thin-film transistor and preparation method thereof

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Publication number Priority date Publication date Assignee Title
CN105637646A (en) * 2013-10-28 2016-06-01 富士电机株式会社 Silicon carbide semiconductor device and manufacturing method for same
CN107799605A (en) * 2017-10-27 2018-03-13 合肥鑫晟光电科技有限公司 A kind of thin film transistor (TFT) and preparation method thereof, array base palte, display device
US10615051B2 (en) 2017-10-27 2020-04-07 Boe Technology Group Co., Ltd. Thin-film transistor and method of manufacturing the same, array substrate, and display apparatus
CN107799605B (en) * 2017-10-27 2020-07-31 合肥鑫晟光电科技有限公司 Thin film transistor, preparation method thereof, array substrate and display device

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