CN105097544A - Manufacturing method for low temperature polycrystalline silicon thin film transistors - Google Patents
Manufacturing method for low temperature polycrystalline silicon thin film transistors Download PDFInfo
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- CN105097544A CN105097544A CN201410222253.3A CN201410222253A CN105097544A CN 105097544 A CN105097544 A CN 105097544A CN 201410222253 A CN201410222253 A CN 201410222253A CN 105097544 A CN105097544 A CN 105097544A
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Abstract
The present invention provides a manufacturing method for low temperature polycrystalline silicon thin film transistors, and the method is characterized by including the following steps: a polycrystalline silicon layer, a gate insulation layer and a gate metal layer are formed on a substrate in sequence; one part of the gate metal layer is removed so as to expose one part of the gate insulating layer; and doping ions penetrate the exposed part of the gate insulation layer by the adoption of an ion-injection method. According to the invention, a metal layer is etched only but a silicon nitride and silicon oxide layer is not etched, a dose uniformity of the doping ion injecting is increased, and therefore, an electricity uniformity of the low temperature polycrystalline silicon thin film transistors is improved.
Description
Technical field
The present invention relates to a kind of manufacture method of low-temperature polysilicon film transistor, particularly relate to a kind of method that can promote the electric uniformity of low-temperature polysilicon film transistor.
Background technology
In CMOS (ComplementaryMetalOxideSemiconductor: the complementary metal oxide semiconductors (CMOS)) manufacturing process of low-temperature polysilicon film transistor (LTPSTFT), after enforcement polysilicon grating structure operation, namely, after forming gate metal layer and gate insulator (GI:Gateinsulator) structure, implement ion implantation doping operation, be " penetrating gate insulator operation ".
Such as, after the membrane structure forming molybdenum (Mo) layer/silicon nitride (SiNx) layer/silica (SiO2) layer/polysilicon (Poly) layer/buffering (Buffer) layer, implement ion injecting process, such as, implement lightly doped drain (LDD:Lightlydopeddrain) injection process and P type source/drain doping (PD:P-typesource/draindoping) injection process.
When the method in the past of employing is dry carve gate metal layer time, as shown in Figure 4, dry quarter such as molybdenum layer gate metal layer 1 operation in, also can etch away silicon nitride layer 2.As shown in Figure 4, the silicon nitride layer 2 of gate metal is not coated with by etching removing.Then, when implementing lightly doped drain injection process, as shown in Figure 4, the thickness making Doped ions 100 directly penetrate silicon dioxide layer 3 along injection direction D is injected in polysilicon layer 5.
In above-mentioned lightly doped drain injection process or P type source/drain doping injection process, Doped ions 100 dose uniformity be injected in polysilicon layer 5 can be subject to dry impact of carving the film thickness uniformity of removing gate metal layer 1 and the rear remaining silicon dioxide layer 3 of silicon nitride layer 2.And then the dose uniformity that described Doped ions 100 injects can have influence on the electric uniformity of low-temperature polysilicon film transistor in panel.Therefore, need to control the film thickness uniformity of silicon dioxide layer 3.Usually when carrying out volume production, the film thickness uniformity of above-mentioned silicon dioxide layer 3 is controlled in 10%.
But, do in the process of carving gate metal layer 1 adopting method in the past, while etching away silicon nitride layer 2, because the etching selectivity of silicon nitride and silicon dioxide is low, etching can be applied to the silicon dioxide layer 3 of the lower floor being positioned at silicon nitride layer 2, and cause silicon dioxide layer 3 loss 10nm ~ 20nm.Its result, causes the film thickness uniformity of silicon dioxide layer 3 more than more than 10%.The dose uniformity that above-mentioned Doped ions 100 can be made thus to be injected into polysilicon layer 5 is deteriorated, and then the uniformity of the electrical property of thin-film transistor in panel also can be deteriorated.If above-mentioned electric uniformity is bad, then the drive current of display unit can be caused uneven, and its result causes the luminance deviation of display unit, shows the problems such as uneven.This not only can make to occur non-uniform phenomenon in same substrate (such as the substrate of 4.5 generation 730mm × 920mm sizes), and occurs non-uniform phenomenon too between substrate and substrate.
Summary of the invention
The present invention completes in view of the above problems, and its object is to provides a kind of manufacture method that can promote the low-temperature polysilicon film transistor of the electric uniformity of low-temperature polysilicon film transistor.
To achieve these goals, one of embodiments of the present invention have employed following technical scheme.
A manufacture method for low-temperature polysilicon film transistor, is characterized in that, comprises the following steps:
Substrate is formed with polysilicon layer, gate insulator and gate metal layer at least successively;
Remove the described gate metal layer of part, the described gate insulator of part is exposed; And
Ion implantation is adopted to make Doped ions penetrate the described gate insulator of exposed parts.
Wherein, the generation type of described gate insulator comprises:
Described polysilicon layer is formed the first silicon dioxide layer; And
Described first silicon dioxide layer forms the first silicon nitride layer.
Wherein, before forming the operation of polysilicon layer, gate insulator and gate metal layer over the substrate at least successively, resilient coating can be formed with further, described resilient coating comprises the second silicon dioxide layer and the second silicon nitride layer, wherein said second silicon nitride layer is formed at described substrate, and described second silicon dioxide layer is formed on the second silicon nitride layer.
Wherein, described polysilicon layer can between described first silicon dioxide layer and described second silicon dioxide layer.
Wherein, the material of described gate metal layer comprises molybdenum.Wherein, described substrate is glass substrate.
A kind of manufacture method of low-temperature polysilicon film transistor according to another execution mode of the present invention, comprising:
Substrate forms polysilicon layer,
Described polysilicon layer forms gate insulator,
Described gate insulator forms gate metal layer,
Etch away gate metal layer and retain described gate insulator to form grid, and
Ion implantation is adopted to make Doped ions penetrate gate insulator.
Wherein, when described etch away gate metal layer and retain described gate insulator to form grid time, also comprise: adopt the etching solution high to the etching selectivity of described gate insulator and described gate metal layer to implement.
Invention effect
Based on execution mode described in the invention described above, dry lithography is adopted only to etch away gate metal layer and not etching grid insulating barrier.Thus, can either solve and dry carve etching of silicon nitride in operation and affect the problem of the production capacity of etching machines, the silicon dioxide loss of the 10nm ~ 20nm caused when etching can be avoided again and the film thickness uniformity of silicon dioxide layer is reduced.Thus, the production capacity of equipment at dry quarter can be promoted, and, when dopant implant ion, the uniformity that Doped ions penetrates silicon nitride layer and silicon dioxide layer can remain on film thickness uniformity when adopting chemical vapour deposition technique (CVD) film forming silicon nitride layer and silicon dioxide layer, below 3%, this will promote the electrical uniformity in panel of thin-film transistor greatly, and improve the uniformity between substrate and substrate further.
Accompanying drawing explanation
Fig. 1 is the schematic diagram representing the doping operation implementing low-temperature polysilicon film transistor according to the embodiment of the present invention.
Fig. 2 is the structural representation of the low-temperature polysilicon film transistor represented before dry quarter gate metal layer.
Fig. 3 represents the structural representation doing the low-temperature polysilicon film transistor after carving gate metal layer according to the embodiment of the present invention.
Fig. 4 is the schematic diagram representing in prior art the doping operation implementing low-temperature polysilicon film transistor.The explanation of Reference numeral
D: ion implantation direction;
1: gate metal layer;
2: silicon nitride layer (the first silicon nitride layer);
3: silicon dioxide layer (the first silicon dioxide layer);
4: gate insulator;
5: polysilicon layer;
6: the second silicon dioxide layers;
7: the second silicon nitride layers;
8: resilient coating;
9: substrate;
10: photoresist;
100: Doped ions.
Embodiment
Describe the present invention in detail below in conjunction with accompanying drawing, but the present invention is also not only confined to this, should be understood that following explanation and accompanying drawing all for better the present invention being described, instead of for limiting the present invention.
Fig. 2 represents one of execution mode of the structure of the low-temperature polysilicon film transistor before dry quarter gate metal layer.Adopt PECVD (plasma enhanced chemical vapor deposition) method, on the surface of the glass substrate as substrate 9, form the second silicon nitride layer 7 and the second silicon dioxide layer 6 as above-mentioned resilient coating 8 successively, that is: the second silicon dioxide layer 6 is positioned at the upside of the second silicon nitride layer 7.And then after forming polysilicon layer 5, then forming the first silicon dioxide layer 3 and the first silicon nitride layer 2 as insulating barrier, that is: the first silicon nitride layer 2 is positioned at the upside of the first silicon dioxide layer 3; Further, polysilicon layer 5 is between the first silicon dioxide layer 3 and the second silicon dioxide layer 6.Then, adopt sputtering method at the Mo layer of the surface of the first silicon nitride layer 2 formation as gate metal 1.
In above-mentioned technical process, employing elliptical polarizer method determines the film thickness uniformity after the first silicon dioxide layer 3 formation below 3%, and the film thickness uniformity after the first silicon nitride layer 2 is formed is below 3%.
As shown in Figure 3, above-mentioned gate metal layer is passed through the pattern of conventional gluing, exposure, development formation photoresist 10.Next, dry operation of carving gate metal is implemented.As shown in Figure 1, only etching grid metal level 1 (such as metal molybdenum layer) in the dry etching method that adopts of the present invention.Because the etching selectivity of metal molybdenum and silicon nitride is high, after etching metal molybdenum layer terminates, can not etch the silicon nitride layer of its lower floor.These are different from dry etching method in the past.As shown in Figure 4, dry etching method in the past will be done and falls silicon nitride layer 2 quarter and can cause etching to silicon dioxide layer 3.
Implement ion injecting process, such as lightly doped drain injection process and P type source/drain doping injection process time, by doping particle 100 all with perpendicular to substrate 9 ion implantation direction D incidence and penetrate the gate insulator 4 not being coated with gate metal layer.Result forms lightly doped drain injection zone and P type source/drain doping injection zone in polysilicon layer 5.
Below, embodiments of the present invention are described in detail by embodiment and comparative example by reference to the accompanying drawings.
Embodiment
In the operation of gate metal at dry quarter, the equipment at dry quarter that eastern electronics (TokyoElectronLimited (TEL)) company such as can be adopted specifically to manufacture, enforcement utilizes chlorine plasma to carry out etching method, only etching metal molybdenum layer is to form grid, then carries out the demoulding and comes unstuck.At this, the film thickness uniformity adopting elliptical polarizer to determine remaining first silicon nitride layer 2 remains on less than 3%.
Penetrating in gate insulator operation, doping particle needs the first silicon nitride layer 2 and the first silicon dioxide layer 3 (being equivalent to the silicon nitride layer 2 in Fig. 1 and silicon dioxide layer 3 respectively) penetrated as gate insulator 4.Implement lightly doped drain injection testing, alloy adopts boron ion with the incident Doped ions of ion implantation direction D perpendicular to substrate, form lightly doped drain injection zone at polysilicon layer 5, the dose uniformity measuring the rear ion implanted polysilicon layer of this doping test is 10%; Enforcement P type source/drain doping injection testing, alloy adopts boron ion with the direction D incident ion perpendicular to substrate, forms P type source/drain doping injection zone at polysilicon layer 5, and the dose uniformity measuring the rear ion implanted polysilicon layer of this doping test is 10%.
After finally making thin-film transistor, the uniformity of ON state current in panel measuring thin-film transistor is 20%.
Comparative example
In the operation of gate metal at dry quarter, adopt the dry quarter equipment utilization chlorine identical with embodiment and the engraving method of sulphur hexafluoride plasma, while etching metal molybdenum layer, etch away silicon nitride layer, then carry out the demoulding and come unstuck.
Now, the etching of crossing adopting elliptical polarizer method to measure silicon oxide layer reaches 20nm; The film thickness uniformity adopting elliptical polarizer method to measure residual silicon oxide layer is 15%.
Penetrating in gate insulator operation, as shown in Figure 4, doping particle only need penetrate rear remaining silicon dioxide layer 3 at dry quarter.Implement lightly doped drain injection testing, alloy adopts boron ion with the ion implantation direction D incident ion perpendicular to substrate, forms lightly doped drain injection zone at polysilicon layer 5, and the dose uniformity measuring the rear ion implanted polysilicon layer of this doping test is 20%.Enforcement P type source/drain doping injection testing, alloy adopts boron ion with the direction D incident ion perpendicular to substrate, forms P type source/drain doping injection zone at polysilicon layer 5, and the dose uniformity measuring the rear ion implanted polysilicon layer of this doping test is 20%.
After finally making thin-film transistor, the uniformity of ON state current in panel measuring thin-film transistor is 40%.
[interpretation of result]
Visible according to the contrast of embodiment and comparative example, by only etch metal layers and not etching of silicon nitride and silicon dioxide layer in dry etch sequence, the dose uniformity that Doped ions injects can be improved, thus promote the electric uniformity of low-temperature polysilicon film transistor.
As mentioned above, described in this specification " silicon nitride " refers to general formula " SiN
x" the nitrogen silicon compound that represents.
" the first silicon nitride layer " and " the second silicon nitride layer " described in this specification is the layer in order to distinguish two " silicon nitride layers " and definition respectively." the first silicon dioxide layer " and " the second silicon dioxide layer " described in this specification is the layer in order to distinguish two " silicon dioxide layers " and definition respectively.
" the electric uniformity of low-temperature polysilicon film transistor " described in this specification refers to " the electric uniformity that low-temperature polysilicon film transistor shows in panel ".
In this specification described to take substrate as the "up" and "down" of object of reference be with direction substrate stacking gradually other layer for " on ", it is reversed D score, namely with the upper and lower shown in Fig. 1 ~ 4 for reference to the explanation carried out.
[variant embodiment]
As mentioned above, in above-mentioned execution mode, enumerate the instantiation that low-temperature polysilicon film transistor manufactures, give example to the material etc. of metal, insulating barrier and the resilient coating employing that grid adopts, but the present invention is not limited thereto.
For the material that gate metal, gate insulator etc. adopt, as long as aim according to the invention and can by select be suitable for etchant to keep the material having higher etching selectivity between gate metal and the insulating barrier of its lower floor, thus can when etching grid metal to its lower membrane do not cause etch and keep its surface uniformity.
It should be understood that embodiments of the present invention are also not only confined to the content of described embodiment.The present invention can carry out various change and replacement on the basis of described embodiment, and it neither departs from the scope of the present invention.
Claims (8)
1. a manufacture method for low-temperature polysilicon film transistor, is characterized in that, comprises the following steps:
Substrate forms polysilicon layer, gate insulator and gate metal layer at least successively;
Remove the described gate metal layer of part, the described gate insulator of part is exposed; And
Ion implantation is adopted to make Doped ions penetrate the described gate insulator of exposed parts.
2. the manufacture method of low-temperature polysilicon film transistor as claimed in claim 1, the generation type of wherein said gate insulator comprises:
Described polysilicon layer is formed the first silicon dioxide layer; And
Described first silicon dioxide layer forms the first silicon nitride layer.
3. the manufacture method of low-temperature polysilicon film transistor as claimed in claim 2, wherein,
Before forming the operation of polysilicon layer, gate insulator and gate metal layer over the substrate at least successively, be formed with resilient coating further,
Described resilient coating comprises the second silicon dioxide layer and the second silicon nitride layer, and wherein said second silicon nitride layer is formed at described substrate, and described second silicon dioxide layer is formed on the second silicon nitride layer.
4. the manufacture method of low-temperature polysilicon film transistor as claimed in claim 3, wherein,
Described polysilicon layer is between described first silicon dioxide layer and described second silicon dioxide layer.
5. the manufacture method of the low-temperature polysilicon film transistor according to any one of Claims 1 to 4, wherein, the material of described gate metal layer comprises molybdenum.
6. the manufacture method of the low-temperature polysilicon film transistor according to any one of Claims 1 to 4, wherein, described substrate is glass substrate.
7. a manufacture method for low-temperature polysilicon film transistor, comprising:
Substrate forms polysilicon layer,
Described polysilicon layer forms gate insulator,
Described gate insulator forms gate metal layer,
Etch away gate metal layer and retain described gate insulator to form grid, and
Ion implantation is adopted to make Doped ions penetrate gate insulator.
8. the manufacture method of low-temperature polysilicon film transistor as claimed in claim 7, wherein,
When described etch away gate metal layer and retain described gate insulator to form grid time, also comprise:
The etching solution high to the etching selectivity of described gate insulator and described gate metal layer is adopted to implement.
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| CN201410222253.3A CN105097544A (en) | 2014-05-23 | 2014-05-23 | Manufacturing method for low temperature polycrystalline silicon thin film transistors |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107527819A (en) * | 2017-08-07 | 2017-12-29 | 武汉华星光电半导体显示技术有限公司 | The preparation method of bottom gate type low-temperature polycrystalline silicon transistor |
| CN108766870A (en) * | 2018-05-31 | 2018-11-06 | 武汉华星光电技术有限公司 | The production method and LTPS TFT substrates of LTPS TFT substrates |
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| US20040072392A1 (en) * | 2002-10-09 | 2004-04-15 | Hui-Chu Lin | Method of forming a low temperature polysilicon thin film transistor |
| CN1967876A (en) * | 2005-11-16 | 2007-05-23 | 三星Sdi株式会社 | Thin film transistor and method of manufacturing the same |
| CN102543860A (en) * | 2010-12-29 | 2012-07-04 | 京东方科技集团股份有限公司 | Manufacturing method of low-temperature polysilicon TFT (thin-film transistor) array substrate |
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Patent Citations (3)
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| US20040072392A1 (en) * | 2002-10-09 | 2004-04-15 | Hui-Chu Lin | Method of forming a low temperature polysilicon thin film transistor |
| CN1967876A (en) * | 2005-11-16 | 2007-05-23 | 三星Sdi株式会社 | Thin film transistor and method of manufacturing the same |
| CN102543860A (en) * | 2010-12-29 | 2012-07-04 | 京东方科技集团股份有限公司 | Manufacturing method of low-temperature polysilicon TFT (thin-film transistor) array substrate |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107527819A (en) * | 2017-08-07 | 2017-12-29 | 武汉华星光电半导体显示技术有限公司 | The preparation method of bottom gate type low-temperature polycrystalline silicon transistor |
| CN107527819B (en) * | 2017-08-07 | 2019-08-30 | 武汉华星光电半导体显示技术有限公司 | The preparation method of bottom gate type low-temperature polycrystalline silicon transistor |
| CN108766870A (en) * | 2018-05-31 | 2018-11-06 | 武汉华星光电技术有限公司 | The production method and LTPS TFT substrates of LTPS TFT substrates |
| WO2019227790A1 (en) * | 2018-05-31 | 2019-12-05 | 武汉华星光电技术有限公司 | Method for manufacturing ltps tft substrate and ltps tft substrate |
| US11088183B2 (en) | 2018-05-31 | 2021-08-10 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Manufacturing method of low temperature poly-silicon (LTPS) thin film transistor (TFT) substrate and the LTPS TFT substrate |
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Application publication date: 20151125 |