CN103730364B - Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof and display device - Google Patents

Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof and display device Download PDF

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Publication number
CN103730364B
CN103730364B CN201210389726.XA CN201210389726A CN103730364B CN 103730364 B CN103730364 B CN 103730364B CN 201210389726 A CN201210389726 A CN 201210389726A CN 103730364 B CN103730364 B CN 103730364B
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layer
low
source electrode
insulating barrier
film transistor
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CN103730364A (en
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刘侑宗
李淂裕
黄建达
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Innolux Shenzhen Co Ltd
Innolux Corp
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Innolux Shenzhen Co Ltd
Innolux Display Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Abstract

The invention relates to a low-temperature polycrystalline silicon thin film transistor, a manufacturing method thereof and a display device. In the manufacturing process, metal thin film layers are formed between a source electrode and a first conducting layer and between a drain electrode and the first conducting layer, and metal silicide is formed through reaction between the metal thin film layers and polycrystalline silicon, wherein the source electrode and the drain electrode are composed of the polycrystalline silicon; then the source electrode and the drain electrode can be activated under low temperature, and the process temperature of the low-temperature polycrystalline silicon thin film transistor can be limited under 350 DEG C.

Description

Low-temperature polysilicon film transistor, its preparation method and display device
Technical field
The present invention is with regard to a kind of low-temperature polysilicon film transistor, its preparation method and display device, espespecially a kind of in The preparation method reducing annealing times in technique and reducing the low-temperature polysilicon film transistor of technological temperature.
Background technology
Using liquid crystal display flat-panel screens now, to have power saving, Low emissivity, light weight etc. excellent due to liquid crystal display more Point, having become main flow commodity on the market, and the thin film transistor (TFT) in liquid crystal display now is to be broadly divided into two kinds:By non- Crystal silicon (Amorphous-Silicon;A-Si made by) or by polysilicon (Poly-Silicon;P-Si) made, and current Thin film transistor (TFT) is with the technique of non-crystalline silicon as main flow, and correlation technique is compared down also more ripe.However, due to polysilicon Carrier degree of excursion (Mobility) is more than 100 times of non-crystalline silicon, and has high brightness, high-resolution, low power consumption, frivolous etc. excellent Point, therefore, the manufacturing technology of Polysilicon Liquid Crystal display is by substantial amounts of research.
In Polysilicon Liquid Crystal display technology, with low temperature polycrystalline silicon (Low Temperature PolySilicon;LTPS) For the main manufacturing technology of a new generation.Because the display of low temperature polysilicon process is more frivolous, by assembly microminiaturization, and can integrate More electronic circuits, make low-temperature polysilicon film transistor miniaturization, therefore can reduce the weight of product and manufacturing cost is lower Honest and clean, therefore attracted attention on liquid crystal display market.
It is well known, however, that low-temperature polysilicon film transistor technique include hydrogenate (hydrogenation), go hydrogenate (dehydrogenation) and dopant activation (dopantactivation) process, all need again via heat or laser energy Process.Wherein, dopant activation is source electrode and the drain electrode low resistance that the impurity activation of doping makes polysilicon layer, turns off Magnitude of voltage improves.However, using laser activation cost at a relatively high, and the technique of high temperature then can restricting substrate material selection and Limit the application of low-temperature polysilicon film transistor.Therefore be badly in need of at present one kind can substitute use laser activation doped region and The low-temperature polysilicon film transistor preparation method of high-temperature technology, except cost-effective, more can expand low-temperature polysilicon film brilliant The application mode of body pipe.
Content of the invention
The main object of the present invention is to provide a kind of low-temperature polysilicon film transistor, its preparation method and display to set Standby, the characteristic of the present invention is not require the use of laser activation and adulterates the source electrode of other atoms and drain electrode, but in preparation process In, form a metal film layer in source electrode and drain electrode and the first conductive interlayer, this metal film layer be selected from nickel, titanium, cobalt, with And the group that tungsten metal is formed, through reaction is produced with source electrode and drain electrode by this metal film layer, form metal silicide layer, Then source electrode and drain electrode can be activated under low temperature, not only can eliminate the need for the cost of laser activation, the temperature highest of integrated artistic Controlled be formed on less than 350 DEG C, consequently, it is possible to due to the reduction of integrated artistic temperature, increased the selection of baseplate material, can be utilized In the technique of following a greater variety of display panels.
The preparation method of the low-temperature polysilicon film transistor of the present invention, its method at least comprises the following steps:(A) provide One low-temperature polysilicon film transistor substrate, its structure includes:Substrate;It is formed at the cushion on substrate;It is formed at cushion On polysilicon layer, wherein, polysilicon layer is with source electrode, drain electrode and passage;First insulation layer segment is formed at polysilicon On layer, and expose source electrode and the drain electrode of polysilicon layer;Part is formed at the grid on the first insulating barrier;Part is formed at grid The second insulating barrier on pole and part first insulating barrier;(B) expose this source electrode in low-temperature polycrystalline silicon thin film transistor structure And form a metal film layer in drain electrode;(C) the first conductive layer is formed on metal film layer, and the first conductive layer is to protrude from On second insulating barrier, and carry out activating this dopant during annealing process simultaneously, make metal film layer and source electrode and drain electrode reaction Form metal silicide layer, and this metal silicide layer is present in this source electrode, drain electrode and this metal film layer;And (D) is formed Protective layer on the first conductive layer and the second insulating barrier, to form low-temperature polysilicon film transistor.
In step (A) as above, the thickness of polysilicon layer is preferably 30nm-100nm, and polysilicon layer is via non- The multiple crystallization of crystal silicon layer laser annealing is formed after processing.The thickness of cushion is for 100nm-400nm, and its material is at least One is selected from the group that silicon oxide and silicon nitride are formed.And the thickness of the first insulating barrier is for 40nm-300nm, its material is also At least one is selected from the group that silicon oxide and silicon nitride are formed.Grid is made using metal materials such as molybdenum, tungsten or its alloys Become, preferably using molybdenum.
Furthermore, in step (B), the material of metal film layer is to be selected from nickel, titanium, cobalt and tungsten metal institute by least one Composition group, wherein with nickel metal be preferable.Metal film layer can use sputtering method by about tens of for thickness to hundreds of nanometers Metallic film be plated on source electrode and drain electrode on.And in step (C), the first conductive layer be for molybdenum, molybdenum/aluminum/molybdenum or titanium/aluminum/ Titanium therein one is formed, and is formed at the metal silicide layer of source electrode and the minimum range of the metal silicide interlayer of drain electrode (D min) or it is equal to 2 μm.
Present invention additionally comprises a kind of display device, this display device is including low-temperature polysilicon film transistor, its In this low-temperature polysilicon film transistor substrate include:Substrate;Cushion, is formed on substrate;Polysilicon layer, is formed at buffering On layer, wherein, polysilicon layer is source electrode, drain electrode and the passage having and completing dopant;First insulating barrier, is formed at On polysilicon layer;Grid, is formed on the first insulating barrier and corresponds to this passage, and this grid is to be patterned;Second Insulating barrier, is formed on grid and the first insulating barrier;Connecting hole, is through this second insulating barrier with the first insulating barrier and relative It is formed at source electrode and drain electrode;Metal film layer, is formed at the connecting hole at place in source electrode and drain electrode;First conductive layer, shape Become on this metal film layer, and the first conductive layer is to protrude from the second insulating barrier;Wherein, metal film layer and polysilicon layer Source electrode and drain electrode between there is a metal silicide layer;And, protective layer is formed at the first conductive layer and the second insulating barrier On.
In above-mentioned display device, in low-temperature polysilicon film transistor, substrate is for glass substrate or plastics base Plate, and metal silicide layer is selected from, by least one, group and source electrode and the drain electrode that nickel, titanium, cobalt and tungsten metal are formed React and formed, and the minimum range (D min) of the metal silicide layer and the metal silicide interlayer of drain electrode being located at source electrode needs More than or equal to 2 μm.
The metal silicide layer being formed between source electrode and drain electrode and metal film layer be by least one be selected from nickel, titanium, The polysilicon layer of the group that cobalt and tungsten metal are formed and source electrode and drain electrode reacts and is formed, and be located at this source electrode should Metal silicide layer is more than or equal to 2 μm with the minimum range (D min) of this metal silicide interlayer of this drain electrode.Furthermore, the One conductive layer is to be formed by molybdenum, molybdenum/aluminum/molybdenum or titanium/aluminum/titanium therein
Metal film layer between source electrode and drain electrode can be reacted when the annealing process with the polysilicon draining with forming source electrode Become metal silicide, and this metal silicide is distributed in heavily doped polysilicon layer, or be diffused into lightly doped polysilicon Layer, but this metal silicide is the channel region that can not be diffused into polysilicon, but the distance between metal silicide can be via control The temperature and time of system annealing, makes this metal silicide can't be diffused into this channel region, and such as annealing temperature is for 330 DEG C, Time is 1 to 2 hour, and regulate and control to be located at this source electrode of this channel region both sides and this draw must be extremely between this metal silicide in area Keep 2 to 3 μm of interval less, to maintain the operating function of channel.And this metal silicide can reduce this source electrode with this drain into During the activation of row dopant, required activation evergy, therefore can reduce the temperature of activation, by low-temperature polysilicon film transistor Technological temperature reduce, be a great improvement for low-temperature polysilicon film transistor technique.
Brief description
For enabling auditor to the object, the technical characteristics and the effect of the present invention, do further understanding and understanding, with Under enumerate embodiment cooperation accompanying drawing, describe in detail as follows, wherein:
Figure 1A-Fig. 1 O is the Making programme of the low-temperature polysilicon film transistor of the present invention.
Fig. 2A and Fig. 2 B is the aspect of metal silicide layer in the present invention.
Specific embodiment
The preferable enforcement aspect of the low-temperature polycrystalline silicon thin film transistor structure of the present invention is as shown in Fig. 1 O, and this structure is relatively Good technique is as shown in Figure 1A -1O.
The low-temperature polycrystalline silicon thin film transistor structure of the present invention as depicted in figure im, including control zone and pixel region, controls Area includes nmos pass transistor area and PMOS transistor area, and pixel region includes nmos pass transistor area, the following institute of its preparation method State.
First, as shown in Figure 1A, provide a substrate, the silicon nitride buffering that this substrate includes substrate 100, is formed on substrate Layer 101 and be formed at oxidation silicon buffer layer 102 on nitridation silicon buffer layer 101, amorphous silicon layer 103 is formed on this substrate, The thickness of amorphous silicon layer 103 is about 30nm-100nm.Through laser annealing, amorphous silicon layer 103 is converted into polysilicon layer 104, such as schemes Shown in 1B, form one first photoresist 105 on polysilicon layer 104 using Lithography Etching technique, after etching polysilicon layer 104, Again the structure that the first photoresist 105 obtains as shown in Figure 1 C is removed with chemical solvent, wherein, left polysilicon layer region is to become Nmos pass transistor area 1041 and the PMOS transistor area 1042 of one control zone 10, and right polysilicon layer is to become a pixel region 11 Nmos pass transistor area 1043.
Then, form one second photoresist 106 in the PMOS transistor area 1042 of control zone 10, as shown in figure ip, to base To form passage (Channel doping), dosage is about 1E11-1E12 to the dopant of plate boron implant.As referring to figure 1e, then It is partially formed the 3rd photoetching in the nmos pass transistor area 1041 of control zone 10 and the nmos pass transistor area 1043 of pixel region 11 Glue 107, the dopant to the phosphorus of the polysilicon layer implantation weight concentration exposing, its dosage is about 1E14-1E15, in control zone Nmos pass transistor 1043 formation source electrode 104a, 104c of 10 nmos pass transistor 1041 and pixel region 11 and drain electrode 104b, After 104e, remove the 3rd photoresist 107.
As shown in fig. 1f, in polysilicon layer and oxidation silicon buffer layer 102 on formed the first insulating layer of silicon oxide 108 and After first silicon nitride dielectric layer 109, a grid conducting layer 110, this Gate Electrode Conductive are formed on the first silicon nitride dielectric layer 109 Layer 110 is to be constituted by molybdenum, and forms the 3rd photoresist 111 on grid conducting layer 110, using photoetching and etching work Skill, forms grid 112, as shown in Figure 1 G, recycles grid 112 as photoresist, this structure is implanted to the phosphorus of light concentration Dopant (Light Doping Drain), its dosage is about 1E12-1E14, formed lightly doped district 104f, 104g, 104h, 104i, 104j, 104k, 104l and 104l '.Then, as shown in fig. 1h, form one the 4th photoresist 113 in control zone 10 In the nmos pass transistor area 1043 of nmos pass transistor area 1041 and pixel region 11, expose the PMOS transistor area of control zone 10 1042, and its structure is implanted with the boron doping of weight concentration, its dosage is about 1E14-1E15, to form the PMOS crystalline substance of control zone 10 The source electrode 104m in body area under control 1042 and drain electrode 104n.
Then, as shown in Figure 1 I, after removing the 4th photoresist 113, in grid 112 and the first silicon nitride dielectric layer The second silicon nitride dielectric layer 114 being formed on 109, its thickness is about hundreds of nanometers, shape on the second silicon nitride dielectric layer 114 Become the second insulating layer of silicon oxide 115, its thickness is about hundreds of nanometers, and 115 formation the 5th on the second insulating layer of silicon oxide Photoresist 116.As shown in figure ij, using photoetching and etch process, multiple connecting holes 117 are formed to expose control zone 10 Nmos pass transistor area 1041, the PMOS transistor area 1042 of control zone 10 and the nmos pass transistor area 1043 of pixel region 11 Source electrode 104a, 104m, 104c and drain electrode 104b, 104n, 104b, then, in the source electrode 104a exposing, 104m, 104c, drain electrode After forming one layer of thin nickel metal film layer 118 on 104b, 104n, 104b and connecting hole 117, more sequentially in thin nickel metal film layer Formation of deposits one first conductive layer 119 on 118, this first conductive layer 119 is that the multiple layer metal deposition for molybdenum/aluminum/molybdenum forms.
Its form such as Fig. 2A, after the completion of this thin nickel metal film layer 118 with this first conductive layer 119 deposition, it can be carried out Annealing process, and annealing process is first to improve ambient temperature to after the predetermined temperature that will be annealed, more quickly reduce the temperature to Ambient temperature, thus, can activate the alloy of its heavily doped region of polysilicon layer 20, lightly doped district and channel region in annealing process Matter, as shown in figs. 2 a and 2b, including first conductive layer 22, makes thin nickel metal film layer 23 and via being contacted with it The nickel silicide layer 24 that source electrode produces reaction with drain electrode and formed, and control the time of its annealing process to make this nickel silicide 24 at this source electrode of heavily doped polysilicon layer 20 and this drain electrode and layer diffusion at this thin nickel metal film layer, and can be formed at this Minimum range (D min) between nickel silicide between source electrode and this drain electrode at least need apart from 2-3 μm (containing) more than, to keep good Good transistor properties.Presence due to thin nickel metal film layer 118, it is possible to decrease the heavily doped region of polysilicon layer, lightly doped district, with And in channel region dopant activation temperature.
Table one:Nickel silicide annealing process time and diffusion length
Then, form the 6th photoresist 121 on this first conductive layer 119 as shown in figure ik, recycle photoetching and etching work Skill, patterning the first conductive layer 119 with, as can be seen in figure il, formed control zone 10 and pixel region 11 source electrode 104a, 104m, 104c and the first conductive layer 119 of drain electrode 104b, 104n, 104d electric connection.
Then, as depicted in figure im, form a protective layer 123 in the first conductive layer 119 and the second insulating layer of silicon oxide 115 On, and form connecting hole 124 in the protective layer 123 of pixel region 11, then, as shown in Fig. 1 N, formed by indium tin oxide (ITO) The second conductive layer 125 being formed, and this second conductive layer 125 of this case is for ITO conductive layer, this second conductive layer 125 sets On protective layer 123, and connecting hole 124 can be filled up, re-form one the 7th photoresist 126 afterwards in pixel region 11.As Fig. 1 O institute Show, remove the second conductive layer 125 of control zone 10 top using photoetching and etch process, and the low temperature being formed as shown in Fig. 1 O is many Polycrystal silicon film transistor.
Include via the low-temperature polysilicon film transistor manufactured by above-mentioned preparation method:Substrate;Cushion, is formed at On substrate;Polysilicon layer, is formed on cushion, and wherein, polysilicon layer is with source electrode, drain electrode and passage;First is exhausted Edge layer, is partly formed on polysilicon layer, and exposes source electrode and the drain electrode of polysilicon layer;Grid, is partly formed at first On insulating barrier;Second insulating barrier, is partly formed on grid and part first insulating barrier;First conductive layer, is formed at source electrode And in drain electrode, and source electrode and drain electrode form a metal film layer, this metal film layer and this source electrode with the first conductive interlayer Drain and formed a metal silicide layer with this, and the first conductive layer is to protrude from the second insulating barrier;Protective layer is formed at On one conductive layer and the second insulating barrier;Second conductive layer, is formed on the protective layer of pixel region.
Above-described embodiment explanation merely for convenience and illustrate, the interest field that the present invention is advocated is from should be with right It is defined described in claimed range, rather than be only limitted to above-described embodiment.

Claims (18)

1. a kind of preparation method of low-temperature polysilicon film transistor, the method at least includes:
(A) a low-temperature polysilicon film transistor substrate is provided, including:One substrate;One cushion is formed on this substrate;More than one Crystal silicon layer is formed on this cushion, and wherein, this polysilicon layer has a source electrode, a drain electrode and a passage;One first insulation Layer segment is formed on this polysilicon layer, and exposes this source electrode and this drain electrode of this polysilicon layer;One grid, part is formed On this first insulating barrier;One second insulation layer segment is formed on this grid and this first insulating barrier of part;
(B) form a metal film layer on this source electrode exposing in this low-temperature polycrystalline silicon thin film transistor structure and drain electrode;
(C) one first conductive layer is formed on this metal film layer, this first conductive layer covers and is located in this source electrode and drain electrode This metal film layer, and this first conductive layer protrudes from this second insulating barrier, and carry out an annealing process, make this metallic film Layer and this source electrode and this drain electrode react formation one metal silicide layer;And
(D) form a protective layer on this first conductive layer and this second insulating barrier, brilliant to form a low-temperature polysilicon film Body pipe.
2. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (A), this cushion At least one is selected from the group that silicon oxide and silicon nitride are formed.
3. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (A), this is first exhausted Edge layer at least one is selected from the group that silicon oxide layer and silicon nitride layer are formed.
4. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (A), this grid is Molybdenum, tungsten or its alloy.
5. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (C), this is second exhausted Edge layer at least one is selected from the group that silicon oxide layer and silicon nitride layer are formed.
6. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (B), this metal foil The material of film layer is selected from, by least one, the group that nickel, titanium, cobalt and tungsten metal are formed.
7. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (C), this metallic silicon Compound layer is located at this metal film layer and this source electrode and this drain electrode, and controls this annealing process time, makes this gold of this source electrode The minimum range belonging to this metal silicide interlayer of silicide layer and this drain electrode is more than or equal to 2 μm.
8. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (C), this first is led Electric layer is molybdenum, molybdenum/aluminum/molybdenum or titanium/aluminum/titanium one of them formed.
9. a kind of display device, including:
One display floater, shows the image being provided by a low-temperature polysilicon film transistor substrate, and this low temperature polycrystalline silicon is thin Film transistor substrate also includes:
One substrate;
One cushion, is formed on this substrate;
One polysilicon layer, is formed on this cushion, and wherein, this polysilicon layer has a source electrode, the leakage completing dopant Pole and a passage;
One first insulating barrier, is formed on this polysilicon layer;
One grid, is formed on this first insulating barrier and corresponds to this passage, and this grid is patterned;
One second insulating barrier, is formed on this grid and this first insulating barrier;
At least one first connecting hole, runs through this second insulating barrier and with this first insulating barrier and relative is formed at this source electrode and this leakage At pole;
One metal film layer, is formed at this first connecting hole at this source electrode and this drain electrode;
One first conductive layer, is formed on this metal film layer, and this first conductive layer protrudes from this second insulating barrier;
One protective layer is formed on this first conductive layer and this second insulating barrier;
One second connecting hole is formed in this protective layer and runs through this protective layer, is relatively formed at this drain electrode;And
One second conductive layer, on this protective layer, and inserts this first connecting hole and this second connecting hole, and part this second Conductive layer in this second connecting hole with this protective layer directly contact, this second conductive layer and this first conductive layer are electrically connected with;
Wherein, a metal silicide layer is located between this source electrode and this drain electrode of this metal film layer and polysilicon layer, and part Metal silicide layer covered by this first insulating barrier.
10. display device as claimed in claim 9, wherein, this substrate is glass substrate or plastic base.
11. display devices as claimed in claim 9, wherein, this cushion at least is selected from silicon oxide and silicon nitride is formed Group.
12. display devices as claimed in claim 9, wherein, this first insulating barrier at least one is selected from silicon oxide layer and silicon nitride The group that layer is formed.
13. display devices as claimed in claim 9, wherein, this grid is molybdenum, tungsten or its alloy.
14. display devices as claimed in claim 9, wherein, this second insulating barrier at least one is selected from silicon oxide layer and silicon nitride The group that layer is formed.
This metal silicide layer of 15. display devices as claimed in claim 9, wherein this source electrode and this metallic silicon of this drain electrode The minimum range of compound interlayer is greater than or equal to 2 μm.
16. display devices as claimed in claim 9, wherein, this metal silicide layer by least one be selected from nickel, titanium, cobalt and The group that tungsten metal is formed reacts and is formed with this source electrode and this drain electrode.
17. display devices as claimed in claim 9, wherein, the distance of this metal silicide interlayer is more than or equal to 2 μm.
18. display devices as claimed in claim 9, wherein, this first conductive layer is molybdenum, molybdenum/aluminum/molybdenum or titanium/aluminum/titanium its In one formed.
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TWI578443B (en) 2015-09-22 2017-04-11 友達光電股份有限公司 Polycrystalline silicon thin film transistor device and method of fabricating the same
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