CN103730364A - Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof and display device - Google Patents
Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof and display device Download PDFInfo
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- CN103730364A CN103730364A CN201210389726.XA CN201210389726A CN103730364A CN 103730364 A CN103730364 A CN 103730364A CN 201210389726 A CN201210389726 A CN 201210389726A CN 103730364 A CN103730364 A CN 103730364A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 87
- 239000010409 thin film Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 28
- 230000008569 process Effects 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 144
- 229920005591 polysilicon Polymers 0.000 claims description 75
- 239000010408 film Substances 0.000 claims description 63
- 230000004888 barrier function Effects 0.000 claims description 39
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 17
- 238000000576 coating method Methods 0.000 claims description 17
- 229910052750 molybdenum Inorganic materials 0.000 claims description 17
- 239000011733 molybdenum Substances 0.000 claims description 17
- 238000002360 preparation method Methods 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 14
- 239000010936 titanium Substances 0.000 claims description 14
- 229910052719 titanium Inorganic materials 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 239000002019 doping agent Substances 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- 239000004411 aluminium Substances 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000010941 cobalt Substances 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000004913 activation Effects 0.000 description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 229910021334 nickel silicide Inorganic materials 0.000 description 4
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006356 dehydrogenation reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000004064 recycling Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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Abstract
The invention relates to a low-temperature polycrystalline silicon thin film transistor, a manufacturing method thereof and a display device. In the manufacturing process, metal thin film layers are formed between a source electrode and a first conducting layer and between a drain electrode and the first conducting layer, and metal silicide is formed through reaction between the metal thin film layers and polycrystalline silicon, wherein the source electrode and the drain electrode are composed of the polycrystalline silicon; then the source electrode and the drain electrode can be activated under low temperature, and the process temperature of the low-temperature polycrystalline silicon thin film transistor can be limited under 350 DEG C.
Description
Technical field
The invention relates to a kind of low-temperature polysilicon film transistor, its preparation method and display device, espespecially a kind of preparation method who reduces annealing number of times and reduce the low-temperature polysilicon film transistor of technological temperature in technique.
Background technology
Flat-panel screens is used liquid crystal display more now, due to liquid crystal display, there is the advantages such as power saving, low radiation, light weight, becoming on the market main flow commodity, and thin-film transistor in liquid crystal display is now to be mainly divided into two kinds: by amorphous silicon (Amorphous-Silicon; A-Si) made or by polysilicon (Poly-Silicon; P-Si) made, and current thin film transistor is that to take the technique of amorphous silicon be main flow, correlation technique compare under also comparatively ripe.Yet, because the carrier degree of excursion (Mobility) of polysilicon is the more than 100 times of amorphous silicon, and there is high brightness, high-resolution, low power consumption, the advantage such as frivolous, therefore, the manufacturing technology of polysilicon liquid crystal display is by a large amount of research.
In polysilicon LCD Technology, with low temperature polycrystalline silicon (Low Temperature PolySilicon; LTPS) be the main manufacturing technology of a new generation.Because the display of low temperature polycrystalline silicon technique is more frivolous, can be by assembly microminiaturization, and integrate more polyelectron circuit, make low-temperature polysilicon film transistor miniaturization, therefore can reduce weight and the manufacturing cost more cheap of product, therefore attracted attention on liquid crystal display market.
Yet, known low-temperature polysilicon film transistor technique comprises hydrogenation (hydrogenation), dehydrogenation (dehydrogenation) and dopant activation (dopantactivation) process, all needs via heat or laser energy, to process again.Wherein, dopant activation is by the impurity activation of doping, makes source electrode and the drain electrode low resistance of polysilicon layer, makes to close magnitude of voltage and improves.Yet, use the cost of laser activation quite high, and the selection that the technique of high temperature can restricting substrate material and limit the application of low-temperature polysilicon film transistor.Therefore be badly in need of at present a kind of energy and substitute the low-temperature polysilicon film transistor preparation method who uses laser activation doped region and high-temperature technology, except saving cost, more can expand the application mode of low-temperature polysilicon film transistor.
Summary of the invention
Main purpose of the present invention is that a kind of low-temperature polysilicon film transistor is being provided, its preparation method, and display device, characteristic of the present invention is not need to use laser activation adulterate source electrode and the drain electrode of other atoms, but in preparation process, in between source electrode and drain electrode and the first conductive layer, form a metal film layer, this metal film layer is to be selected from nickel, titanium, cobalt, and the group that forms of tungsten metal, through metal film layer thus, produce and react with source electrode and drain electrode, form metal silicide layer, can under low temperature, activate source electrode and drain electrode, not only can save the cost that uses laser activation, the highest being controlled in below 350 ℃ of temperature of integrated artistic, thus, reduction due to integrated artistic temperature, increased the selection of baseplate material, can be used in the technique of following a greater variety of display panels.
The preparation method of low-temperature polysilicon film transistor of the present invention, its method at least comprises the following steps: a low-temperature polysilicon film transistor substrate (A) is provided, and its structure comprises: substrate; Be formed at the resilient coating on substrate; Be formed at the polysilicon layer on resilient coating, wherein, polysilicon layer is to have source electrode, drain electrode and passage; The first insulating barrier is partly formed on polysilicon layer, and exposes source electrode and the drain electrode of polysilicon layer; Part is formed at the grid on the first insulating barrier; Part is formed at the second insulating barrier on grid and part the first insulating barrier; (B) in low-temperature polycrystalline silicon thin film transistor structure, expose the upper metal film layer that forms of this source electrode and drain electrode; (C) on metal film layer, form the first conductive layer, and the first conductive layer is to protrude from the second insulating barrier, and activate this dopant while carrying out annealing process simultaneously, make metal film layer react and form metal silicide layer with source electrode and drain electrode, and this metal silicide layer is present in this source electrode, drain electrode and this metal film layer; And (D) form protective layer on the first conductive layer and the second insulating barrier, to form low-temperature polysilicon film transistor.
In step as above (A), the thickness of polysilicon layer is preferably 30nm-100nm, and polysilicon layer is to form after processing via the multiple crystallization of amorphous silicon layer laser annealing.The thickness of resilient coating is to be 100nm-400nm, and its material is at least one group that silica and silicon nitride form that is selected from.And the thickness of the first insulating barrier is to be 40nm-300nm, its material is also at least one group that silica and silicon nitride form that is selected from.Grid is to use the metal materials such as molybdenum, tungsten or its alloy made, is preferably use molybdenum.
Moreover in step (B), the material of metal film layer is selected from by least one the group that nickel, titanium, cobalt and tungsten metal form, wherein with nickel metal for better.Metal film layer can be used sputtering method that thickness is about to tens of metallic films to hundreds of nanometers and be plated in source electrode and drain electrode.And in step (C), the first conductive layer is to be molybdenum, molybdenum/aluminium/molybdenum or titanium/aluminium/titanium one being formed wherein, and is formed at the minimum range (D min) of the metal silicide layer of source electrode and the metal silicide interlayer of drain electrode or equals 2 μ m.
The present invention also comprises a kind of display device, and this display device is to comprise low-temperature polysilicon film transistor, and wherein this low-temperature polysilicon film transistor substrate comprises: substrate; Resilient coating, is formed on substrate; Polysilicon layer, is formed on resilient coating, and wherein, polysilicon layer is source electrode, drain electrode and the passage with dopant; The first insulating barrier is to be formed on polysilicon layer; Grid be formed on the first insulating barrier and correspond to this passage, and this grid is to be patterned; The second insulating barrier, is formed on grid and the first insulating barrier; Connecting hole is run through this second insulating barrier and the first insulating barrier and be relatively formed at source electrode and drain electrode place; Metal film layer, is formed at the upper connecting hole of locating of source electrode and drain electrode; The first conductive layer, is formed on this metal film layer, and the first conductive layer is to protrude from the second insulating barrier; Wherein, between the source electrode of metal film layer and polysilicon layer and drain electrode, there is a metal silicide layer; And protective layer is formed on the first conductive layer and the second insulating barrier.
In above-mentioned display device, in low-temperature polysilicon film transistor, substrate is to be glass substrate or plastic base, and metal silicide layer is selected from the group that nickel, titanium, cobalt and tungsten metal form and is reacted and form with source electrode and drain electrode by least one, and the minimum range (D min) that is positioned at the metal silicide layer of source electrode and the metal silicide interlayer of drain electrode need be more than or equal to 2 μ m.
Be formed at metal silicide layer between source electrode and drain electrode and metal film layer and be selected from the group that nickel, titanium, cobalt and tungsten metal form and react and form with the polysilicon layer of source electrode and drain electrode by least one, and the minimum range (D min) that is positioned at this metal silicide layer of this source electrode and this metal silicide interlayer of this drain electrode is more than or equal to 2 μ m.Moreover the first conductive layer is to be molybdenum, molybdenum/aluminium/molybdenum or titanium/aluminium/titanium one being formed wherein
Metal film layer between source electrode and drain electrode and the polysilicon of formation source electrode and drain electrode can react and become metal silicide when annealing process, and this metal silicide is distributed in heavily doped polysilicon layer, or be diffused into lightly doped polysilicon layer, but this metal silicide is the channel region that can not be diffused into polysilicon, yet the distance between metal silicide can be via the temperature and time of controlling annealing, make this metal silicide can't be diffused into this channel region, if annealing temperature is to be 330 ℃, time is 1 to 2 hour, and regulation and control between this metal silicide in this source electrode Yu Gaiji district of these both sides, channel region, must at least keep between 2 to 3 μ m every, to maintain the operating function of channel.And this metal silicide needed activation evergy can reduce this source electrode and this drain electrode and carry out dopant activation time, therefore can reduce the temperature of activation, the technological temperature of low-temperature polysilicon film transistor is reduced, and is a great improvement for low-temperature polysilicon film transistor technique.
Accompanying drawing explanation
For making auditor do further understanding and understanding to the object, the technical characteristics and the effect of the present invention, below enumerate embodiment and coordinate accompanying drawing, be described in detail as follows, wherein:
Figure 1A-Fig. 1 O is the making flow process of low-temperature polysilicon film transistor of the present invention.
Fig. 2 A and Fig. 2 B are the aspects of metal silicide layer in the present invention.
Embodiment
The better enforcement aspect of low-temperature polycrystalline silicon thin film transistor structure of the present invention is as shown in Fig. 1 O, and the preferred process of this structure is as shown in Figure 1A-1O.
Low-temperature polycrystalline silicon thin film transistor structure of the present invention, as shown in Fig. 1 M, comprises controlled area and pixel region, and controlled area comprises nmos pass transistor district and PMOS transistor area, and pixel region has comprised nmos pass transistor district, and its preparation method is as described below.
First, as shown in Figure 1A, one substrate is provided, this substrate comprises substrate 100, is formed at the silicon nitride resilient coating 101 on substrate and is formed at the silica resilient coating 102 on silicon nitride resilient coating 101, amorphous silicon layer 103 is formed on this substrate, and the thickness of amorphous silicon layer 103 is about 30nm-100nm.Through laser annealing, convert amorphous silicon layer 103 to polysilicon layer 104, as shown in Figure 1B, utilize photoengraving carving technology to form one first photoresist 105 on polysilicon layer 104, after etching polysilicon layer 104, with chemical solvent, remove the first photoresist 105 again and obtain structure as shown in Figure 1 C, wherein, left polysilicon layer region is the nmos pass transistor district 1041 and PMOS transistor area 1042 that becomes a controlled area 10, and right-hand polysilicon layer is the nmos pass transistor district 1043 that becomes a pixel region 11.
Then, form one second photoresist 106 in controlled area 10 PMOS transistor area 1042, as shown in Fig. 1 D, to the dopant of substrate boron implant, to form passage (Channel doping), dosage is about 1E11-1E12.As shown in Fig. 1 E, in controlled area, 1043 tops, nmos pass transistor district of 10 nmos pass transistor district 1041 and pixel region 11 divide formation the 3rd photoresist 107 again, the polysilicon layer exposing is implanted to the dopant of the phosphorus of heavy concentration, its dosage is about 1E14-1E15, in the nmos pass transistor 1041 of controlled area 10 and the nmos pass transistor of pixel region 11 1043, form after source electrode 104a, 104c and drain electrode 104b, 104e, remove the 3rd photoresist 107.
As shown in Fig. 1 F, on polysilicon layer and silica resilient coating 102, form after the first insulating layer of silicon oxide 108 and the first silicon nitride dielectric layer 109, on the first silicon nitride dielectric layer 109, form again a grid conducting layer 110, this grid conducting layer 110 is formed by molybdenum, and on grid conducting layer 110, form the 3rd photoresist 111, utilize photoetching and etch process, form grid 112, as shown in Figure 1 G, recycling grid 112 is as photoresist, for this structure, implant the dopant (Light Doping Drain) of the phosphorus of light concentration, its dosage is about 1E12-1E14, form light doping section 104f, 104g, 104h, 104i, 104j, 104k, 104l, and 104l '.Then, as shown in Fig. 1 H, form one the 4th photoresist 113 in the nmos pass transistor district 1041 of controlled area 10 and the nmos pass transistor district 1043 of pixel region 11, expose the PMOS transistor area 1042 of controlled area 10, and the boron doping of its structure being implanted to heavy concentration, its dosage is about 1E14-1E15, with source electrode 104m and the drain electrode 104n of the PMOS transistor area 1042 in formation control district 10.
Then, as shown in Figure 1 I, remove after the 4th photoresist 113, in grid 112 and the first silicon nitride dielectric layer 109 on the second silicon nitride dielectric layer 114 of forming, its thickness is about hundreds of nanometers, on the second silicon nitride dielectric layer 114, form the second insulating layer of silicon oxide 115, its thickness is about hundreds of nanometers again, and 115 forms the 5th photoresists 116 on the second insulating layer of silicon oxide.As shown in Fig. 1 J, utilize photoetching and etch process, form a plurality of connecting holes 117 to expose the nmos pass transistor district 1041 of controlled area 10, the PMOS transistor area 1042 of controlled area 10, and the source electrode 104a in the nmos pass transistor district 1043 of pixel region 11, 104m, 104c and drain electrode 104b, 104n, 104b, then, in the source electrode 104a exposing, 104m, 104c, drain electrode 104b, 104n, 104b, and on connecting hole 117, form after one deck thin nickel metal film layer 118, sequentially on thin nickel metal film layer 118, deposition forms one first conductive layer 119 again, this first conductive layer 119 is that the multiple layer metal deposition for molybdenum/aluminium/molybdenum forms.
Its form is as Fig. 2 A, after this thin nickel metal film layer 118 has deposited with this first conductive layer 119, it can carry out annealing process, and annealing process is first to improve ambient temperature after the predetermined temperature that will anneal, fast reducing temperature is to ambient temperature again, thus, in annealing process, can activate polysilicon layer 20 its heavily doped regions, the dopant of light doping section and channel region, as shown in Fig. 2 A and 2B, comprising the first conductive layer 22, make thin nickel metal film layer 23, and produce with drain electrode a nickel silicide layer 24 that reacts and form via the source electrode contacting with it, and control its annealing process time chien shih this nickel silicide 24 can be in this source electrode and this drain electrode place and this thin nickel metal film layer place layer diffusion of heavily doped polysilicon layer 20, and the minimum range (D min) being formed between the nickel silicide between this source electrode and this drain electrode at least needs apart from more than 2-3 μ m (containing), to keep good transistor properties.Due to the existence of thin nickel metal film layer 118, can reduce the activation temperature of dopant in heavily doped region, light doping section and the channel region of polysilicon layer.
Table one: nickel silicide annealing process time and diffusion length
Then, as shown in Fig. 1 K, on this first conductive layer 119, form the 6th photoresist 121, recycling photoetching and etch process, patterning the first conductive layer 119 with, as shown in Fig. 1 L, the first conductive layer 119 that formation control district 10 and pixel region 11 source electrode 104a, 104m, 104c and drain electrode 104b, 104n, 104d are electrically connected.
Then; as shown in Fig. 1 M; form a protective layer 123 on the first conductive layer 119 and the second insulating layer of silicon oxide 115, and form connecting hole 124 in pixel region 11 protective layer 123, then; as shown in Fig. 1 N; the second conductive layer 125 that formation is comprised of indium tin oxide (ITO), and this second conductive layer 125 of this case is to be ITO conductive layer, this second conductive layer 125 is located on protective layer 123; and can fill up connecting hole 124, form again afterwards one the 7th photoresist 126 in pixel region 11.As shown in Fig. 1 O, utilize photoetching and etch process to remove the second conductive layer 125 of 10 tops, controlled area, and form the low-temperature polysilicon film transistor as shown in Fig. 1 O.
The low-temperature polysilicon film transistor manufacturing via above-mentioned preparation method comprises: substrate; Resilient coating, is formed on substrate; Polysilicon layer, is formed on resilient coating, and wherein, polysilicon layer is to have source electrode, drain electrode and passage; The first insulating barrier, part is formed on polysilicon layer, and exposes source electrode and the drain electrode of polysilicon layer; Grid, part is formed on the first insulating barrier; The second insulating barrier, part is formed on grid and part the first insulating barrier; The first conductive layer, be formed in source electrode and drain electrode, and between source electrode and drain electrode and the first conductive layer, form a metal film layer, this metal film layer and this source electrode and this drain electrode also form a metal silicide layer, and the first conductive layer is to protrude from the second insulating barrier; Protective layer is formed on the first conductive layer and the second insulating barrier; The second conductive layer, is formed on the protective layer of pixel region.
Above-described embodiment is only to give an example for convenience of description, and the interest field that the present invention advocates should be as the criterion certainly described in claim scope, but not only limits to above-described embodiment.
Claims (18)
1. a preparation method for low-temperature polysilicon film transistor, the method at least comprises:
(A) provide a low-temperature polysilicon film transistor substrate, comprising: a substrate; One resilient coating is formed on this substrate; One polysilicon layer is formed on this resilient coating, and wherein, this polysilicon layer has one source pole, drain electrode and a passage; One first insulating barrier is partly formed on this polysilicon layer, and exposes this source electrode and this drain electrode of this polysilicon layer; One grid, part is formed on this first insulating barrier; One second insulating barrier is partly formed on this grid and this first insulating barrier of part;
(B) the upper metal film layer that forms of this source electrode exposing in this low-temperature polycrystalline silicon thin film transistor structure and drain electrode;
(C) on this metal film layer, form one first conductive layer, and this first conductive layer protrudes from this second insulating barrier, and carry out an annealing process, this metal film layer is reacted with this source electrode and this drain electrode and form a metal silicide layer; And
(D) form a protective layer on this first conductive layer and this second insulating barrier, to form a low-temperature polysilicon film transistor.
2. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (A), this resilient coating is at least one is selected from the group that silica and silicon nitride form.
3. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (A), this first insulating barrier is at least one is selected from the group that silicon oxide layer and silicon nitride layer form.
4. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (A), this grid is molybdenum, tungsten or its alloy.
5. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (C), this second insulating barrier is at least one is selected from the group that silicon oxide layer and silicon nitride layer form.
6. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (B), the material of this metal film layer is selected from by least one the group that nickel, titanium, cobalt and tungsten metal form.
7. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (C), this metal silicide layer is positioned at this metal film layer and this source electrode and this drain electrode place, and control this annealing process time, make the minimum range of this metal silicide layer of this source electrode and this metal silicide interlayer of this drain electrode be more than or equal to 2 μ m.
8. the preparation method of low-temperature polysilicon film transistor as claimed in claim 1, wherein, in step (C), this first conductive layer is molybdenum, molybdenum/aluminium/molybdenum or titanium/aluminium/titanium one being formed wherein.
9. a display device, comprising:
One display floater, show the image being provided by a low-temperature polysilicon film transistor substrate, and this low-temperature polysilicon film transistor substrate also comprises:
One substrate;
One resilient coating, is formed on this substrate;
One polysilicon layer, is formed on this resilient coating, and wherein, this polysilicon layer has had one source pole, drain electrode and a passage of dopant;
One first insulating barrier, is formed on this polysilicon layer;
One grid be formed on this first insulating barrier and correspond to this passage, and this grid is patterned;
One second insulating barrier, is formed on this grid and this first insulating barrier;
One connecting hole, runs through this second insulating barrier and this first insulating barrier and is relatively formed at this source electrode and this drain electrode place;
One metal film layer, is formed at this connecting hole of this source electrode and this drain electrode place;
One first conductive layer, is formed on this metal film layer, and this first conductive layer protrudes from this second insulating barrier;
Wherein, a metal silicide layer is between this source electrode and this drain electrode of this metal film layer and polysilicon layer; And
One protective layer is formed on this first conductive layer and this second insulating barrier.
10. display device as claimed in claim 9, wherein, this substrate is glass substrate or plastic base.
11. display devices as claimed in claim 9, wherein, this resilient coating is at least one is selected from the group that silica and silicon nitride form.
12. display devices as claimed in claim 9, wherein, this first insulating barrier is at least one is selected from the group that silicon oxide layer and silicon nitride layer form.
13. display devices as claimed in claim 9, wherein, this grid is molybdenum, tungsten or its alloy.
14. display devices as claimed in claim 9, wherein, this second insulating barrier is at least one is selected from the group that silicon oxide layer and silicon nitride layer form.
15. display devices as claimed in claim 9, wherein the minimum range of this metal silicide layer of this source electrode and this metal silicide interlayer of this drain electrode is to be more than or equal to 2 μ m.
16. display devices as claimed in claim 9, wherein, this metal silicide layer is selected from the group that nickel, titanium, cobalt and tungsten metal form and is reacted and form with this source electrode and this drain electrode by least one.
17. display devices as claimed in claim 9, wherein, the distance of this metal silicide interlayer is more than or equal to 2 μ m.
18. display devices as claimed in claim 9, wherein, this first conductive layer is molybdenum, molybdenum/aluminium/molybdenum or titanium/aluminium/titanium one being formed wherein.
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