CN104124206A - Ltps阵列基板的制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 51
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
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- 238000000151 deposition Methods 0.000 claims abstract description 14
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- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 238000004380 ashing Methods 0.000 claims abstract description 5
- 238000005224 laser annealing Methods 0.000 claims abstract description 5
- 238000002513 implantation Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 13
- 229910004205 SiNX Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 238000002425 crystallisation Methods 0.000 claims description 3
- 230000008025 crystallization Effects 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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Abstract
本发明公开了一种LTPS阵列基板的制造方法,在基板上依次沉积缓冲层和非晶硅层,通过激光退火使得所述非晶硅层晶化为多晶硅层;分别在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶,所述P沟道区域的光刻胶厚度是所述N沟道区域以及所述TFT区域光刻胶厚度的两倍以上,其他部分没有光刻胶;经过多晶硅层干刻后形成多晶硅图案和沟道,然后通过光刻胶灰化处理,使得所述N沟道区域和所述TFT区域较薄的光刻胶被去除,而留下所述P沟道区域的光刻胶。本发明节省设备费用,提高产量,降低了常规8道光罩所带来的设计上的缺陷及制程的难度。
Description
技术领域
本发明涉及薄膜晶体管(TFT)阵列基板,尤其涉及一种LTPS阵列基板的制造方法。
背景技术
液晶显示器件(LCD)或主动式有机电致发光显示器(AMOLED)通过采用电场控制液晶(LC)的透光率显示图像或通过采用电流控制有机发光材料发光显示图像。此类显示器都需要通过薄膜晶体管(TFT)阵列基板来实现电压或电流对像素的驱动及控制功能,该TFT阵列基板包括扫描线、信号线及TFT。为了实现高分辨率的要求,目前TFT阵列基板多采用低温多晶硅(LTPS)的制造工艺,由于TFT阵列基板特别是LTPS基板需要半导体工序和多轮光罩工序,其制造工序很复杂,因此制造成本比较高。
一轮比较完整的光罩工序包括诸如清洗工序、薄膜沉积工序、光刻工序、刻蚀工序、光刻胶剥离和检查工序等多个工序,此外某些需要应用光罩的工序中还包括激光退火及离子注入等工序。目前量产的LTPS阵列基板通常是采用9道或8道光罩的CMOS工艺。
图1示出了CMOS工艺流程中应用到9道光罩的简单工序示意图,依次包括:(1)P-Si Pattern,经过P-Si干刻后形成多晶硅图案,图2a示出了该步骤中使用光罩的示意图;(2)Channel Doping,沟道掺杂,图2b示出了该步骤中使用光罩的截面图;(3)N+Doping(S/D),屏蔽P型区域,对N型区域实行离子注入(源极/漏极);(4)Gate Electrode Deposition(M1),栅极沉积,形成第一金属层,定义出栅极;(5)P+Doping,屏蔽N型区域,对P型区域实行离子注入;(6)Contact Hole,形成接触孔;(7)WiringLayer(M2),布线层沉积,形成第二金属层,定义数据线图案;(8)PLN(Planarization),平坦层沉积,形成接触孔;(9)PixelElectrode,定义像素电极形状。
图3示出了CMOS工艺流程中应用到8道光罩的简单工序示意图,其实质上是将图1所示出的应用到9道光罩的工序流程中的第二步(Channel Doping,沟道掺杂)取消,即不作沟道掺杂,但是应用8道光罩的CMOS工艺存在以下三个方面的缺陷:
1、设计的冗余量较小;如图4a和图4b中可以清晰看出冗余量变小(从2.64V至1.64V),其中,Vcom:0.64V~4.44V(电压差:3.8V),数据信号:0.94V~4.14V,当耦合发生,数据信号变为:0.94-3.8=-2.86V,VgateH:8.5-4.14=4.36V(VGSgate ON);VgateL:-4-(-2.86)=-1.14V(VGSgate OFF);
2、功率损耗更高;去除沟道掺杂工序,会使迁移率受到影响(降低),为了达到同样的输出电流,则需要加大面板的驱动电压,从而使得面板的功耗更高。
3、对Vthn和Vthp的均一性要求更高;由于迁移率下降,需要在设计上降低器件的沟道长度来补偿(提高W/L),这样需要极佳均匀性的短沟道器件,因此必须制备更加均匀的p-Si薄膜,从而加大了制程和设计的难度。
发明内容
针对上述存在的问题,本发明的目的是提供一种可以减少光罩工序数量的LTPS阵列基板,将传统的需要9道光罩工序的CMOS工艺简化为8道光罩工序,减少了工艺步序,节省了设备费用,并克服了现有应用8道光罩工序的CMOS工艺的主要缺陷。
本发明的目的是通过下述技术方案实现的:
一种LTPS阵列基板的制造方法,所述LTPS阵列基板包括N沟道区域、P沟道区域和TFT区域,包括:
在基板上依次沉积缓冲层和非晶硅层,通过激光退火使得所述非晶硅层晶化为多晶硅层;
分别在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶,所述P沟道区域的光刻胶厚度是所述N沟道区域以及所述TFT区域光刻胶厚度的两倍以上,其他部分没有光刻胶;
经过多晶硅层干刻后形成多晶硅图案和沟道,然后通过光刻胶灰化处理,使得所述N沟道区域和所述TFT区域较薄的光刻胶被去除,而留下所述P沟道区域的光刻胶;
屏蔽所述P沟道区域,对所述N沟道区域和所述TFT区域实行离子注入;
屏蔽P型所述N沟道区域、P型所述P沟道区域以及P型所述TFT区域,实行离子注入以形成N型源/漏极区域和N型TFT区域;
栅极电极沉积,形成第一金属层,定义出栅极;
屏蔽N型所述N沟道区域和N型所述TFT区域,实行离子注入以形成P型源/漏极区域;
在所述N沟道区域、所述P沟道区域以及所述TFT区域的源极、漏极、栅极处分别形成接触孔;
布线层沉积,形成第二金属层,并定义数据线图案;
平坦层沉积,并在所述TFT区域形成所述平坦层的接触孔;
涂覆ITO膜层,定义像素电极形状。
上述LTPS阵列基板的制造方法,其中,分别在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶,所述P沟道区域的光刻胶厚度是所述N沟道区域以及所述TFT区域光刻胶厚度的两倍或三倍,其他部分没有光刻胶。
上述LTPS阵列基板的制造方法,其中,在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶采用GTM的方式实现。
上述LTPS阵列基板的制造方法,其中,在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶采用HTM的方式实现。
上述LTPS阵列基板的制造方法,其中,所述缓冲层包括SiNx层和SiOx层,所述SiOx层位于所述SiNx层上方。
上述LTPS阵列基板的制造方法,其中,所述平坦层材料为PC403或PC452。
上述LTPS阵列基板的制造方法,其中,所述布线层为钼铝叠层金属。
与已有技术相比,本发明的有益效果在于:
节省设备费用,提高产量,降低了常规8道光罩所带来的设计上的缺陷及制程的难度。
附图说明
图1示出了现有技术中CMOS工艺流程中应用到9道光罩的简单工序示意图;
图2a示出了现有技术中CMOS工艺流程中应用到9道光罩的第一步工序中应用第一道光罩实现多晶硅图案的截面图;
图2b示出了现有技术中CMOS工艺流程中应用到9道光罩的第二步工序中应用第二道光罩实现沟道掺杂的截面图;
图3示出了现有技术中CMOS工艺流程中应用到8道光罩的简单工序示意图;
图4a示出了现有技术中CMOS工艺采用9道光罩工序的Id和Vgs之间的关系曲线示意图;
图4b示出了现有技术中CMOS工艺采用8道光罩工序的Id和Vgs之间的关系曲线示意图;
图5a示出了基于本发明LTPS阵列基板的制造方法的实施例一的第一步工序中应用光罩实现多晶硅图案的截面图;
图5b示出了基于本发明LTPS阵列基板的制造方法的实施例一的第二步工序中应用同一光罩实现沟道掺杂的截面图;
图6a示出了基于本发明LTPS阵列基板的制造方法的实施例二的第一步工序中应用光罩实现多晶硅图案的截面图;
图6b示出了基于本发明LTPS阵列基板的制造方法的实施例二的第二步工序中应用同一光罩实现沟道掺杂的截面图。
具体实施方式
下面结合原理图和具体操作实施例对本发明作进一步说明。
本发明是将常规应用9道光罩工艺步序中的前两道光罩通过HTM(Half Tone Mask,半色调掩膜)或者GTM(Gray Tone Mask,灰阶掩膜)方式合成一道光罩,并同时保留了沟道掺杂这道工序。
在本发明LTPS阵列基板的制造方法中,LTPS阵列基板包括N沟道区域、P沟道区域和TFT区域。
首先在玻璃基板上依次沉积缓冲层和非晶硅层(a-Si),缓冲层包括SiNx层和SiOx层,SiOx层位于SiNx层上方,再通过激光退火使得非晶硅层晶化为多晶硅层(p-Si)。
实施例一
如图5a和图5b所示,在本发明的第一个实施例中,分别在多晶硅层的P沟道区域、N沟道区域和TFT区域上涂覆光刻胶,P沟道区域的光刻胶厚度恰好是N沟道区域以及TFT区域光刻胶厚度的两倍,TFT区域等其他部分没有光刻胶。经过多晶硅层干刻后形成多晶硅图案和沟道,然后通过光刻胶灰化处理,使得N沟道区域和TFT区域较薄的光刻胶被去除,而留下P沟道区域的光刻胶。
优选的,在多晶硅层的P沟道区域、N沟道区域和TFT区域上涂覆光刻胶的厚度差别是采用GTM(Gray Tone Mask,灰阶掩膜)或者HTM(Half Tone Mask,半色调掩膜)的方式实现。
接着,屏蔽P沟道区域,对N沟道区域和TFT区域实行离子注入,优选采用硼离子注入。
接着,N沟道区域、P型P沟道区域以及P型TFT区域实行离子注入以形成N型源/漏极区域和N型TFT区域。
栅极电极沉积,形成第一金属层,定义出栅极。
屏蔽N型N沟道区域和N型TFT区域,实行离子注入以形成P型源/漏极区域。
在N沟道区域、P沟道区域以及TFT区域的源极、漏极、栅极处分别形成接触孔。
布线层沉积,形成第二金属层,平坦层沉积,涂覆ITO膜层,定义像素电极形状。
优选的,平坦层材料优选为由JSR公司出品的PC403或者PC452,布线层可以优选为钼铝叠层金属(Mo-Al-Mo)。
实施例二
如图6a所示,在本发明的第二个实施例中,分别在多晶硅层的P沟道区域、N沟道区域和TFT区域上涂覆光刻胶,P沟道区域的光刻胶厚度是N沟道区域以及TFT区域光刻胶厚度的三倍,TFT区域等其他部分没有光刻胶。经过多晶硅层干刻后形成多晶硅图案和沟道,然后通过光刻胶灰化处理,使得N沟道区域和TFT区域较薄的光刻胶被去除,如图6b所示,仅留下P沟道区域的光刻胶。
优选的,在多晶硅层的P沟道区域、N沟道区域和TFT区域上涂覆光刻胶的厚度差别是采用GTM(Gray Tone Mask,灰阶掩膜)或者HTM(Half Tone Mask,半色调掩膜)的方式实现。
接着,屏蔽P沟道区域,对N沟道区域和TFT区域实行离子注入,优选采用硼离子注入。
接着,N沟道区域、P型P沟道区域以及P型TFT区域实行离子注入以形成N型源/漏极区域和N型TFT区域。
栅极电极沉积,形成第一金属层,定义出栅极。
屏蔽N型N沟道区域和N型TFT区域,实行离子注入以形成P型源/漏极区域。
在N沟道区域、P沟道区域以及TFT区域的源极、漏极、栅极处分别形成接触孔。
布线层沉积,形成第二金属层,并定义数据线图案。
平坦层沉积,并在TFT区域形成平坦层的接触孔,涂覆ITO膜层,定义像素电极形状。
优选的,平坦层材料优选为由JSR公司出品的PC403或者PC452,布线层可以优选为钼铝叠层金属(Mo-Al-Mo)。
上述为本发明使用8道光罩的新LTPS阵列基板制造方法的主要工序步骤,通过上述新制造方法,使得设备费用降低,同时提高产量,还降低了常规8道光罩所带来的设计上的缺陷及制程的难度。
以上对本发明的具体实施例进行了详细描述,但本发明并不限制于以上描述的具体实施例,其只是作为范例。对于本领域技术人员而言,任何等同修改和替代也都在本发明的范畴之中。因此,在不脱离本发明的精神和范围下所作出的均等变换和修改,都应涵盖在本发明的范围内。
Claims (7)
1.一种LTPS阵列基板的制造方法,所述LTPS阵列基板包括N沟道区域、P沟道区域和TFT区域,其特征在于,包括:
在基板上依次沉积缓冲层和非晶硅层,通过激光退火使得所述非晶硅层晶化为多晶硅层;
分别在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶,所述P沟道区域的光刻胶厚度是所述N沟道区域以及所述TFT区域光刻胶厚度的两倍以上,其他部分没有光刻胶;
经过多晶硅层干刻后形成多晶硅图案和沟道,然后通过光刻胶灰化处理,使得所述N沟道区域和所述TFT区域较薄的光刻胶被去除,而留下所述P沟道区域的光刻胶;
屏蔽所述P沟道区域,对所述N沟道区域和所述TFT区域实行离子注入;
屏蔽P型所述N沟道区域、P型所述P沟道区域以及P型所述TFT区域,实行离子注入以形成N型源/漏极区域和N型TFT区域;
栅极电极沉积,形成第一金属层,定义出栅极;
屏蔽N型所述N沟道区域和N型所述TFT区域,实行离子注入以形成P型源/漏极区域;
在所述N沟道区域、所述P沟道区域以及所述TFT区域的源极、漏极、栅极处分别形成接触孔;
布线层沉积,形成第二金属层,并定义数据线图案;
平坦层沉积,并在所述TFT区域形成所述平坦层的接触孔;
涂覆ITO膜层,定义像素电极形状。
2.如权利要求1所述LTPS阵列基板的制造方法,其特征在于,分别在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶,所述P沟道区域的光刻胶厚度是所述N沟道区域以及所述TFT区域光刻胶厚度的两倍或三倍,其他部分没有光刻胶。
3.如权利要求2所述LTPS阵列基板的制造方法,其特征在于,在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶采用GTM的方式实现。
4.如权利要求2所述LTPS阵列基板的制造方法,其特征在于,在所述多晶硅层的所述P沟道区域、所述N沟道区域和所述TFT区域上涂覆光刻胶采用HTM的方式实现。
5.如权利要求1所述LTPS阵列基板的制造方法,其特征在于,所述缓冲层包括SiNx层和SiOx层,所述SiOx层位于所述SiNx层上方。
6.如权利要求1所述LTPS阵列基板的制造方法,其特征在于,所述平坦层材料为PC403或PC452。
7.如权利要求1所述LTPS阵列基板的制造方法,其特征在于,所述布线层为钼铝叠层金属。
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CN105304569B (zh) * | 2015-09-24 | 2018-05-11 | 武汉华星光电技术有限公司 | 一种cmos晶体管及ltps阵列基板的制作方法 |
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