TW201712805A - 多晶矽薄膜電晶體元件及其製作方法 - Google Patents

多晶矽薄膜電晶體元件及其製作方法 Download PDF

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TW201712805A
TW201712805A TW104131229A TW104131229A TW201712805A TW 201712805 A TW201712805 A TW 201712805A TW 104131229 A TW104131229 A TW 104131229A TW 104131229 A TW104131229 A TW 104131229A TW 201712805 A TW201712805 A TW 201712805A
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layer
buffer layer
thin film
film transistor
polycrystalline germanium
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TW104131229A
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TWI578443B (zh
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蕭翔允
陳佳楷
林世亮
許庭毓
王培筠
黃雅琴
江丞偉
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友達光電股份有限公司
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Priority to CN201510872131.3A priority patent/CN105448999B/zh
Priority to US15/264,805 priority patent/US9891501B2/en
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Abstract

一種製作多晶矽薄膜電晶體元件的方法，包括下列步驟。提供基板，並形成具有複數個摻質的緩衝層於基板上。形成非晶矽層於具有摻質的緩衝層上。進行熱製程，將非晶矽層多晶化以轉換成多晶矽層，並同時將緩衝層內之一部分的摻質向外擴散至多晶矽層內以調整起始電壓。圖案化多晶矽層，以形成主動層。形成閘極絕緣層於主動層上。形成閘極於閘極絕緣層上。形成源極摻雜區與汲極摻雜區於主動層內。

Description

多晶矽薄膜電晶體元件及其製作方法
本發明係關於一種多晶矽薄膜電晶體元件及其製作方法，尤指一種具有高電子遷移率(mobility)的多晶矽薄膜電晶體元件及其製作方法。
低溫多晶矽(low temperature polycrystalline silicon, LTPS)薄膜電晶體元件由於具有較高電子遷移率(mobility)的特性，因此理論上具有較非晶矽(amorphous silicon)薄膜電晶體元件更佳的電性表現。然而，由於低溫多晶矽薄膜電晶體元件的製程較為複雜，其相較於非晶矽薄膜電晶體元件而要更多道的微影暨蝕刻(photolithography and etching, PEP)製程，因此不僅製作成本較高，且良率也會下降。
本發明之目的之一在於提供一種多晶矽薄膜電晶體元件及其製作方法，以簡化製程步驟及製作成本並提升電子遷移率與元件特性。
本發明之一實施例提供一種製作多晶矽薄膜電晶體元件的方法，包括下列步驟。提供基板，並形成具有複數個摻質的緩衝層於基板上。形成非晶矽層於具有摻質的緩衝層上。進行熱製程，將非晶矽層多晶化以轉換成多晶矽層，並同時將緩衝層內之一部分的摻質向外擴散至多晶矽層內以調整起始電壓。圖案化多晶矽層，以形成主動層。形成閘極絕緣層於主動層上。形成閘極於閘極絕緣層上。形成源極摻雜區與汲極摻雜區於主動層內。
本發明之另一實施例提供一種多晶矽薄膜電晶體元件，設置於基板上。多晶矽薄膜電晶體元件包括緩衝層、多晶矽層、閘極絕緣層與閘極。緩衝層設置於基板上，且緩衝層內具有複數個摻質。多晶矽層設置於緩衝層上，其中多晶矽層包括通道、源極摻雜區以及汲極摻雜區，且源極摻雜區與汲極摻雜區分別位於通道之兩側。閘極絕緣層設置於多晶矽層上。閘極設置於閘極絕緣層上並對應於多晶矽層之通道。
為使熟悉本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。
請參考第1圖。第1圖繪示了本發明之製作多晶矽薄膜電晶體元件的方法流程圖。如第1圖所示，本發明之製作多晶矽薄膜電晶體元件的方法包括下列步驟。
步驟10：提供基板。
步驟12：形成具有複數個摻質的緩衝層於基板上。
步驟14：形成非晶矽層於具有摻質的緩衝層上。
步驟16：進行熱製程，將非晶矽層多晶化以轉換成多晶矽層，並同時將緩衝層內之一部分的摻質向外擴散至多晶矽層內以調整起始電壓。
步驟18：圖案化多晶矽層以形成主動層。
步驟20：形成閘極絕緣層於主動層上。
步驟22：形成閘極於閘極絕緣層上。
步驟24：形成源極摻雜區與汲極摻雜區於主動層內。
請繼續參考第2圖至第8圖，並一併參考第1圖。第2圖至第8圖繪示了本發明之第一實施例之製作多晶矽薄膜電晶體元件的方法示意圖。如第2圖所示，首先提供基板30。基板30可包括透明基板例如玻璃基板、塑膠基板、石英基板、藍寶石基板或其它適合基板，且基板30可選用硬質基板或可撓式基板。接著，形成具有複數個摻質34的緩衝層32於基板30上。在本實施例中，緩衝層32為單層結構緩衝層，且其材料可包括無機絕緣材料例如氧化矽，但不以此為限。緩衝層32的材料也可包括氮化矽、氮氧化矽或其它適合的無機或有機絕緣材料。在其它實施例中，緩衝層32可為多層堆疊結構緩衝層。緩衝層32可利用沉積製程例如化學氣相沉積(CVD)製程、物理氣相沉積(PVD)或其它適合的沉積製程形成。此外，本實施例之方法可包括於形成緩衝層32的沉積製程中同時通入包含摻質34之氣體，以於緩衝層32內形成摻質34，也就是說，緩衝層32與摻質34可於同一反應室內一併形成。緩衝層32內之摻質34可包括P型摻質例如硼離子或N型摻質例如磷離子，在此狀況下，通入反應室的氣體可為包含硼離子或磷離子的氣體，但不以此為限。此外，在一變化實施例中，緩衝層32與摻質34釓可分別加以製作，亦即可先進行沉積製程以於基板30上沉積緩衝層32，接著再進行離子佈植製程以於緩衝層32內形成摻質34。在本實施例中，緩衝層32內的摻質34的摻雜濃度例如可介於 8x1014 至4x1015 atom/cm3 之間，但不以此為限。摻質34的摻雜濃度可視多晶矽薄膜電晶體元件的起始電壓規格與熱製程的不同而加以變更。此外，摻質34在緩衝層32內可為均勻分布、或大部分分布在靠近緩衝層32的表面的區域，或為梯度分布。
如第3圖所示，接著形成非晶矽層36於具有摻質34的緩衝層32上。非晶矽層36可利用沉積製程例如化學氣相沉積(CVD)製程、電漿增強化學氣相沉積(PECVD)製程或其它適合的沉積製程形成。
如第4圖所示，隨後進行熱製程，將非晶矽層36多晶化以轉換成多晶矽層38，並同時將緩衝層32內之一部分的摻質34向外擴散至多晶矽層38內以調整起始電壓。本實施例的方法可為製作低溫多晶矽薄膜電晶體元件的方法，其中熱製程可包括準分子雷射退火(Excimer Laser Annealing, ELA)製程，其利用雷射光束37以掃描方式依序對不同位置的非晶矽層36進行多晶化，以使非晶矽重新排列成多晶矽。在一變化實施例中，熱製程也可包括固相結晶化(Solid Phase Crystallization, SPC)製程或其它適合的熱製程。在準分子雷射退火製程中，緩衝層32也會受到雷射光束37的照射而受熱而使得一部分的摻質34擴散至多晶矽層38內而使得多晶矽層38形成摻雜，達到調整起始電壓的作用。值得說明的是，當緩衝層32內的摻質34擴散至多晶矽層38時，緩衝層32可能具有粗糙表面，且緩衝層32會形成多孔(porous)緩衝層，其中，此時，熱製程後的緩衝層32的摻質34的摻雜濃度會小於熱製程前的緩衝層32的摻質34的摻雜濃度。在此狀況下，在經過雷射光束37的照射後，熱能會蓄積在緩衝層32的粗糙表面與孔洞內而使得多晶矽層38內的多晶矽的晶界尺寸(grain boundary size)加大(即多晶矽的晶粒變大)而可優化晶種成長。也就是說，本實施例的熱製程可以同時對非晶矽層36進行多晶化，以及一併對多晶矽層38進行摻雜以調整起始電壓。此外，相較於分別利用離子佈植製程直接對多晶矽層38進行摻雜的方式以及利用熱製程對非晶矽層36進行多晶化的方式，本實施例利用緩衝層32內的摻質34對多晶矽層38進行摻雜的作法不僅只需要一道熱製程即可達到調整起起電壓及多晶化的作用，且緩衝層32內的孔洞更可發揮蓄積熱能的作用使得多晶矽層38內的多晶矽的晶界尺寸加大而可優化晶種成長，而可有助於提升電子遷移率。
另外，為了進一步改善準分子雷射退火製程的結晶化能力，本實施例之緩衝層32的厚度與折射率以及準分子雷射的波長之間可以符合下式(1)的關係。 2nd=mλ                                                 (1)
其中n是緩衝層32的折射率，d是緩衝層32的厚度，λ是準分子雷射的波長，m為正整數。
在符合上述式(1)的條件下，準分子雷射可以在緩衝層32內產生共振而放大能量，藉此可以改善多晶矽的結晶狀況並加大晶界尺寸，進而提升電子遷移率與元件特性。
值得說明的是於進行熱製程之前，本實施例的方法可選擇性地先對非晶矽層36進行去氫(dehydrogenation)製程，且在去氫製程時可同時將緩衝層32內之一部分的摻質34擴散至非晶矽層36內。
如第5圖所示，接著對多晶矽層38進行圖案化，移除一部分的多晶矽層38以形成主動層381。上述圖案化製程可為微影暨蝕刻製程，但不以此為限。
如第6圖所示，於主動層381中形成通道38C、源極摻雜區38S與汲極摻雜區38D，其中源極摻雜區38S與汲極摻雜區38D分別位於通道38C之兩側。此外，可選擇性地於通道38C與源極摻雜區38S之間以及通道38C與汲極摻雜區38D之間分別形成輕摻雜區38L，其中源極摻雜區38S與汲極摻雜區38D的摻雜濃度大於輕摻雜區38L的摻雜濃度，且通道38C的摻雜濃度小於源極摻雜區38S、汲極摻雜區38D與輕摻雜區38L。
在本實施例中，源極摻雜區38S、汲極摻雜區38D與輕摻雜區38L可利用離子佈植製程並搭配遮罩(圖未示)例如光阻圖案形成。舉例而言，可先於主動層381的表面形成光阻圖案，其中光阻圖案覆蓋通道38C及預定形成輕摻雜區38L的區域並暴露出預定形成源極摻雜區38S與汲極摻雜區38D的區域。接著，利用光阻圖案作為遮罩對暴露出的主動層381進行離子佈植製程以形成源極摻雜區38S與汲極摻雜區38D。隨後，移除一部分的光阻圖案例如利用灰化製程以進一步暴露出預定形成輕摻雜區38L的區域，並再利用縮減後光阻圖案作為遮罩再進行離子佈植製程以形成輕摻雜區38L。最後，移除剩餘的光阻圖案。本發明之源極摻雜區38S與汲極摻雜區38D以及輕摻雜區38L的製作方式不以上述實施例為限。在變化實施例中，源極摻雜區38S與汲極摻雜區38D可利用一離子佈植製程並搭配一遮罩形成，而輕摻雜區38L可利用另一離子佈植製程並搭配另一遮罩。或者，源極摻雜區38S與汲極摻雜區38D以及輕摻雜區38L可利用後續形成的閘極作為遮罩加以製作。之後，本實施例之方法可包括對多晶矽層38進行氫化製程，以修補多晶矽層38的缺陷。此外，本實施例之方法也可包括可對源極摻雜區38S與汲極摻雜區38D進行活化製程，例如熱退火製程或雷射退火製程，以降低源極摻雜區38S與汲極摻雜區38D的阻值。
如第7圖所示，接著形成閘極絕緣層40於主動層381上。閘極絕緣層40的材料可為無機材料例如氧化矽、氮化矽或氮氧化矽，但不以此為限。隨後，形成閘極42G於閘極絕緣層40上，其中閘極42G與通道38C在垂直投影方向上重疊。在本實施例中，閘極42G的材料可包括金屬或合金，例如金、銀、銅、鋁、鈦、鉬等金屬或其合金，或其它適合之導電材料。
如第8圖所示，接著形成層間介電層44於閘極42G上，並對層間介電層44與閘極絕緣層40進行圖案化以暴露出源極摻雜區38S與汲極摻雜區38D。上述圖案化製程可為微影暨蝕刻製程，但不以此為限。在本實施例中，層間介電層44可為多重堆疊結構層間介電層，其可包括例如第一層間介電層441位於閘極42G上，以及第二層間介電層442堆疊於第一層間介電層441上，其中第一層間介電層441可為無機介電層，例如氧化矽層、氮化矽層或氮氧化矽層，但不以此為限；第二層間介電層442可為有機介電層，但不以此為限。在變化實施例中，層間介電層44亦可為單層結構層。隨後，形成源極電極46S與汲極電極46D於層間介電層44上，其中源極電極46S與源極摻雜區38S電性連接，且汲極電極46D與汲極摻雜區38D電性連接。源極電極46S與汲極電極46D的材料可包括金屬或合金，例如金、銀、銅、鋁、鈦、鉬等金屬或其合金，或其它適合之導電材料。至此，可製作出本實施例之多晶矽薄膜電晶體元件1。本實施例中之層間介電層44可為多重堆疊結構設計，可增加雷射退火製程中共振的效果，可使晶界尺寸加大而可優化晶種成長，進而提升電子遷移率與元件特性。
本實施例之多晶矽薄膜電晶體元件1可應用於顯示面板例如液晶顯示面板、電激發光顯示板或其它各種類型的顯示面板、觸控面板或任何電子裝置或光電裝置上，作為開關元件或驅動元件之用。請接續第8圖參考第9圖。第9圖繪示本發明之一實施例之製作顯示面板的示意圖。如第9圖所示，接著依序形成一保護層48與一畫素電極PE於多晶矽薄膜電晶體元件1上，其中保護層48可部分暴露出汲極電極46D，而畫素電極PE與汲極電極46D電性連接。接著，提供另一基板50，並於基板50上形成共通電極CE。接著，將基板30與基板50結合，並於基板30與基板50之間形成顯示介質層52，以形成本實施例的顯示面板100。本實施例顯示面板100係以液晶顯示面板為例，因此顯示介質層52可包括液晶層，但不以此為限。在變化實施例中，顯示面板也可是電激發光顯示面板例如有機發光二極體顯示面板，而顯示介質層52可為電激發光層或其它適合的非自發光顯示介質層或自發光顯示介質層。本實施例之顯示面板1係垂直電場驅動型液晶顯示面板為例，例如向列扭轉型(TN)液晶顯示面板或垂直配向型(VA)液晶顯示面板，但不以此為限。舉例而言，本發明之顯示面板也可為水平電場驅動型液晶顯示面板例如平面切換型(IPS)液晶顯示面板、邊緣電場切換(FFS)液晶顯示面板或其它型式的顯示面板。在一變化實施例中，共通電極CE也可形成於基板30上並與畫素電極PE位於同一平面上，作為平面電場切換型(IPS)液晶顯示面板的應用。在另一變化實施例中，共通電極CE也可形成於基板30上但與畫素電極PE位於不同平面上，作為邊緣電場切換型(FFS)液晶顯示面板的應用。
由上述可知，本發明之製作多晶矽薄膜電晶體元件的方法利用單一道熱製程即可將非晶矽層轉換成多晶矽層，並同時將緩衝層內的摻質擴散至多晶矽層內而調整起始電壓，因此可簡化製程步驟及製作成本。此外，當緩衝層內的摻質擴散至多晶矽層時，緩衝層會形成多孔緩衝層，因此在熱製程中熱能可蓄積在孔洞內而使得多晶矽層內的多晶矽的晶界尺寸加大而可優化晶種成長，進而提升電子遷移率與元件特性。
本發明之多晶矽薄膜電晶體元件及其製作方法並不以上述實施例為限。下文將依序介紹本發明之其它較佳實施例之多晶矽薄膜電晶體元件及其製作方法，且為了便於比較各實施例之相異處並簡化說明，在下文之各實施例中使用相同的符號標注相同的元件，且主要針對各實施例之相異處進行說明，而不再對重覆部分進行贅述。
請繼續參考第10圖與第11圖，並一併參考第1圖。第10圖與第11圖繪示了本發明之第二實施例之製作多晶矽薄膜電晶體元件的方法示意圖。如第10圖所示，在本實施例中，緩衝層32為多層堆疊結構緩衝層，其包括至少一底緩衝層32B位於基板30上，以及一頂緩衝層32T位於底緩衝層32B上。舉例而言，本實施例之緩衝層32的底緩衝層32B可包括第一底緩衝層32B1、第二底緩衝層32B2以及第三底緩衝層32B3，依序形成於基板30上，而頂緩衝層32T可形成於第三底緩衝層32B3上。在本實施例中，第一底緩衝層32B1、第二底緩衝層32B2、第三底緩衝層32B3與頂緩衝層32T可為依序堆疊的不同材料膜層，例如第一底緩衝層32B1與第三底緩衝層32B3的材料可為氮化矽，而第二底緩衝層32B2與頂緩衝層32T的材料可為氧化矽，藉此可增加與基板30的附著力並減少應力。另外，第一底緩衝層32B1、第二底緩衝層32B2、第三底緩衝層32B3與頂緩衝層32T的厚度可視附著力、應力與其它考量加以調整。在一實施樣態中，第二底緩衝層32B2與頂緩衝層32T的厚度可大於第一底緩衝層32B1與第三底緩衝層32B3的厚度，例如第二底緩衝層32B2或頂緩衝層32T的厚度可為第一底緩衝層32B1或第三底緩衝層32B3的厚度的數倍，但不以此為限。
在本實施例中，摻質34可僅形成於多層堆疊結構緩衝層之頂緩衝層32T內，其中於頂緩衝層32T內形成摻質34的方式可如前述實施例所述，例如形成頂緩衝層32T的沉積製程中同時通入包含摻質34之氣體，以於頂緩衝層32T內形成摻質34，而底緩衝層32B內不形成摻質34；或是先形成頂緩衝層32T，接著再進行離子佈植製程以於頂緩衝層32T內形成摻質34，而底緩衝層32B內不形成摻質34。在一變化實施例中，摻質34除了形成於頂緩衝層32T內，也可形成於底緩衝層32B內。
如第11圖所示，接著進行如第一實施例之第3圖至第8圖之製程，即可製作出本實施例之多晶矽薄膜電晶體元件2。
本實施例之多晶矽薄膜電晶體元件2可應用於顯示面板例如液晶顯示面板、電激發光顯示板或其它各種類型的顯示面板、觸控面板或任何電子裝置或光電裝置上，作為開關元件或驅動元件之用，如上述實施例所示，在此不再贅述。
請參考第12圖至第14圖。第12圖繪示對照實施例之多晶矽薄膜電晶體元件的汲極電流-閘極電壓關係圖及電子遷移率-閘極電壓關係圖，第13圖繪示本發明之第一樣本之多晶矽薄膜電晶體元件的汲極電流-閘極電壓關係圖及電子遷移率-閘極電壓關係圖，且第14圖繪示本發明之第二樣本之多晶矽薄膜電晶體元件的汲極電流-閘極電壓關係圖及電子遷移率-閘極電壓關係圖。在對照實施例(第12圖)的方法中，多晶矽薄膜電晶體元件係利用離子佈植製程直接對多晶矽層進行起始電壓的調整，而緩衝層內沒有摻質，並分別在汲極電壓Vd為0.1V, 5.1V, 10.1V的條件下進行測試；本發明(第13與14圖)的方法係先對緩衝層進行離子佈植製程，再藉由熱製程同時進行多晶化並一併將摻質擴散至多晶矽薄膜電晶體元件的多晶矽層內，並分別在汲極電壓Vd為0.1V, 5.1V, 10.1V的條件下進行測試，其中第13圖的第一樣本的離子佈植製程的能量為60kev，摻質為硼離子，且摻雜濃度為5*1013 atoms/cm3 ；第14圖的第二樣本的離子佈植製程的能量為60kev，摻質為磷離子，且摻雜濃度為2*1014 atoms/cm3 。如第12圖所示，對照實施例之多晶矽薄膜電晶體元件的起始電壓(Vth)約為-2.71V。相較之下，如第13圖所示，第一樣本之多晶矽薄膜電晶體元件的起始電壓(Vth)約為-1.17V；如第14圖所示，第二樣本之多晶矽薄膜電晶體元件的起始電壓(Vth)約為-2.02V。由上述實驗數據可知，藉由在緩衝層內先形成摻質再藉由熱製程同時進行多晶化並一併將摻質擴散至多晶矽薄膜電晶體元件的多晶矽層內的作法確實可以有效將起始電壓調整至預定的區間內。
另外，本發明針對多晶矽層的晶界尺寸所作的實驗亦顯示了藉由在緩衝層內先形成摻質再藉由熱製程同時進行多晶化並一併將摻質擴散至多晶矽薄膜電晶體元件的多晶矽層內的作法可以有效增大晶界尺寸(即增大晶粒尺寸)。請參考表1，表1列示了對照實施例與本發明之一實施例的晶界尺寸，其中對照實施例係在緩衝層內沒有摻質的條件下所實際量測出的晶界尺寸，而本實施例係在緩衝層內摻雜有氬(Ar)離子的條件下實際量測出的晶界尺寸。   表1
由表1的結果可知，在緩衝層內沒有摻質的條件下，對照實施例的晶界尺寸約為0.3098微米，而在緩衝層中形成摻質的條件下，本實施例的晶界尺寸約為0.3432微米，其晶界尺寸增加了約10.81%。
綜上所述，本發明之製作多晶矽薄膜電晶體元件的方法利用單一道熱製程即可將非晶矽層轉換成多晶矽層，並一併將緩衝層內的摻質擴散至多晶矽層內而調整起始電壓至預定區間，因此可簡化製程步驟及製作成本。此外，當緩衝層內的摻質擴散至多晶矽層時，緩衝層會形成多孔緩衝層，因此在熱製程中熱能可蓄積在孔洞內而使得多晶矽層內的多晶矽的晶界尺寸加大而可優化晶種成長，進而提升電子遷移率與元件特性。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1,2‧‧‧多晶矽薄膜電晶體元件
30‧‧‧基板
32‧‧‧緩衝層
32B‧‧‧底緩衝層
32B1‧‧‧第一底緩衝層
32B2‧‧‧第二底緩衝層
32B3‧‧‧第三底緩衝層
32T‧‧‧頂緩衝層
34‧‧‧摻質
37‧‧‧雷射光束
36‧‧‧非晶矽層
38‧‧‧多晶矽層
381‧‧‧主動層
38C‧‧‧通道
38S‧‧‧源極摻雜區
38D‧‧‧汲極摻雜區
38L‧‧‧輕摻雜區
40‧‧‧閘極絕緣層
42G‧‧‧閘極
44‧‧‧層間介電層
441‧‧‧第一層間介電層
442‧‧‧第二層間介電層
46S‧‧‧源極電極
46D‧‧‧汲極電極
48‧‧‧保護層
PE‧‧‧畫素電極
50‧‧‧基板
CE‧‧‧共通電極
52‧‧‧顯示介質層
100‧‧‧顯示面板
第1圖繪示了本發明之製作多晶矽薄膜電晶體元件的方法流程圖。 第2圖至第8圖繪示了本發明之第一實施例之製作多晶矽薄膜電晶體元件的方法示意圖。 第9圖繪示本發明之一實施例之製作顯示面板的示意圖。 第10圖與第11圖繪示了本發明之第二實施例之製作多晶矽薄膜電晶體元件的方法示意圖。 第12圖繪示對照實施例之多晶矽薄膜電晶體元件的汲極電流-閘極電壓關係圖及電子遷移率-閘極電壓關係圖。 第13圖繪示本發明之第一樣本之多晶矽薄膜電晶體元件的汲極電流-閘極電壓關係圖及電子遷移率-閘極電壓關係圖。 第14圖繪示本發明之第二樣本之多晶矽薄膜電晶體元件的汲極電流-閘極電壓關係圖及電子遷移率-閘極電壓關係圖。
2‧‧‧多晶矽薄膜電晶體元件
30‧‧‧基板
32‧‧‧緩衝層
32B‧‧‧底緩衝層
32B1‧‧‧第一底緩衝層
32B2‧‧‧第二底緩衝層
32B3‧‧‧第三底緩衝層
32T‧‧‧頂緩衝層
38‧‧‧多晶矽層
381‧‧‧主動層
38C‧‧‧通道
38S‧‧‧源極摻雜區
38D‧‧‧汲極摻雜區
38L‧‧‧輕摻雜區
40‧‧‧閘極絕緣層
42G‧‧‧閘極
44‧‧‧層間介電層
441‧‧‧第一層間介電層
442‧‧‧第二層間介電層
46S‧‧‧源極電極
46D‧‧‧汲極電極

Claims (19)

  1. 一種製作多晶矽薄膜電晶體元件的方法，包括： 提供一基板； 形成一具有複數個摻質(dopant)的緩衝層於該基板上； 形成一非晶矽層於具有該等摻質的該緩衝層上； 進行一熱製程，將該非晶矽層多晶化以轉換成一多晶矽層，並同時將該緩衝層內之一部分的該等摻質向外擴散至該多晶矽層內以調整起始電壓(threshold voltage)； 圖案化該多晶矽層，以形成一主動層； 形成一閘極絕緣層於該主動層上； 形成一閘極於該閘極絕緣層上；以及 形成一源極摻雜區與一汲極摻雜區於該主動層內。
  2. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，其中該緩衝層內之該等摻質包括P型摻質或N型摻質。
  3. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，其中該緩衝層係為一單層結構緩衝層。
  4. 如請求項3所述之製作多晶矽薄膜電晶體元件的方法，其中於進行該熱製程之前，該等摻質係位於該單層結構緩衝層內。
  5. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，其中該緩衝層係為一多層堆疊結構緩衝層，其包括至少一底緩衝層位於該基板上以及一頂緩衝層位於該至少一底緩衝層上。
  6. 如請求項5所述之製作多晶矽薄膜電晶體元件的方法，其中於進行該熱製程之前，該等摻質係位於該多層堆疊結構緩衝層之該頂緩衝層內。
  7. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，其中於該基板上形成具有該等摻質的緩衝層之步驟包括： 進行一沉積製程以於該基板上沉積該緩衝層，並於該沉積製程中同時通入包含該等摻質之氣體，以於該緩衝層內形成該等摻質。
  8. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，其中於該基板上形成具有該等摻質的緩衝層之步驟包括： 進行一沉積製程以於該基板上沉積該緩衝層；以及 進行一離子佈植製程以於該緩衝層內形成該等摻質。
  9. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，其中該熱製程包括一準分子雷射退火(Excimer Laser Annealing, ELA)製程。
  10. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，其中該熱製程包括固相結晶化(Solid Phase Crystallization, SPC)製程。
  11. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，另包括於進行該熱製程之前，先對該非晶矽層進行一去氫(dehydrogenation)製程，並同時進一步將該緩衝層內之一部分的該等摻質擴散至該非晶矽層內。
  12. 如請求項1所述之製作多晶矽薄膜電晶體元件的方法，另包括： 形成一層間介電層於該閘極上；以及 形成一源極電極與一汲極電極於該層間介電層上，其中該源極電極與該源極摻雜區電性連接，且該汲極電極與該汲極摻雜區電性連接。
  13. 一種多晶矽薄膜電晶體元件，設置於一基板上，該多晶矽薄膜電晶體元件包括： 一緩衝層，設置於該基板上，其中該緩衝層內具有複數個摻質(dopant)； 一多晶矽層，設置於該緩衝層上，其中該多晶矽層包括一通道、一源極摻雜區以及一汲極摻雜區，且該源極摻雜區與該汲極摻雜區分別位於該通道之兩側； 一閘極絕緣層，設置於該多晶矽層上；以及 一閘極，設置於該閘極絕緣層上並對應於該多晶矽層之該通道。
  14. 如請求項13所述之多晶矽薄膜電晶體元件，其中該緩衝層內之該等摻質包括P型摻質或N型摻質。
  15. 如請求項13所述之多晶矽薄膜電晶體元件，其中該緩衝層係為一單層結構緩衝層，且該等摻質係位於該單層結構緩衝層內。
  16. 如請求項15所述之多晶矽薄膜電晶體元件，其中該單層結構緩衝層係為一多孔(porous)緩衝層。
  17. 如請求項13所述之多晶矽薄膜電晶體元件，其中該緩衝層係為一多層堆疊結構緩衝層，其包括至少一底緩衝層位於該基板上以及一頂緩衝層位於該至少一底緩衝層上，且該等摻質係位於該多層堆疊結構緩衝層之該頂緩衝層內。
  18. 如請求項17所述之多晶矽薄膜電晶體元件，其中該頂緩衝層係為一多孔緩衝層。
  19. 如請求項13所述之多晶矽薄膜電晶體元件，另包括： 一層間介電層位於該閘極上；以及 一源極電極與一汲極電極位於該層間介電層上，其中該源極電極與該源極摻雜區電性連接，且該汲極電極與該汲極摻雜區電性連接。
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