CN105448901A - 电子部件 - Google Patents

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Publication number
CN105448901A
CN105448901A CN201510609503.3A CN201510609503A CN105448901A CN 105448901 A CN105448901 A CN 105448901A CN 201510609503 A CN201510609503 A CN 201510609503A CN 105448901 A CN105448901 A CN 105448901A
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China
Prior art keywords
npn
low
electrode
transistor
pressure depletion
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CN201510609503.3A
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O·黑伯伦
M-A·库奇埃克
R·奥特雷姆巴
K·希斯
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Publication of CN105448901A publication Critical patent/CN105448901A/zh
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Abstract

在一个实施例中，电子部件包括：高压耗尽型晶体管，包括与低压增强型晶体管的电流路径串联耦合的电流路径；二极管，包括阳极和阴极；以及裸片焊盘。高压耗尽型晶体管的后表面安装在裸片焊盘上并电耦合至裸片焊盘。低压增强型晶体管的第一电流电极安装在裸片焊盘上并电耦合至裸片焊盘。二极管的阳极耦合至高压耗尽型晶体管的控制电极，并且二极管的阴极安装在裸片焊盘上。

Description

电子部件
技术领域
本发明涉及半导体领域，更具体地，涉及电子部件。
背景技术
迄今为止，晶体管被用于通常利用硅(Si)半导体材料制造的功率电子应用中。用于功率应用的普通晶体管器件包括SiCoolMOS、Si功率MOSFET和Si绝缘栅极双极型晶体管(IGBT)。在一些应用中还使用化合物半导体，例如III-V族化合物半导体(诸如GaAs)。近来，已经考虑碳化硅(SiC)功率器件。诸如基于氮化镓(GaN)的器件的基于III族N的半导体器件现在正在成为承载大电流、支持高压以及提供非常低的导通阻抗和快速切换时间的强有力的候选。
发明内容
在一个实施例中，一种电子部件包括：高压耗尽型晶体管，包括与低压增强型晶体管的电流路径串联耦合的电流路径；二极管，包括阳极和阴极；以及裸片焊盘。高压耗尽型晶体管的后表面安装在裸片焊盘上并电耦合至裸片焊盘。低压增强型晶体管的第一电流电极安装在裸片焊盘上并电耦合至裸片焊盘。二极管的阳极耦合至高压耗尽型晶体管的控制电极，并且二极管的阴极安装在裸片焊盘上。
本领域技术人员将在阅读以下详细描述以及附图的基础上理解附加特征和优势。
附图说明
附图中的元件没有必要彼此按比例绘制。类似的参考标号对应于类似的部件。各个所示实施例的特征可以进行组合，除非它们相互排斥。在附图中示出实施例并在以下的说明书中进行描述。
图1示出了根据第一实施例的电子部件。
图2示出了示出共源共栅电路的示意图。
图3示出了示出电路布置的示意图。
图4示出了根据第二实施例的电子部件。
图5示出了根据第三实施例的电子部件。
图6示出了根据第四实施例的高压耗尽型晶体管。
图7示出了根据第五实施例的高压耗尽型晶体管。
具体实施方式
在以下详细描述中，参照作为说明书一部分且通过可实践本发明的示例性具体实施例的附图。关于这点，诸如“顶部”、“底部”、“前”、“后”、“头部”、“尾部”等的方向术语用于表示所描述附图的定向。由于可以以多种不同的定向来定位实施例的部件，所以方向术语是为了说明的目的而不用于限制。应该理解，在不背离本发明的范围的情况下可以利用其他实施例并进行结构或逻辑改变，并且本发明的范围通过所附权利要求来限定。
以下将解释多个实施例。在这这种情况下，在附图中通过相同或相似的参考符号来表示相同的结构部件。在本说明的上下文中，“横向”应该理解为表示通常与半导体材料或半导体载体的横向平行的方向或范围。因此，横向通常平行于这些表面或侧。相反，术语“垂直”或“垂直方向”应理解为表示通常垂直于这些表面或侧，并由此垂直于横向的方向。因此，垂直方向在半导体材料或半导体载体的厚度方向上延伸。
如说明书所使用的，术语“耦合”和/或“电耦合”不表示元件必须直接耦合到一起，而是可以在“耦合”或“电耦合”的元件之间设置夹置元件。
如说明书所使用的，当诸如层、区域或衬底的元件表示为位于另一元件“上”或在另一元件“上”延伸，则该元件可以直接位于另一元件上或在其上延伸，或者也可以存在夹置元件。相反，当元件被表示为“直接位于另一元件上”或“在另一元件上”延伸，则不存在夹置元件。如说明书所使用的，当元件被表示为“连接”或“耦合”至另一元件，则该元件可以直接连接或耦合至另一元件或者可以存在夹置元件。相反，当元件被表示为“直接连接”或“直接耦合”至另一元件，则不存在夹置元件。
耗尽型器件(诸如高压耗尽型晶体管)具有负阈值电压，这表示其可以以零栅极电压来传导电流。这些器件通常是导通的。增强型器件(诸如低压增强型晶体管)具有正阈值电压，则表示其不能以零栅极电压传导电流且通常是截止的。
如本文所使用的，“高压器件”(诸如高压耗尽型晶体管)是优化用于高压切换应用的电子器件。即，当晶体管截止时，其能够阻挡高压(诸如大约300V以上、大约600V以上、或者大约1200V以上)，而当晶体管导通时，其针对使用其的应用具有充分低的导通阻抗(RON)，即当充分大的电流经过器件时其经历充分低的传导损失。高压器件可以至少能够阻挡等于高压电源或使用其的电路中的最大电压的电压。高压器件能够阻挡300V、600V、1200V或其他应用所要求的适当阻挡电压。
如本文所使用的，“低压器件”(诸如低压增强型晶体管)是能够阻挡低压的电子器件，诸如0V和Vlow之间的电压，但是不能够阻挡高于Vlow的电压。Vlow可以为大约10V、大约20V、大约30V、大约40V或者大约5V和50V之间，诸如在大约10V和30V之间。
如本文所使用的，术语“III族氮化物”是指包括氮(N)和至少一种III族元素的化合物半导体，包括铝(Al)、镓(Ga)、铟(In)和硼(B)并且包括但不限于它们的任何合金，诸如氮化镓(GaN)、氮化铝镓(AlxGa(1-x)N)、氮化铟镓(InyGa(1-y)N)和氮化铝铟镓(AlxInyGa(1-x-y)N)。氮化铝镓是指通过分子式AlxGa(1-x)N描述的合金，其中x>1。
图1示出了根据第一实施例的电子部件10。电子部件10包括高压耗尽型晶体管11，其包括与低压增强型晶体管14的电流路径13串联耦合的电流路径12。电子部件10还包括二极管15和裸片焊盘18。二极管15包括阳极16和阴极17。高压耗尽型晶体管11的后表面19安装在裸片焊盘18上并与其电耦合。低压增强型晶体管14的第一电流电极20安装在裸片焊盘18上并与其电耦合。二极管15的阳极16耦合至高压耗尽型晶体管11的控制电极21。二极管15的阴极17安装在裸片焊盘18上。
裸片焊盘18可以耦合至地电位并且为二极管15的阴极17、为高压耗尽型晶体管11的后表面19以及为低压增强型晶体管14的第一电流电极20提供公共地。二极管15耦合在高压耗尽型晶体管11的控制电极21与裸片焊盘18提供的公共地之间，并且可用于提供用于高压增强型晶体管14的保护功能。在单个电子部件内为高压耗尽型晶体管11提供保护二极管15。
在高压耗尽型晶体管的控制端失去其限定电位的情况下，例如在栅极驱动器故障时或者如果失去栅极驱动器的供应电压，二极管15可用作保护二极管。在这些情况下，高压耗尽型晶体管不能阻挡并且总线电压会到达高压增强型晶体管，并且甚至会损伤或损害低压增强型晶体管。
这些器件在提供公共地的裸片焊盘上的布置可用于减小两个晶体管器件之间的导电性。可以通过这种布置减小高压耗尽型晶体管22的第一电流电极(例如源电极)和低压增强型晶体管14的第二电流电极(例如漏电极)之间的导电性，例如小于0.5nH。
高压耗尽型晶体管11可以操作地以共源共栅布置连接至低压增强型晶体管14。在操作中，高压耗尽型晶体管11通常是导通的。在期望高压耗尽型晶体管11通常截止的实施例中，这可以通过操作性地将高压耗尽型晶体管11以共源共栅布置连接至低压增强型晶体管14来实现。
高压耗尽型晶体管11还可以被直接驱动。在这些实施例中，控制电极可以通过除了用于驱动低压增强型晶体管14的控制电极的第一栅极驱动电路之外设置的第二栅极驱动电路来驱动。
在一些实施例中，二极管15至少部分地集成到高压耗尽型晶体管11中。在一些实施例中，高压耗尽型晶体管11、低压增强型晶体管14和二极管15均包括分立部件。
在一个实施例中，高压耗尽型晶体管的控制电极21还耦合至电子部件10的接触焊盘。该实施例可以用于高压耗尽型晶体管11被直接驱动的实施例中。
在一些实施例中，高压耗尽型晶体管11的控制栅极21还耦合至低压增强型晶体管的第一电流电极。低压增强型晶体管34的低压电流电极可以是耦合至地的源电极。该布置可用于操作性地以共源共栅布置将高压耗尽型晶体管11连接至低压增强型晶体管14。
高压耗尽型晶体管11和低压增强型晶体管14可安装为彼此相邻以形成混合器件。
高压耗尽型晶体管11可以包括第一侧，其包括第一电流电极、第二电流电极和控制电极。低压增强型晶体管14可以包括：第一侧，其包括第一电流电极和控制电极；以及第二侧，包括第二电流电极，第二侧与第一侧相对。在这些实施例中，高压耗尽型晶体管11是横向器件，因为晶体管的漂移路径是横向的，而低压增强型晶体管14是垂直器件，因为晶体管的漂移路径是垂直的。
在一些实施例中，低压增强型晶体管是n沟道器件。低压增强型晶体管14的第二电流电极可以耦合至高压耗尽型晶体管的第一电流电极。例如，低压增强型晶体管14的漏电极可以耦合至高压耗尽型晶体管11的源电极。低压增强型晶体管11的第一电流电极可以安装在裸片焊盘上。在这些实施例中，第一电流电极可以是源电极，并且低压增强型晶体管可以描述为具有“源极-下”布置。
在低压增强型晶体管具有“源极-下”布置的实施例中，低压增强型晶体管的控制电极可以安装在布配置为与裸片焊盘相邻且与裸片焊盘隔开的引线上。低压增强型晶体管在裸片焊盘和引线之间延伸并桥接裸片焊盘和引线之间的空间。
在一些实施例中，低压增强型晶体管14包括p沟道器件。在这些实施例中，高压耗尽型晶体管可以包括第一侧，其包括第一电流电极、第二电流电极和控制电极。低压增强型晶体管14可以包括第一侧(包括第二电流电极)和第二侧(包括第一电流电极和控制电极)。低压增强型晶体管的第二电流电极可以安装在裸片焊盘上。在这些实施例中，第二电流电极可以是耦合至低电位的漏电极。低压增强型晶体管的第一电流电极可以耦合至高压耗尽型晶体管的第一电流电极。在这些实施例中，第一电流电极可以是源电极并且可以耦合至中间介质。低压增强型晶体管的控制电极可以耦合至被布置为与裸片焊盘相邻且与裸片焊盘隔开的电子部件的引线。
在一些实施例中，二极管整体集成在高压耗尽型晶体管中。高压耗尽型晶体管可以进一步包括第一导电类型的重掺杂衬底、布置在衬底上的第一导电类型的轻掺杂层以及布置在轻掺杂层上的化合物半导体层。衬底可以是n+掺杂硅衬底，并且轻掺杂层可以是沉积的n-掺杂硅层。
化合物半导体层可以提供高压耗尽型晶体管的有源区域。化合物半导体层可以提供基于族III-氮化物的晶体管，诸如基于氮化镓的高电子迁移率晶体管(HEMT)。
二极管可以包括布置在第一导电类型的轻掺杂层中的第二导电类型的重掺杂阱，例如p+掺杂阱。这种布置在重掺杂阱和轻掺杂层之间提供了pn结。二极管可进一步包括导电通孔，其布置在重掺杂阱且与重掺杂阱电耦合并且电耦合至高压耗尽型晶体管的控制电极。二极管整体集成在高压耗尽型晶体管中并且耦合在高压耗尽型晶体管的控制电极和地之间，因为导电硅衬底可以安装在耦合至低电位的裸片焊盘上并电耦合至裸片焊盘。
二极管可以包括肖特基接触来代替重掺杂阱，从而肖特基接触形成在与轻掺杂层的界面处。这可以通过导电通孔来提供，其中导电通孔包括一个或多个金属层，其包括被选择以提供与轻掺杂层的肖特基接触的材料。导电通孔还耦合至高压耗尽型晶体管的控制电极。
重掺杂衬底可以是硅晶圆，例如n+掺杂硅晶圆，并且第一导电性的轻掺杂层可以包括外延沉积硅，例如n-掺杂硅。
在一些实施例中，高压耗尽型晶体管是基于族III氮化物的高电子迁移率晶体管(HEMT)。在这些实施例中，化合物半导体层可以包括布置在轻掺杂层上的氮化镓子层以及布置在氮化镓子层上的氮化铝镓子层。氮化镓子层和氮化铝镓子层之间的界面可以支持通过引发和自发极化形成的二维电子气(2DEG)。可以在氮化铝镓层上进一步布置氮化镓盖层和/或介电层和/或钝化层。
低压增强型晶体管可以包括p沟道MOSFET、n沟道MOSFET或绝缘栅极双极型晶体管。低压增强型晶体管可以包括具有垂直漂移路径的功率晶体管器件。功率晶体管器件可以包括MOSFET、绝缘栅极双极型晶体管(IGBT)或双极结晶体管(BJT)。对于MOSFET器件来说，第一电流电极可以是源电极，控制电极可以是栅电极，以及第二电流电极可以是漏电极。对于IGBT器件来说，第一电流电极可以是发射极电极，控制电极可以是栅电极，以及第二电流电极可以是集电极电极。对于BJT器件来说，第一电流电极可以是发射极电极，控制电极可以基极电极，以及第二电流电极可以是集电极电极。
图2示出了包括共源共栅电极31的电路布置30的示意图，其包括通常为导通的具有与第二晶体管33(通常为截止，诸如低压增强型晶体管)的电流路径串联的电流路径的高压耗尽型晶体管32。电流路径在两个电流电极之间延伸，例如在高压耗尽型晶体管的源极和漏极之间以及低压增强型晶体管的源极和漏极之间延伸。共源共栅电路还包括二极管34，其电耦合在高压耗尽型晶体管32的控制电极37和公共地38之间。在共源共栅布置中，高压耗尽型晶体管的控制电耦合至低压增强型晶体管的第一电流电极。只有低压增强型晶体管的控制电极被控制电路35有效地控制。
图3示出了包括高压耗尽型晶体管41的电路40的示意图，其中高压耗尽型晶体管具有与低压增强型晶体管42的电流路径串联耦合的电流路径。在电路40中，控制器43用于控制高压耗尽型晶体管41的控制电极44和低压增强型晶体管42的控制电极45。两个独立的驱动电路可用于驱动高压耗尽型晶体管41的控制电极44和低压增强型晶体管42的控制电极。这种布置可以描述为直接驱动概念。二极管46被设置为耦合在高压耗尽型晶体管41的控制电极44和公共地48之间。
根据本文描述的实施例，图2和图3所示电路的高压耗尽型晶体管、低压增强型晶体管和二极管被设置在图2中用虚线36以及图3中用虚线47表示的单个电子部件中。
在一些实施例中，高压耗尽型晶体管、低压增强型晶体管和二极管均设置为独立的部件。在其他实施例中，二极管整体集成在高压耗尽型晶体管中。在这些实施例中，具有集成二极管的高压耗尽型晶体管和低压增强型晶体管被设置为独立部件。
图4示出了根据第二实施例的电子部件50。电子部件50包括裸片焊盘51、布置为与裸片焊盘51的第一侧面53相邻且隔开的第一引线52以及布置为与裸片焊盘51的第二侧面55相邻且隔开的第二引线54，第二侧面55与第一侧面53相对。裸片焊盘51的第一侧面53包括基本位于布置第一引线52的侧面53的中心中的凹痕56。裸片焊盘51的第一侧面53与凹痕56邻接的区域具有突出部57，其中突出部提供用于电子部件50的接触区域，例如位于电耦合至裸片焊盘51的电子部件50的外表面和下表面上的接触区域。
第二引线54基本是细长的并且延伸到四个区域58中，这四个区域为电子部件50提供接触区域，例如布置在电子部件50的外表面处的接触区域，其在电子部件50的下表面上提供接触区域。
电子部件50包括高压耗尽型晶体管59，其安装在裸片焊盘51的上表面60上。高压耗尽型晶体管59可以是高电子迁移率晶体管(HEMT)。在该实施例中，HEMT59是基于氮化镓的并且是横向晶体管，其具有布置在其上表面64上的源极焊盘61、漏极焊盘62和栅极焊盘63。HEMT59的后表面安装在裸片焊盘51的上表面60上。
电子部件50还包括低压增强型晶体管65，其在该实施例中是n沟道MOSFEt器件。n沟道MOSFET器件65包括第一表面66(包括源极焊盘67和栅极焊盘68)和第二表面69(与第一表面68相对，包括漏极焊盘70)。
n沟道MOSFET器件65被安装为其第一表面66面向裸片焊盘51的上表面60，并具有所谓的“源极-下”布置。源极焊盘67安装在裸片焊盘51上并电耦合至裸片焊盘51，并且栅极焊盘65安装在上表面71上并电耦合至第一引线52。n沟道MOSFET器件65在裸片焊盘51和第一引线52之间延伸。
n沟道MOSFET器件65的漏极焊盘67例如通过一个或多个导电件(诸如接合线72)电耦合至HEMT59的源极焊盘61。HEMT59的漏极焊盘62例如通过一个或多个其他导电件(诸如接合线73)电耦合至第二引线54。
电子部件50还包括安装在裸片焊盘51的上表面60上的保护二极管75。二极管75是垂直器件，并且具有布置在上表面77上的阳极76和布置在相对后表面81上的阴极80。阴极安装在裸片焊盘51的上表面60上且电耦合至裸片焊盘51。阳极76例如通过一个或多个导电件(诸如接合线78)电耦合至高压耗尽型晶体管59的栅极焊盘65。因此，二极管75耦合在HEMT59的栅极焊盘65和地之间，因为裸片焊盘51为HEMT59、n沟道MOSFET65和二极管75提供了公共地。
在其他实施例中，一条或多条接合线可以被不同类型的导电件(诸如接触夹或带)替代。电子部件50还包括塑料壳体79，其覆盖裸片焊盘51的上表面60、第一引线52的上表面71、第二引线54的上表面，并覆盖HEMT59、n沟道MOSFET65和二极管75。
HEMT59操作性地与n沟道MOSFET65以共源共栅布置耦合，HEMT59的栅极耦合至低电位。只有n沟道MOSFET65的栅极68通过第一引线52有效控制。
图5示出了根据第三实施例的电子部件90。电子部件90包括裸片焊盘91、布置为与裸片焊盘91的第一侧面95相邻且与其隔开的三条引线92、93、94、以及与裸片焊盘91的与第一侧面95相对的第二侧面97相邻的第四引线96。第四引线96基本是细长的，并且包括延伸到电子部件90的外表面99并在电子部件90的下表面上提供外接触区域的突出部98。
电子部件90包括基于氮化镓的HEMT形式的高压耗尽型晶体管100、低压增强型晶体管101(在该实施例中为p沟道MOSFET器件)和二极管102。基于氮化镓的HEMT100是横向器件，并包括位于上表面107上的源极焊盘103、漏极焊盘104以及两个栅极焊盘105、106。基于氮化镓的HEMT100的后表面安装在裸片焊盘91的上表面108上。P沟道MOSFET器件101包括位于其上表面111上的源极焊盘109和栅极焊盘110以及位于其下表面上的漏电极112。漏电极112安装在裸片焊盘91上并电耦合至裸片焊盘91。
二极管102包括位于上表面上的阳极113和位于下表面上的阴极114。阴极114安装在裸片焊盘91上且电耦合至裸片焊盘91。p沟道MOSFET101的栅极焊盘110通过导电件(诸如接合线115)电耦合至第三引线94。p沟道MOSFET101的源极109通过一个或多个导电件(诸如接合线116)电耦合至HEMT100的源极焊盘103。HEMT100的漏极104通过一个或多个导电件(诸如接合线117)电耦合至第四引线96。HEMT100的一个栅极焊盘105通过诸如接合线118的导电件电耦合至第一引线92。第二栅极106通过导电件119电耦合至二极管102的阳极。因此，二极管102耦合在HEMT100的栅极与裸片焊盘91提供的地电位之间。HEMT100的栅极可以通过第一引线92直接控制。二极管102为HEMT100提供保护二极管。第二引线93可用于例如为HEMT100提供感应功能，例如用于HEMT100的源极感应功能。
电子部件90包括塑料壳体120，其覆盖裸片焊盘51的上表面60、引线和电子器件(即，HEMT100、p沟道MOSFET器件101和二极管102)的上表面。
裸片焊盘51以及引线92、93、94、96可以包括铜。安装表面可以包括安装层，其包括适合用于为焊盘提供适当接合的材料。例如，如果软焊料用于将焊盘安装在裸片焊盘上，则安装层可以包括可被焊料润湿的材料，例如Ni/Au。
如果接合线形式的导电元件用于将焊盘电耦合至引线，则焊盘可以包括适合于为接合线形成可靠接合的材料，诸如NiP合金。安装层不限于单层，并且可以包括不同材料的两层或更多层。如果接触夹形式的导电元件用于将焊盘电耦合至引线，则安装层可以包括可被焊料润湿的材料。
在一些实施例中，耦合在高压耗尽型晶体管的栅极和地之间的二极管整体集成在高压耗尽型晶体管中来代替以独立部件的形式来设置。
图6示出了包括基于氮化镓的HEMT形式的化合物半导体器件131的高压耗尽型晶体管130，其形成在衬底132上。在该实施例中，衬底132包括硅并且重掺杂有第一导电类型，例如n+掺杂。轻掺杂有第一导电类型(例如n-掺杂)的第二硅层133布置在衬底132上。一个或多个缓冲层134(诸如AlN)被布置在轻掺杂硅层133上。氮化镓层135被布置在最上面的缓冲层134上。氮化铝镓层136布置在氮化镓层135上。氮化镓层135与氮化铝镓层136之间的界面可以支持通过引发和自发极化形成的二维电子气(2DEG)，其在图6中通过虚线150示意性示出。
源电极137和漏电极138布置在氮化铝镓层136上。源电极137和漏电极138可以部分延伸进入氮化铝镓层136中并且可以延伸并接触氮化镓层135。栅电极139布置在源电极137和漏电极138之间的氮化铝镓层136上。栅电极139可以包括位于金属栅电极139与氮化铝镓层136之间的绝缘层或p掺杂GaN层。氮化铝镓层135可以被钝化层140(诸如氮化硅)覆盖。介电层141可以布置在钝化层140上。
二极管142可以通过在轻掺杂层133中设置相对导电类型(诸如p+)的阱143提供pn结144来整体集成。导电通孔145设置为电耦合至阱143。导电通孔145可以从钝化层140的上表面延伸穿过氮化铝镓层135、穿过氮化镓层134和缓冲层134，并接触阱143。导电通孔145还电耦合至栅极139(在图6中通过线146示意性表示)。二极管142耦合在栅电极139和硅衬底132之间。
金属层147布置在衬底132的后表面148上。由于衬底132被轻掺杂，所以二极管142的阴极电耦合至金属层147。金属层147可用于在电子部件的裸片焊盘149上安装高压耗尽型晶体管130，例如如图1、图4和图5所示。裸片焊盘可以为高压耗尽型晶体管131、二极管142和未示出的低压增强型晶体管提供公共地。
图7示出了高压耗尽型晶体管130’，其与图6所示实施例一样，包括提供基于氮化镓的晶体管结构的重掺杂硅衬底132’、轻掺杂硅层133’和化合物半导体层。高压耗尽型晶体管130’还包括整体集成的二极管142’。二极管142’通过位于导电通孔154’与轻掺杂硅层133’之间的肖特基接触152来制造。肖特基接触152可以通过适当地选择形成导电通孔154或者位于与轻掺杂硅层133’的界面处的材料层的材料来制造。二极管142’耦合在栅电极139’与裸片焊盘149’提供的公共地之间。
为了描述的容易而使用诸如“下方”、“之下”、“下”、“上方”、“上”等的空间相对术语，来解释一个元件相对于第二元件的定位。这些术语用于包括除了图中所示不同定向之外的器件的不同定向。
此外，诸如“第一”、“第二”等的术语也用于描述各种元件、区域、部分等，并且不用于限制。类似的符号在秒书中表示类似的元件。
如本文所使用的，术语“具有”、“包含”、“包括”等是开放性的术语，其表示所提元件或部件的存在，但是不排除附加元件或部件。定冠词“一个”、“该”用于包括多个以及单个，除非另有明确说明。
应该理解，本文所描述的各种实施例的特征可以相互组合，除非另有指定。
尽管本文示出和描述了具体实施例，但本领域技术人员应该理解，在不背离本发明范围的情况下可以进行各种可选和/或等效实施来替代所示和描述的具体实施例。本申请用于覆盖本文所讨论的具体实施例的任何修改或改变。因此，仅通过权利要求及其等效物来限制本发明。

Claims (20)

1.一种电子部件，包括：
高压耗尽型晶体管，包括与低压增强型晶体管的电流路径串联耦合的电流路径；
二极管，包括阳极和阴极；以及
裸片焊盘，
其中所述高压耗尽型晶体管的后表面安装在所述裸片焊盘上并电耦合至所述裸片焊盘，所述低压增强型晶体管的第一电流电极安装在所述裸片焊盘上并电耦合至所述裸片焊盘，所述二极管的所述阳极耦合至所述高压耗尽型晶体管的控制电极，并且所述二极管的所述阴极安装在所述裸片焊盘上。
2.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管操作性地以共源共栅布置连接至所述低压增强型晶体管。
3.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管被直接驱动。
4.根据权利要求1所述的电子部件，其中所述二极管至少部分地集成到所述高压耗尽型晶体管中。
5.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管包括分立部件，所述低压增强型晶体管包括分立部件并且所述二极管设置为分立部件。
6.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管的栅极还耦合至所述电子部件的接触焊盘。
7.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管的栅极还耦合至所述低压增强型晶体管的低压电流电极。
8.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管和所述低压增强型晶体管在组合封装件中被安装为彼此相邻。
9.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管包括具有第一电流电极、第二电流电极和控制电极的第一侧，其中所述低压增强型晶体管包括具有第一电流电极和控制电极的第一侧以及与所述第一侧相对的第二侧，所述第二侧包括第二电流电极。
10.根据权利要求9所述的电子部件，其中所述低压增强型晶体管的第二电流电极耦合至所述高压耗尽型晶体管的第一电流电极。
11.根据权利要求9所述的电子部件，其中所述低压增强型晶体管的第一电流电极安装在所述裸片焊盘上。
12.根据权利要求9所述的电子部件，其中所述低压增强型晶体管的控制电极安装在布置为与所述裸片焊盘相邻且与所述裸片焊盘隔开的引线上。
13.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管包括具有第一电流电极、第二电流电极和控制电极的第一侧，其中所述低压增强型晶体管包括具有第二电流电极的第一侧、具有第一电流电极和控制电极的第二侧，并且其中所述低压增强型晶体管的第二电流电极安装在所述裸片焊盘上。
14.根据权利要求13所述的电子部件，其中所述低压增强型晶体管的第一电流电极耦合至所述高压耗尽型晶体管的第一电流电极。
15.根据权利要求13所述的电子部件，其中所述低压增强型晶体管的控制电极耦合至引线。
16.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管还包括第一导电类型的重掺杂半导体衬底、位于所述重掺杂半导体衬底上的所述第一导电类型的轻掺杂半导体层以及布置在所述轻掺杂半导体层上的化合物半导体层。
17.根据权利要求16所述的电子部件，其中所述二极管包括布置在所述轻掺杂半导体层中的重掺杂p阱以及耦合至所述高压耗尽型晶体管的控制电极的导电通孔。
18.根据权利要求16所述的电子部件，其中所述二极管包括具有所述轻掺杂半导体掺杂层的肖特基接触以及耦合至所述高压耗尽型晶体管的控制电极的导电通孔。
19.根据权利要求1所述的电子部件，其中所述高压耗尽型晶体管是基于III族-氮化物的高电子迁移率晶体管。
20.根据权利要求1所述的电子部件，其中从由IGBT、p沟道MOSFET和n沟道MOSFET组成的组中选择所述低压增强型晶体管。
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