CN105428426A - 一种二级管用外延片及其制备方法 - Google Patents

一种二级管用外延片及其制备方法 Download PDF

Info

Publication number
CN105428426A
CN105428426A CN201510755545.8A CN201510755545A CN105428426A CN 105428426 A CN105428426 A CN 105428426A CN 201510755545 A CN201510755545 A CN 201510755545A CN 105428426 A CN105428426 A CN 105428426A
Authority
CN
China
Prior art keywords
layer
resilient coating
gan resilient
ngan
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510755545.8A
Other languages
English (en)
Other versions
CN105428426B (zh
Inventor
王东盛
苗操
李亦衡
魏鸿源
严文胜
张葶葶
朱廷刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JIANGSU NENGHUA MICROELECTRONIC TECHNOLOGY DEVELOPMENT Co Ltd
Original Assignee
JIANGSU NENGHUA MICROELECTRONIC TECHNOLOGY DEVELOPMENT Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JIANGSU NENGHUA MICROELECTRONIC TECHNOLOGY DEVELOPMENT Co Ltd filed Critical JIANGSU NENGHUA MICROELECTRONIC TECHNOLOGY DEVELOPMENT Co Ltd
Priority to CN201510755545.8A priority Critical patent/CN105428426B/zh
Publication of CN105428426A publication Critical patent/CN105428426A/zh
Application granted granted Critical
Publication of CN105428426B publication Critical patent/CN105428426B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02414Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66143Schottky diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

<b>本发明提供一种二级管用外延片及其制备方法,由其制成的二极管电子器件漏电较低、击穿电压较高、寿命较长。一种二级管用外延片,包括:图形化蓝宝石衬底;</b><b>AlN</b><b>成核层,通过磁控溅射技术沉积于所述图形化蓝宝石衬底的上表面;</b><b>GaN</b><b>缓冲层,其沉积于所述</b><b>AlN</b><b>成核层的上表面,所述</b><b>GaN</b><b>缓冲层为</b><b>C</b><b>掺杂的</b><b>GaN</b><b>缓冲层;外延结构层,其沉积于所述</b><b>GaN</b><b>缓冲层的上表面。</b>

Description

一种二级管用外延片及其制备方法
技术领域
本发明涉及一种二极管用外延片及其制备方法。
背景技术
目前用于二极管的外延片的衬底主要有两种,即蓝宝石衬底和碳化硅衬底。但由于碳化硅的价格昂贵,故蓝宝石衬底的使用更为广泛。现有技术中普遍使用的平片状蓝宝石衬底由于其位错密度较高,制成的二极管电子器件漏电流较高、易击穿。
发明内容
针对上述问题,本发明的目的是提供一种二级管用外延片及其制备方法,由其制成的二极管电子器件漏电较低、击穿电压较高、寿命较长。
为解决上述技术问题,本发明采用的技术方案为:
一种二级管用外延片,包括:
图形化蓝宝石衬底;
AlN成核层,通过磁控溅射技术沉积于所述图形化蓝宝石衬底的上表面;
GaN缓冲层,其沉积于所述AlN成核层的上表面,所述GaN缓冲层为C掺杂的GaN缓冲层;
外延结构层,其沉积于所述GaN缓冲层的上表面。
优选地,所述图形化蓝宝石衬底的图形高度为1~2μm,图形宽度为1.5~6μm,图形间隙为0.1~2μm。
优选地,所述AlN成核层是厚度为5~25nm的多晶AlN层。
优选地,所述GaN缓冲层中C的掺杂源为TMGa、CCl 4 或C 2 H 2
优选地,所述GaN缓冲层中C的掺杂浓度为5E15~1E19cm -3 ,且所述GaN缓冲层的厚度为2~3μm。
优选地,所述外延结构层包括:
AlGaN层,其沉积于所述GaN缓冲层的上表面且厚度为30~300nm;
重掺杂nGaN层,其沉积于所述AlGaN层的上表面且掺杂浓度为5E18~2E19cm -3 ,所述重掺杂nGaN层的厚度为2.5~3μm;
轻掺杂nGaN层,其沉积于所述重掺杂nGaN层的上表面且掺杂浓度为4E15~2E16cm -3 ,所述轻掺杂nGaN层的厚度为5~15μm。
更优选地,所述AlGaN层中Al的摩尔百分含量为5~20%。
本发明采用的又一技术方案是:
一种所述的二级管用外延片的制备方法,包括如下步骤:
A、在图形化蓝宝石衬底的上表面磁控溅射形成一层多晶AlN成核层;
B、加热升温至1040~1080℃,保持压力为30~400mbar,通过MOCVD技术在AlN成核层的上表面生长C掺杂的GaN缓冲层。
优选地,还包括如下步骤:
C、在950~1050℃下,在GaN缓冲层的上表面生长AlGaN层;
D、在1000~1080℃下,在AlGaN层的上表面生长重掺杂nGaN层;
E、保持温度不变,在重掺杂nGaN层的上表面生长轻掺杂nGaN层;
上述各步骤的顺序为依次进行。
更优选地,所述重掺杂nGaN层、轻掺杂nGaN层的生长压力均为100~700mbar,生长温度均为1000~1080℃。
本发明采用以上技术方案,相比现有技术具有如下优点:使用磁控溅射技术在图形化蓝宝石衬底沉积AlN成核层,并在AlN上生长外延结构层的掺C的GaN缓冲层,相比使用其它类型的蓝宝石衬底(如蓝宝石平片)制作的肖特基二极管,晶体质量较好,位错密度由现有技术中的1E9cm -3 降低至6E7cm -3 。本发明的二极管外延片制作的肖特基二极管器件漏电较低,散热较好,击穿电压较高,寿命较长。
具体实施方式
下面对本发明的较佳实施例进行详细阐述,以使本发明的优点和特征能更易于被本领域的技术人员理解。
本发明的一种二级管用外延片,该二级管用外延片包括自下至上依次层叠的衬底、AlN成核层、GaN缓冲层、AlGaN层、重掺杂nGaN层、轻掺杂nGaN层。其中,AlGaN层、重掺杂nGaN层、轻掺杂nGaN层构成外延片的外延结构层。
衬底为图形化蓝宝石衬底(PSS)。图形化蓝宝石衬底的图形高度为1~2μm,图形宽度为1.5~6μm,图形间隙为0.1~2μm。图形化蓝宝石衬底通过纳米压印光刻技术、stepper光刻技术、干法刻蚀技术或湿法刻蚀技术制备而成。图像化蓝宝石衬底的图像为正圆锥形,或者为类圆锥形,类圆锥形是指其侧壁为向外突的弧形。
成核层通过磁控溅射技术沉积于图形化蓝宝石衬底的上表面。AlN成核层是厚度为5~25nm的多晶AlN层。
缓冲层为C掺杂的GaN缓冲层,C的掺杂源为TMGa、CCl 4 或C 2 H 2 。GaN缓冲层中C的掺杂浓度为5E15~1E19cm -3 ,GaN缓冲层的厚度为2~3μm。
层、重掺杂nGaN层、轻掺杂nGaN层构成三级管用外延片的外延结构层。其中,AlGaN层沉积于GaN缓冲层的上表面且厚度为30~300nm,AlGaN层中Al的摩尔百分含量为5~20%;重掺杂nGaN层沉积于AlGaN层的上表面且掺杂浓度为5E18~2E19cm -3 ,重掺杂nGaN层的厚度为2.5~3μm;轻掺杂nGaN层沉积于重掺杂nGaN层的上表面且掺杂浓度为4E15~2E16cm -3 ,轻掺杂nGaN层的厚度为5~15μm。
一种上述二级管用外延片的制备方法,依次包括如下步骤:
A、通过磁控溅射设备在图形化蓝宝石衬底的上表面磁控溅射形成一层多晶AlN成核层;
B、加热升温至1040~1080℃,保持压力为30~400mbar,将带有AlN成核层的图像化蓝宝石衬底放入MOCVD中,通过MOCVD技术在AlN成核层的上表面生长C掺杂的GaN缓冲层;
C、在950~1050℃下,在GaN缓冲层的上表面生长AlGaN层;
D、在1000~1080℃下,在AlGaN层的上表面生长重掺杂nGaN层;
E、保持温度不变,在重掺杂nGaN层的上表面生长轻掺杂nGaN层。
其中,重掺杂nGaN层、轻掺杂nGaN层的生长压力均为100~700mbar,生长温度均为1000~1080℃。
相比平片蓝宝石衬底制成的三极管外延片,本发明在图像化蓝宝石衬底上通过磁控溅射生长一层多晶AlN成核层,在通过MOCVD技术生长一层掺C的GaN缓冲层,在此基础上制成的二极管外延片的位错密度由现有技术中的1E9cm -3 降低至6E7cm -3
上述实施例只为说明本发明的技术构思及特点,是一种优选的实施例,其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施,并不能以此限制本发明的保护范围。凡根据本发明的精神实质所作的等效变化或修饰,都应涵盖在本发明的保护范围之内。

Claims (10)

1.一种二级管用外延片,其特征在于,包括:
图形化蓝宝石衬底;
AlN成核层,通过磁控溅射技术沉积于所述图形化蓝宝石衬底的上表面;
GaN缓冲层,其沉积于所述AlN成核层的上表面,所述GaN缓冲层为C掺杂的GaN缓冲层;
外延结构层,其沉积于所述GaN缓冲层的上表面。
2.根据权利要求1所述的二极管用外延片,其特征在于:所述图形化蓝宝石衬底的图形高度为1~2μm,图形宽度为1.5~6μm,图形间隙为0.1~2μm。
3.根据权利要求1所述的二极管用外延片,其特征在于:所述AlN成核层是厚度为5~25nm的多晶AlN层。
4.根据权利要求1所述的二极管用外延片,其特征在于:所述GaN缓冲层中C的掺杂源为TMGa、CCl4或C2H2
5.根据权利要求1所述的二极管用外延片,其特征在于:所述GaN缓冲层中C的掺杂浓度为5E15~1E19cm-3,且所述GaN缓冲层的厚度为2~3μm。
6.根据权利要求1所述的二极管用外延片,其特征在于,所述外延结构层包括:
AlGaN层,其沉积于所述GaN缓冲层的上表面且厚度为30~300nm;
重掺杂nGaN层,其沉积于所述AlGaN层的上表面且掺杂浓度为5E18~2E19cm-3,所述重掺杂nGaN层的厚度为2.5~3μm;
轻掺杂nGaN层,其沉积于所述重掺杂nGaN层的上表面且掺杂浓度为4E15~2E16cm-3,所述轻掺杂nGaN层的厚度为5~15μm。
7.根据权利要求6所述的二极管用外延片,其特征在于:所述AlGaN层中Al的摩尔百分含量为5~20%。
8.一种如权利要求1-7任一项所述的二级管用外延片的制备方法,其特征在于,包括如下步骤:
A、在图形化蓝宝石衬底的上表面磁控溅射形成一层多晶AlN成核层;
B、加热升温至1040~1080℃,保持压力为30~400mbar,通过MOCVD技术在AlN成核层的上表面生长C掺杂的GaN缓冲层。
9.根据权利要求8所述的制备方法,其特征在于,还包括如下步骤:
C、在950~1050℃下,在GaN缓冲层的上表面生长AlGaN层;
D、在1000~1080℃下,在AlGaN层的上表面生长重掺杂nGaN层;
E、保持温度不变,在重掺杂nGaN层的上表面生长轻掺杂nGaN层;
上述各步骤的顺序为依次进行。
10.根据权利要求9所述的制备方法,其特征在于:所述重掺杂nGaN层、轻掺杂nGaN层的生长压力均为100~700mbar,生长温度均为1000~1080℃。
CN201510755545.8A 2015-11-09 2015-11-09 一种肖特基二极管用外延片及其制备方法 Active CN105428426B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510755545.8A CN105428426B (zh) 2015-11-09 2015-11-09 一种肖特基二极管用外延片及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510755545.8A CN105428426B (zh) 2015-11-09 2015-11-09 一种肖特基二极管用外延片及其制备方法

Publications (2)

Publication Number Publication Date
CN105428426A true CN105428426A (zh) 2016-03-23
CN105428426B CN105428426B (zh) 2019-07-19

Family

ID=55506489

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510755545.8A Active CN105428426B (zh) 2015-11-09 2015-11-09 一种肖特基二极管用外延片及其制备方法

Country Status (1)

Country Link
CN (1) CN105428426B (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098747A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 一种肖特基二极管用外延片及其制备方法
CN106098798A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 肖特基二极管用外延片及其制备方法
CN106098795A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 一种二极管用外延片及其制备方法
CN106098793A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 肖特基二极管用外延片及其制备方法
CN106098746A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 一种二极管用外延片及其制备方法
CN106098796A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 二极管用外延片及其制备方法
CN106098794A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 二极管用外延片及其制备方法
CN106098797A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 一种二极管用外延片及其制备方法
CN109860023A (zh) * 2018-12-29 2019-06-07 杭州士兰明芯科技有限公司 氮化镓晶体管及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915537A (zh) * 2013-01-09 2014-07-09 理想能源设备(上海)有限公司 硅衬底上化合物半导体外延层生长方法及其器件结构
US20140264370A1 (en) * 2013-03-15 2014-09-18 Transphorm Inc. Carbon doping semiconductor devices
CN104485402A (zh) * 2014-12-29 2015-04-01 厦门市三安光电科技有限公司 图形化蓝宝石衬底的制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915537A (zh) * 2013-01-09 2014-07-09 理想能源设备(上海)有限公司 硅衬底上化合物半导体外延层生长方法及其器件结构
US20140264370A1 (en) * 2013-03-15 2014-09-18 Transphorm Inc. Carbon doping semiconductor devices
CN104485402A (zh) * 2014-12-29 2015-04-01 厦门市三安光电科技有限公司 图形化蓝宝石衬底的制作方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098747A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 一种肖特基二极管用外延片及其制备方法
CN106098798A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 肖特基二极管用外延片及其制备方法
CN106098795A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 一种二极管用外延片及其制备方法
CN106098793A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 肖特基二极管用外延片及其制备方法
CN106098746A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 一种二极管用外延片及其制备方法
CN106098796A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 二极管用外延片及其制备方法
CN106098794A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 二极管用外延片及其制备方法
CN106098797A (zh) * 2016-06-30 2016-11-09 江苏能华微电子科技发展有限公司 一种二极管用外延片及其制备方法
CN109860023A (zh) * 2018-12-29 2019-06-07 杭州士兰明芯科技有限公司 氮化镓晶体管及其制造方法

Also Published As

Publication number Publication date
CN105428426B (zh) 2019-07-19

Similar Documents

Publication Publication Date Title
CN105428426A (zh) 一种二级管用外延片及其制备方法
KR101909919B1 (ko) 응력 완화 반도체 층
CN101800170B (zh) 制造第ⅲ族氮化物半导体的方法和模板衬底
US7915698B2 (en) Nitride semiconductor substrate having a base substrate with parallel trenches
US20120187444A1 (en) Template, method for manufacturing the template and method for manufacturing vertical type nitride-based semiconductor light emitting device using the template
Youtsey et al. Wafer‐scale epitaxial lift‐off of GaN using bandgap‐selective photoenhanced wet etching
JP2007243155A (ja) GaN半導体装置および多結晶炭化ケイ素基板上のサファイア薄層上のGaNを用いる方法
JP5758880B2 (ja) 半導体素子用エピタキシャル基板、半導体素子、および半導体素子用エピタキシャル基板の作製方法
JP2018168029A (ja) Iii族窒化物半導体成長用テンプレート
CN104201196B (zh) 表面无微裂纹的Si基III族氮化物外延片
CN105489714A (zh) 一种多孔氮化铝复合衬底及其在外延生长高质量氮化镓薄膜中的应用
JP2011524322A5 (zh)
JPWO2011122322A1 (ja) エピタキシャル基板およびエピタキシャル基板の製造方法
CN100483738C (zh) 基于自支撑SiC的GaN器件及制作方法
CN106910675A (zh) 一种用于制备氮化物电子器件的复合衬底及其制备方法
CN105336605A (zh) 二级管用外延片及其制备方法
CN101901756A (zh) 基于c面Al2O3衬底上极性c面GaN薄膜的MOCVD生长方法
CN105336769A (zh) 三级管用外延片及其制备方法
CN105448651B (zh) 一种衬底上的外延片及其制作方法
CN104134733A (zh) 一种用于生长半导体薄膜的图形化衬底及其制备方法
JP2014192226A (ja) 電子デバイス用エピタキシャル基板
CN105140364A (zh) 一种GaN发光器件及其制备方法
Kim et al. Epitaxial lateral overgrowth of GaN on sapphire substrates using in-situ carbonized photoresist mask
CN106910807A (zh) 一种用于生长外延片的复合衬底及其制备方法
Wu et al. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant