CN106098798A - 肖特基二极管用外延片及其制备方法 - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 21
- 239000011435 rock Substances 0.000 claims abstract description 14
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 12
- 239000010980 sapphire Substances 0.000 claims abstract description 12
- 238000011065 in-situ storage Methods 0.000 claims abstract description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 94
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000002344 surface layer Substances 0.000 abstract description 3
- 238000005036 potential barrier Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000013517 stratification Methods 0.000 description 2
- 238000003763 carbonization Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
本发明公开了一种肖特基二极管用外延片及其制备方法。该二极管外延片,包括依次层叠设置的衬底、GaN二维生长层、SiNx模板层、GaN恢复层、重掺杂nGaN层、轻掺杂nGaN层,外延片还包括覆盖在轻掺杂nGaN层的背离重掺杂nGaN层一侧的另一侧面上的AlN帽层,其中,的衬底为带有AlN盖层的蓝宝石平片衬底,的SiNx模板层是在GaN二维生长层的背离衬底一侧的另一侧面上使用SiH4和NH3原位生长形成的,SiNx层的厚度低于一个原子层的厚度。本发明的外延片,其表面层的势垒高、厚度极薄,使得电荷易隧穿,使制成的器件的反向击穿电压可显著提高,同时该外延片的位错密度低,使制成的器件的漏电较低,增加了器件的反向击穿电压和正向导通电流,延长了器件的使用寿命。
Description
技术领域
本发明涉及半导体制造技术领域,具体涉及一种肖特基二极管用外延片及其制备方法。
背景技术
肖特基二极管利用金属与半导体接触形成的金属-半导体接触原理制作而成,是一种热载流子二极管,具有低正向电压、超高速等特点,被广泛地应用在高频、大电流、低电压整流电路以及微波电子混频电路、检波电路、高频数字逻辑电路、交流-直流变换系统中,是电子器件中常见的分立器件。现有技术中,肖特基二极管普遍采用外延片作为其半导体部件。而用于GaN肖特基二极管的外延片的衬底主要有三种,即蓝宝石衬底、硅衬底和碳化硅衬底。其中,由于碳化硅的价格昂贵,而Si衬底不适合用于制作垂直结构的肖特基二极管,故蓝宝石衬底在垂直结构的肖特基二极管中应用更为广泛。现有技术中普遍使用的平片状蓝宝石衬底由于其位错密度较高,制成的二极管电子器件漏电流较高、易击穿、晶体质量不高。
发明内容
本发明的目的是提供一种肖特基二极管用外延片及其制备方法。
为达到上述目的,本发明采用的一种技术方案是:一种肖特基二极管用外延片,包括依次层叠设置的衬底、GaN二维生长层、SiNx模板层、GaN恢复层、重掺杂nGaN层、轻掺杂nGaN层,所述外延片还包括覆盖在所述轻掺杂nGaN层的背离所述重掺杂nGaN层一侧的另一侧面上的AlN帽层,其中,所述的衬底为带有AlN盖层的蓝宝石平片衬底,所述的SiNx模板层是在GaN二维生长层的背离所述衬底一侧的另一侧面上使用SiH4和NH3原位生长形成的,所述SiNx层的厚度低于一个原子层的厚度。
优选地,所述衬底中的AlN盖层厚度为5~200nm。
进一步优选地,所述衬底是由所述AlN盖层采用PVD或sputter设备在蓝宝石平片上制作而成的。
优选地,所述GaN二维生长层的厚度为0.3~1μm;所述GaN恢复层的厚度为2~5μm;所述重掺杂nGaN层的厚度为2~3.5μm;所述轻掺杂nGaN层的厚度为4~12μm,所述AlN帽层的厚度为1~20nm。
优选地所述重掺杂nGaN层和轻掺杂nGaN层的掺杂源均为SiH4,其掺杂浓度分别为1E18~1.5E19cm-3和3E15~1.5E16cm-3。
本发明的又一技术方案为:
一种如上述肖特基二极管用外延片的制备方法,其特征在于,包括如下步骤:
A、将带有AlN盖层的所述衬底放入MOCVD设备中加热升温至1040~1100℃,而后在所述衬底上直接生长所述GaN二维生长层;
B、在950~1050℃温度下,在所述GaN二维生长层上生长所述SiNx模板层;
C、在1000~1080℃温度下,在所述SiNx模板层上依次生长所述GaN恢复层和所述重掺杂nGaN层;
D、保持温度不变,在所述重掺杂nGaN层上生长所述轻掺杂nGaN层;
E、在450~800℃温度下,在所述轻掺杂nGaN层上生长所述AlN帽层;
上述各步骤的顺序为依次进行。
优选地,所述GaN二维生长层的生长压力为30~400mbar。
优选地,所述重掺杂nGaN层、轻掺杂nGaN层的生长压力均为200~700mbar。
优选地,所述AlN帽层的生长压力为20~400mbar。
本发明采用以上技术方案,相比现有技术具有如下优点:
1、本发明的衬底通过在蓝宝石平片上覆盖AlN盖层来替代低温GaN缓冲层,同时在GaN二维生长层上原位生长SiNx模板层,显著减少了刃位错密度和螺位错密度,使二极管外延片结构的XRD102和002分别降低至100arcsec和80arcsec以下,总位错密度降低至5*107/cm3以下。低位错密度减少了肖特基二极管终端器件的漏电通道,可显著提高反向击穿电压和正向导通电流,提高了外延片的晶体质量、增加了器件的使用寿命;同时还节约了生长时间。
本发明中还使用了AlN帽层结构,该AlN帽层的能隙宽度为6.2eV以上。采用该帽层结构可非常显著地提高表面层的势垒高度,同时,由于该层厚度极薄,电荷很容易遂穿,因此,由本发明的外延片制成的二极管终端器件的反向击穿电压可显著升高,但同时其正向导通电压不会发生明显变化。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图,其中:
附图1是本发明所述的肖特基二极管用外延片的结构示意图。
上述附图中:1、衬底;11、蓝宝石平片;12、AlN盖层;2、GaN二维生长层;3、SiNx模板层;4、GaN恢复层;5、重掺杂nGaN层;6、轻掺杂nGaN层;7、AlN帽层。
具体实施方式
下面结合附图来对本发明的技术方案作进一步的阐述。
参见图1所示,一种肖特基二极管用外延片,包括衬底以及沿其厚度方向依次覆盖在衬底一侧面上的GaN二维生长层、SiNx模板层、GaN恢复层、重掺杂nGaN层、轻掺杂nGaN层、AlN帽层。
其中,该衬底为带有AlN盖层12的蓝宝石平片11衬底,该衬底由AlN盖层12采用PVD或sputter设备在蓝宝石平片11上制作而成,该AlN盖层12厚度为5~200nm。
该SiNx模板层是在GaN二维生长层上使用SiH4和NH3原位生长形成的,该SiNx层的厚度低于一个原子层的厚度。
这里,通过采用AlN盖层12替代了低温GaN层,同时配合SiNx模板层,可显著减少了整个外延片的刃位错密度和螺位错密度,使肖特基二极管外延片结构的XRD102和002分别降低至100arcsec和80arcsec以下,总位错密度降低至5*107/cm3以下。低位错密度减少了肖特基二极管终端器件的漏电通道,可显著提高反向击穿电压和正向导通电流,提高了外延片的晶体质量,增加了器件的使用寿命,同时还节约了外延片的生长时间。
而这里使用了AlN帽层结构,该AlN帽层的能隙宽度为6.2eV以上。采用该帽层结构可非常显著地提高表面层的势垒高度,同时,由于该层厚度极薄,电荷很容易遂穿,因此,由本发明的外延片制成的二极管终端器件的反向击穿电压可显著升高,但同时其正向导通电压不会发生明显变化。
本例中,该GaN二维生长层的厚度为0.3~1μm;GaN恢复层的厚度为2~5μm;重掺杂nGaN层的厚度为2~3.5μm;轻掺杂nGaN层的厚度为4~12μm,AlN帽层的厚度为1~20nm。
这里,重掺杂nGaN层和轻掺杂nGaN层的掺杂源均为SiH4,其掺杂浓度分别为1E18~1.5E19cm-3和3E15~1.5E16cm-3。
一种上述肖特基二极管用外延片的制备方法,包括如下步骤:
A、将衬底放入MOCVD设备中加热升温至1040~1100℃,而后在衬底上直接生长GaN二维生长层;
B、在950~1050℃温度下,在GaN二维生长层上原位生长SiNx模板层;
C、在1000~1080℃温度下,在SiNx模板层上依次生长GaN恢复层和重掺杂nGaN层;
D、保持温度不变,在重掺杂nGaN层上生长轻掺杂nGaN层;
E、在450~800℃温度下,在轻掺杂nGaN层上生长AlN帽层。
其中,GaN二维生长层的生长压力为30~400mbar;重掺杂nGaN层、轻掺杂nGaN层的生长压力均为200~700mbar;而AlN帽层的生长压力为20~400mbar。
上述实施例只为说明本发明的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本发明的内容并加以实施,并不能以此限制本发明的保护范围,凡根据本发明精神实质所作的等效变化或修饰,都应涵盖在本发明的保护范围内。
Claims (9)
1.一种肖特基二极管用外延片,包括依次层叠设置的衬底、GaN二维生长层、SiNx模板层、GaN恢复层、重掺杂nGaN层、轻掺杂nGaN层,其特征在于,所述外延片还包括覆盖在所述轻掺杂nGaN层的背离所述重掺杂nGaN层一侧的另一侧面上的AlN帽层,其中,所述的衬底为带有AlN盖层的蓝宝石平片衬底,所述的SiNx模板层是在GaN二维生长层的背离所述衬底一侧的另一侧面上使用SiH4和NH3原位生长形成的,所述SiNx层的厚度低于一个原子层的厚度。
2.根据权利要求1所述的肖特基二极管用外延片,其特征在于,所述衬底中的AlN盖层厚度为5~200nm。
3.根据权利要求2所述的肖特基二极管用外延片,其特征在于,所述衬底是由所述AlN盖层采用PVD或sputter设备在蓝宝石平片上制作而成的。
4.根据权利要求1所述的肖特基二极管用外延片,其特征在于,所述GaN二维生长层的厚度为0.3~1μm;所述GaN恢复层的厚度为2~5μm;所述重掺杂nGaN层的厚度为2~3.5μm;所述轻掺杂nGaN层的厚度为4~12μm,所述AlN帽层的厚度为1~20nm。
5.根据权利要求1所述的肖特基二极管用外延片,其特征在于,所述重掺杂nGaN层和轻掺杂nGaN层的掺杂源均为SiH4,其掺杂浓度分别为1E18~1.5E19cm-3和3E15~1.5E16 cm-3。
6.一种如权利要求1至5任一项所述的肖特基二极管用外延片的制备方法,其特征在于,包括如下步骤:
A、将带有AlN盖层的所述衬底放入MOCVD设备中加热升温至1040~1100℃,而后在所述衬底上直接生长所述GaN二维生长层;
B、在950~1050℃温度下,在所述GaN二维生长层上生长所述SiNx模板层;
C、在1000~1080℃温度下,在所述SiNx模板层上依次生长所述GaN恢复层和所述重掺杂nGaN层;
D、保持温度不变,在所述重掺杂nGaN层上生长所述轻掺杂nGaN层;
E、在450~800℃温度下,在所述轻掺杂nGaN层上生长所述AlN帽层;
上述各步骤的顺序为依次进行。
7.根据权利要求6所述的制备方法,其特征在于,所述GaN二维生长层的生长压力为30~400mbar。
8.根据权利要求6所述的制备方法,其特征在于,所述重掺杂nGaN层、轻掺杂nGaN层的生长压力均为200~700mbar。
9.根据权利要求6所述的制备方法,其特征在于,所述AlN帽层的生长压力为20~400mbar。
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CN105428426A (zh) * | 2015-11-09 | 2016-03-23 | 江苏能华微电子科技发展有限公司 | 一种二级管用外延片及其制备方法 |
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CN101132022A (zh) * | 2007-09-29 | 2008-02-27 | 西安电子科技大学 | 基于组份渐变GaN MISFET的GaN器件及制备方法 |
US20150228858A1 (en) * | 2012-09-27 | 2015-08-13 | Osram Opto Semiconductors Gmbh | Optoelectronic component with a layer structure |
US20140231818A1 (en) * | 2013-02-20 | 2014-08-21 | Erdem Arkun | AlN CAP GROWN ON GaN/REO/SILICON SUBSTRATE STRUCTURE |
CN103952683A (zh) * | 2013-06-14 | 2014-07-30 | 西安电子科技大学 | 含有SiNx插入层的半极性m面GaN基的半导体器件的制备方法 |
CN105428426A (zh) * | 2015-11-09 | 2016-03-23 | 江苏能华微电子科技发展有限公司 | 一种二级管用外延片及其制备方法 |
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