CN105322009A - 氮化镓基高电子迁移率晶体管外延结构及其制造方法 - Google Patents

氮化镓基高电子迁移率晶体管外延结构及其制造方法 Download PDF

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CN105322009A
CN105322009A CN201510757512.7A CN201510757512A CN105322009A CN 105322009 A CN105322009 A CN 105322009A CN 201510757512 A CN201510757512 A CN 201510757512A CN 105322009 A CN105322009 A CN 105322009A
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陈振
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JIANGXI CHANGDA OPTOELECTRONICS TECHNOLOGY Co Ltd
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Abstract

本发明公开了一种氮化镓基高电子迁移率晶体管外延结构及其制造方法。该外延结构包括衬底层，在该衬底层上从下至上依次生长有AlN成核层、AlGaN缓冲层、Al掺杂GaN模板层和AlGaN势垒层。本发明通过在制造氮化镓基高电子迁移率晶体管外延结构时，利用Al掺杂形成GaN模板层的方法，能够降低材料的位错密度，改善界面的平整度，提高材料的电子迁移率，减少异质外延AlGaN势垒层表面态密度，进而降低了器件的漏电流，提高了器件的击穿电压且工艺简单易行。

Description

氮化镓基高电子迁移率晶体管外延结构及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种氮化镓基高电子迁移率晶体管外延结构及其制造方法。
背景技术
GaN具有较大的直接禁带宽度(3.4ev)、高热导率、高电子饱和漂移速度等特点，因此已经成为目前半导体技术领域的研究热点。特别地，氮化镓基高电子迁移率场效应晶体管(HEMT)是一种基于氮化物异质结构的新型电子器件。该器件具有高频、大功率的优异特性，广泛应用于无线通信基站、电力电子器件等信息收发、能量转换等领域。
高电子迁移率晶体管(HEMT)的原理是由于组成异质结构的两种材料的禁带宽度不同，在异质结界面处形成了势垒和势阱，由极化效应或调制掺杂产生的自由电子，积累在非掺杂的氮化镓层靠近界面的三角形势阱中，形成二维电子气，由于势阱中的这些电子与势垒中的电离杂质空间分离，大大降低了库伦散射，从而提高了材料的电子迁移率。研制成器件后，通过调节栅电极偏压可以控制异质结界面处的二维电子气密度，在一定的直流偏压下，可以对高频微波信号进行放大。
现有技术氮化镓基HEMTs器件的外延结构一般如图1所示。其生长过程是：先在Si衬底上依次生长一AlN成核层和AlGaN缓冲层；再在缓冲层上生长一GaN沟道层；随后再生长一AlGaN势垒层。但是由于AlGaN势垒层和GaN沟道层之间存在晶格失配和热失配，使得AlGaN异质外延生长时会产生高密度的位错。AlGaN/GaN异质结中高密度的位错不但增加了缓冲层和栅极的漏电流，而且对二维电子气的密度和迁移速率产生巨大的影响。如失配位错、合金混乱以及界面粗糙等缺陷都对二维电子气有很强的散射作用，进而降低了AlGaN/GaN基高电子迁移率晶体管的射频性能。
发明内容
针对上述现有技术的不足，本发明的一个目的是提供一种结构简单、位错密度小且集成电压高的氮化镓基高电子迁移率晶体管外延结构。
为了实现上述目的，本发明采用以下技术方案：一种氮化镓基高电子迁移率晶体管外延结构，包括SiC或Si衬底层，在该衬底层上从下至上依次形成AlN成核层、AlGaN缓冲层、GaN沟道层、Si掺杂AlGaN势垒层和GaN盖帽层。
优选地，所述Si掺杂AlGaN势垒层中Si掺杂的浓度为1×1017cm-3-2×1019cm-3
为了实现上述氮化镓基高电子迁移率晶体管外延结构，本发明的另一个目的是提供一种氮化镓基高电子迁移率晶体管外延结构的制造方法，该方法包括：一种氮化镓基高电子迁移率晶体管外延结构的制造方法，该方法包括，在SiC或Si衬底上依次生长完AlN成核层、AlGaN缓冲层、GaN沟道层后，再生长Si掺杂AlGaN势垒层，最后生长GaN盖帽层。
优选地，所述Si掺杂AlGaN势垒层中Si掺杂的浓度为1×1017cm-3-2×1019cm-3。
本发明的有益效果是：利用Si掺杂形成AlGaN势垒层的方法，能够降低材料的位错密度，改善界面的平整度，提高材料的电子迁移率，减少异质外延AlGaN势垒层表面态密度，进而降低了器件的漏电流，提高了器件的击穿电压且工艺简单易行。
附图说明
图1为现有技术氮化镓基HEMTs器件的外延结构示意图。
图2为本发明所述的一个氮化镓基高电子迁移率晶体管结构示意图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合实施例，对本发明进行进一步的详细说明。
实施例一
本实施例提供一个氮化镓基高电子迁移率晶体管，如图2所示，在SiC或Si衬底210上生长一层AlN成核层220，再生长AlGaN缓冲层230，随后生长GaN沟道层240，然后生长一Si掺杂浓度为1×1017cm-3的AlGaN势垒层250和一掺杂或非掺杂GaN盖帽层260，最后制作器件源、漏欧姆接触电极和栅电极(图2中未标出)。
实施例二
本实施例提供一个氮化镓基高电子迁移率晶体管，在SiC或Si衬底上生长一层AlN成核层，再生长缓冲层，随后生长沟道层，然后生长一Si掺杂浓度为2×1019cm-3的AlGaN势垒层和一掺杂或非掺杂GaN盖帽层，最后制作器件源、漏欧姆接触电极和栅电极。
以上所述，仅为本发明中的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉该技术的人在本发明所揭露的技术范围内，可轻易想到的变换或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求书的保护范围为准。

Claims (4)

1.一种氮化镓基高电子迁移率晶体管外延结构的制造方法，其特征在于，在SiC或Si衬底上依次生长完AlN成核层、AlGaN缓冲层、GaN沟道层后，再生长Si掺杂AlGaN势垒层，最后生长GaN盖帽层。
2.根据权利要求1所述的一种氮化镓基高电子迁移率晶体管外延结构的制造方法，其特征在于，所述Si掺杂AlGaN势垒层中Si掺杂的浓度为1×1017cm-3-2×1019cm-3。
3.一种氮化镓基高电子迁移率晶体管外延结构，其特征在于，所述氮化镓基高电子迁移率晶体管外延结构中包括SiC或Si衬底层，在该衬底层上从下至上依次形成AlN成核层、AlGaN缓冲层、GaN沟道层、AlGaN势垒层和GaN盖帽层，所述AlGaN势垒层为Si掺杂AlGaN势垒层。
4.根据权利要求3所述的一种氮化镓基高电子迁移率晶体管外延结构，其特征在于，所述Si掺杂AlGaN势垒层中Si掺杂的浓度为1×1017cm-3-2×1019cm-3。
CN201510757512.7A 2015-11-09 2015-11-09 氮化镓基高电子迁移率晶体管外延结构及其制造方法 Pending CN105322009A (zh)

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Cited By (5)

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CN107230621A (zh) * 2016-03-25 2017-10-03 北京大学 氮化镓晶体管的制造方法
CN107946358A (zh) * 2017-11-21 2018-04-20 华南理工大学 一种与Si‑CMOS工艺兼容的AlGaN/GaN异质结HEMT器件及其制作方法
CN108346687A (zh) * 2018-01-03 2018-07-31 东南大学 一种氮化镓基高电子迁移率晶体管
WO2019095923A1 (zh) * 2017-11-14 2019-05-23 厦门市三安集成电路有限公司 一种覆盖纳米柱势垒的GaN晶体管及其制备方法
CN111244163A (zh) * 2019-12-11 2020-06-05 叶顺闵 一种应用有新型氮化铝铟势垒层的高电子迁移率晶体管

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* Cited by examiner, † Cited by third party
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CN107230621A (zh) * 2016-03-25 2017-10-03 北京大学 氮化镓晶体管的制造方法
WO2019095923A1 (zh) * 2017-11-14 2019-05-23 厦门市三安集成电路有限公司 一种覆盖纳米柱势垒的GaN晶体管及其制备方法
CN107946358A (zh) * 2017-11-21 2018-04-20 华南理工大学 一种与Si‑CMOS工艺兼容的AlGaN/GaN异质结HEMT器件及其制作方法
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CN108346687B (zh) * 2018-01-03 2021-02-09 东南大学 一种氮化镓基高电子迁移率晶体管
CN111244163A (zh) * 2019-12-11 2020-06-05 叶顺闵 一种应用有新型氮化铝铟势垒层的高电子迁移率晶体管

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