CN105428254A - 叠层封装方法 - Google Patents

叠层封装方法 Download PDF

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Publication number
CN105428254A
CN105428254A CN201510977315.6A CN201510977315A CN105428254A CN 105428254 A CN105428254 A CN 105428254A CN 201510977315 A CN201510977315 A CN 201510977315A CN 105428254 A CN105428254 A CN 105428254A
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chip
package
salient point
substrate
mode
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沈海军
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Nantong Fujitsu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15322—Connection portion the connection portion being formed on the die mounting surface of the substrate being a pin array, e.g. PGA

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本申请公开了一种叠层封装方法，包括以下步骤：以倒装贴装的方式将设置有凸点的第一芯片贴装到基板上；在所述基板上形成塑封层，所述塑封层包覆所述第一芯片及所述凸点；对所述塑封层及所述第一芯片进行研磨，直至所述凸点的顶部露出所述塑封层。本申请提供的叠层封装方法，通过将封料层及第一芯片研磨掉来使凸点的顶部露出封料层，而不需要通过激光打孔的方式来使凸点露出封料层，因此克服了采用激光打孔方式时出现的孔径一致性差、凸点露出高度不稳定、钻孔位置容易偏移的问题。采用本申请方法可以实现更小节距的凸点制作。

Description

叠层封装方法
技术领域
本申请一般涉及半导体封装技术领域，尤其涉及叠层封装方法。
背景技术
传统的POP(PackageOnPackage；叠层封装)封装中，底层产品部分的制作流程是：在基板的正面植上凸点(通常是焊球)，然后再塑封，且塑封体完全覆盖凸点，随后再通过激光打孔的方式，在凸点对应的位置将塑封体击穿，使凸点露出塑封体。
采用上述方式存在孔径一致性差、凸点露出高度不稳定、钻孔位置容易偏移的问题。
发明内容
鉴于现有技术中的上述缺陷或不足，期望提供一种叠层封装方法，用以解决现有技术中存在的孔径一致性差、凸点露出高度不稳定、钻孔位置容易偏移的问题。
本申请提供一种叠层封装方法，包括以下步骤：
以倒装贴装的方式将设置有凸点的第一芯片贴装到基板上；
在所述基板上形成塑封层，所述塑封层包覆所述第一芯片及所述凸点；
对所述塑封层及所述第一芯片进行研磨，直至所述凸点的顶部露出所述塑封层。
本申请提供的叠层封装方法，通过将封料层及第一芯片研磨掉来使凸点的顶部露出封料层，而不需要通过激光打孔的方式来使凸点露出封料层，因此克服了采用激光打孔方式时出现的孔径一致性差、凸点露出高度不稳定、钻孔位置容易偏移的问题。采用本申请方法可以实现更小节距的凸点制作。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1为本发明实施例一提供的叠层封装方法的流程图；
图2为第一芯片贴装于基板之前的结构示意图；
图3为第一芯片贴装于基板上之后的结构示意图；
图4为将第一芯片塑封于基板上之后的结构示意图；
图5为对第一芯片及塑封层顶面进行研磨的结构示意图；
图6为研磨后凸点露出塑封层后的结构示意图；
图7为本发明实施例二提供的叠层封装方法的流程图；
图8为本发明实施例三提供的叠层封装方法的流程图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
请参考图1所述，本发明实施例一提供的叠层封装方法，包括以下步骤：
S10：以倒装贴装的方式将设置有凸点的第一芯片贴装到基板上；
如图2、3所示，第一芯片1上预先制作好凸点2，该凸点2可以是铜柱，将第一芯片1和凸点2作为一个整体，采用倒装贴装的方式连接到基板5的正面，凸点2的设置位置与基板5上对应的电连接位置相对应。
S20：在所述基板上形成塑封层，所述塑封层包覆所述第一芯片及所述凸点；
如图4所示，将第一芯片1和凸点2作为一个整体贴装到基板5上之后，在基板上形成塑封层6，塑封层6完全覆盖第一芯片5和凸点2，塑封层6一方面起到固定的作用，另一方面实现了器件之间的绝缘。
S30：对所述塑封层及所述第一芯片进行研磨，直至所述凸点的顶部露出所述塑封层。
如图5、6所示，通过磨轮7从塑封层6的顶面开始向下研磨，将塑封层6的顶部及第一芯片1研磨掉，直至凸点2的顶部露出塑封层6。
进一步地，如图7所示，该实施例与实施例一的不同在于，在以倒装贴装的方式将设置有凸点的第一芯片贴装到基板上之前，还包括：
S101：以倒装贴装的方式在所述基板上贴装第二芯片。
进一步地，如图8所示，该实施例与实施例二的不同在于，在以倒装贴装的方式在基板上贴装第二芯片之后，还包括：
S102：在第二芯片与基板之间形成封料层。
另可参见图2-6，可以通过在第一芯片与基板之间填充胶水，以形成封料层4。
本申请提供的叠层封装方法，通过将封料层及第一芯片研磨掉来使凸点的顶部露出封料层，而不需要通过激光打孔的方式来使凸点露出封料层，因此克服了采用激光打孔方式时出现的孔径一致性差、凸点露出高度不稳定、钻孔位置容易偏移的问题。采用本申请方法可以实现更小节距的凸点制作。
进一步地，第一芯片覆盖于第二芯片的上方，这样来构成层叠的封装形式。
进一步地，凸点2的顶面高于第二芯片3的顶面。以防止在研磨的过程中损伤到第二芯片3。
进一步地，凸点2分布于第二芯片3的外侧。
本文中所涉及的第一芯片及第二芯片可以是一个也可以是多个，上述实施例中仅示出了一个第一芯片及一个第二芯片的情况。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (6)

1.一种叠层封装方法，其特征在于，包括以下步骤：
以倒装贴装的方式将设置有凸点的第一芯片贴装到基板上；
在所述基板上形成塑封层，所述塑封层包覆所述第一芯片及所述凸点；
对所述塑封层及所述第一芯片进行研磨，直至所述凸点的顶部露出所述塑封层。
2.根据权利要求1所述的叠层封装方法，其特征在于，在所述以倒装贴装的方式将设置有凸点的第一芯片贴装到基板上之前，还包括：
以倒装贴装的方式在所述基板上贴装第二芯片。
3.根据权利要求2所述的叠层封装方法，其特征在于，在所述以倒装贴装的方式在所述基板上贴装第二芯片之后，还包括：在所述第二芯片与所述基板之间形成封料层。
4.根据权利要求2或3所述的叠层封装方法，其特征在于，所述第一芯片覆盖于所述第二芯片的上方。
5.根据权利要求4所述的叠层封装方法，其特征在于，所述凸点的顶面高于所述第二芯片的顶面。
6.根据权利要求5所述的叠层封装方法，其特征在于，所述凸点分布于所述第二芯片的外侧。
CN201510977315.6A 2015-12-23 2015-12-23 叠层封装方法 Pending CN105428254A (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101266967A (zh) * 2008-05-04 2008-09-17 日月光半导体制造股份有限公司 堆叠式芯片封装结构及其制作方法
US20110256664A1 (en) * 2009-06-19 2011-10-20 Reza Argenty Pagaila Integrated circuit packaging system with mountable inward and outward interconnects and method of manufacture thereof
CN102543939A (zh) * 2012-01-05 2012-07-04 三星半导体(中国)研究开发有限公司 超细间距焊盘的叠层倒装芯片封装结构及其制造方法
CN203055899U (zh) * 2012-12-12 2013-07-10 华天科技（西安）有限公司 一种带有铜柱的晶圆减薄的单芯片封装件
CN104103595A (zh) * 2014-07-15 2014-10-15 南通富士通微电子股份有限公司 Pop封装方法
CN104658933A (zh) * 2014-12-30 2015-05-27 华天科技（西安）有限公司 一种运用贴膜工艺的pop封装结构及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101266967A (zh) * 2008-05-04 2008-09-17 日月光半导体制造股份有限公司 堆叠式芯片封装结构及其制作方法
US20110256664A1 (en) * 2009-06-19 2011-10-20 Reza Argenty Pagaila Integrated circuit packaging system with mountable inward and outward interconnects and method of manufacture thereof
CN102543939A (zh) * 2012-01-05 2012-07-04 三星半导体(中国)研究开发有限公司 超细间距焊盘的叠层倒装芯片封装结构及其制造方法
CN203055899U (zh) * 2012-12-12 2013-07-10 华天科技（西安）有限公司 一种带有铜柱的晶圆减薄的单芯片封装件
CN104103595A (zh) * 2014-07-15 2014-10-15 南通富士通微电子股份有限公司 Pop封装方法
CN104658933A (zh) * 2014-12-30 2015-05-27 华天科技（西安）有限公司 一种运用贴膜工艺的pop封装结构及其制备方法

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