CN105405777B - 一种大面积平行堆栈式封装结构和封装方法 - Google Patents
一种大面积平行堆栈式封装结构和封装方法 Download PDFInfo
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- CN105405777B CN105405777B CN201510982782.8A CN201510982782A CN105405777B CN 105405777 B CN105405777 B CN 105405777B CN 201510982782 A CN201510982782 A CN 201510982782A CN 105405777 B CN105405777 B CN 105405777B
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 105
- 238000007789 sealing Methods 0.000 claims abstract description 59
- 239000000084 colloidal system Substances 0.000 claims description 22
- 239000003292 glue Substances 0.000 claims description 14
- 238000001723 curing Methods 0.000 claims description 9
- 238000001514 detection method Methods 0.000 claims description 7
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000013007 heat curing Methods 0.000 claims description 6
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- 239000004065 semiconductor Substances 0.000 abstract description 6
- 238000002360 preparation method Methods 0.000 abstract description 3
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- 239000000047 product Substances 0.000 description 30
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- 239000000919 ceramic Substances 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
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- 239000002356 single layer Substances 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
Description
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510982782.8A CN105405777B (zh) | 2015-12-24 | 2015-12-24 | 一种大面积平行堆栈式封装结构和封装方法 |
Applications Claiming Priority (1)
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---|---|---|---|
CN201510982782.8A CN105405777B (zh) | 2015-12-24 | 2015-12-24 | 一种大面积平行堆栈式封装结构和封装方法 |
Publications (2)
Publication Number | Publication Date |
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CN105405777A CN105405777A (zh) | 2016-03-16 |
CN105405777B true CN105405777B (zh) | 2018-07-13 |
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Family Applications (1)
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CN201510982782.8A Active CN105405777B (zh) | 2015-12-24 | 2015-12-24 | 一种大面积平行堆栈式封装结构和封装方法 |
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CN (1) | CN105405777B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107808888B (zh) * | 2017-10-25 | 2020-12-01 | 积高电子(无锡)有限公司 | 一种cmos图像传感器的封装工艺 |
CN108734156B (zh) * | 2018-07-27 | 2023-08-15 | 星科金朋半导体(江阴)有限公司 | 一种超薄指纹识别芯片的封装方法及其封装结构 |
CN108734154B (zh) * | 2018-07-27 | 2023-08-15 | 星科金朋半导体(江阴)有限公司 | 一种超薄指纹识别芯片的封装方法及其封装结构 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007042773A (ja) * | 2005-08-02 | 2007-02-15 | Canon Inc | 光学センサ及びその製造方法 |
TW201312782A (zh) * | 2011-09-02 | 2013-03-16 | Lite On Singapore Pte Ltd | 整合式感測封裝結構 |
CN103299408A (zh) * | 2011-01-07 | 2013-09-11 | 株式会社村田制作所 | 电子元器件模块的制造方法及电子元器件模块 |
CN105023851A (zh) * | 2014-04-28 | 2015-11-04 | 环旭电子股份有限公司 | 电子封装模块的制造方法 |
CN205303419U (zh) * | 2015-12-24 | 2016-06-08 | 上海源模微电子有限公司 | 一种大面积平行堆栈式封装结构 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080061425A1 (en) * | 2006-09-13 | 2008-03-13 | United Microdisplay Optronics Corp. | Chip package structure and fabricating method thereof |
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2015
- 2015-12-24 CN CN201510982782.8A patent/CN105405777B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007042773A (ja) * | 2005-08-02 | 2007-02-15 | Canon Inc | 光学センサ及びその製造方法 |
CN103299408A (zh) * | 2011-01-07 | 2013-09-11 | 株式会社村田制作所 | 电子元器件模块的制造方法及电子元器件模块 |
TW201312782A (zh) * | 2011-09-02 | 2013-03-16 | Lite On Singapore Pte Ltd | 整合式感測封裝結構 |
CN105023851A (zh) * | 2014-04-28 | 2015-11-04 | 环旭电子股份有限公司 | 电子封装模块的制造方法 |
CN205303419U (zh) * | 2015-12-24 | 2016-06-08 | 上海源模微电子有限公司 | 一种大面积平行堆栈式封装结构 |
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CN105405777A (zh) | 2016-03-16 |
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Denomination of invention: Large-area parallel stacking type packaging structure and packaging method Effective date of registration: 20190919 Granted publication date: 20180713 Pledgee: Bank of Nanjing Jiangbei District branch of Limited by Share Ltd. Pledgor: Nanjing Huigan Electronic Technology Co.,Ltd. Registration number: Y2019320000144 |
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Date of cancellation: 20220223 Granted publication date: 20180713 Pledgee: Bank of Nanjing Jiangbei District branch of Limited by Share Ltd. Pledgor: Nanjing Huigan Electronic Technology Co.,Ltd. Registration number: Y2019320000144 |
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Denomination of invention: A large area parallel stack packaging structure and packaging method Effective date of registration: 20220228 Granted publication date: 20180713 Pledgee: Bank of Nanjing Jiangbei District branch of Limited by Share Ltd. Pledgor: Nanjing Huigan Electronic Technology Co.,Ltd. Registration number: Y2022320000087 |
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Denomination of invention: A Large Area Parallel Stacked Packaging Structure and Packaging Method Effective date of registration: 20231229 Granted publication date: 20180713 Pledgee: Bank of Nanjing Jiangbei District branch of Limited by Share Ltd. Pledgor: Nanjing Huigan Electronic Technology Co.,Ltd. Registration number: Y2023980075543 |