CN105242097B - 薄晶片电流传感器 - Google Patents
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Abstract
本发明涉及薄晶片电流传感器。实施例涉及使用薄晶片制造工艺制造的IC电流传感器。这样的技术可以包括其中利用研磨前划片(DBG)的处理,这可以改进可靠性并且使应力效应最小化。尽管实施例利用面朝上安装,但是在其他实施例中通过过孔接触而使面朝下安装是可能的。IC电流传感器实施例可以在使常常与传统的IC电流传感器相关联的缺陷最小化的同时呈现许多优点。
Description
本发明是于2011年8月31日提交的、申请号为“2011102543935”、发明名称为“薄晶片电流传感器”的分案申请。
技术领域
本发明通常涉及集成电路(IC)电流传感器并且更具体地涉及根据薄晶片制造工艺制造的IC电流传感器。
背景技术
流电(galvanically)隔离集成电路(IC)电流传感器的期望性质包括高磁灵敏度;高机械稳定性和可靠性;对芯片边界附近的霍尔(Hall)传感器元件的低应力影响;高热均匀性和低热梯度;高隔离电压;以及低制造成本。传统的电流传感器可以包括一个或多个旨在应对这些期望性质的特征或者以旨在应对这些期望性质的方式制造。
例如,一些电流传感器使用引线框作为电流引线。其他电流传感器还包括磁芯。然而,这样的传感器可能制造昂贵。
其他电流传感器包括额外的层,诸如硅管芯顶部上的特殊磁层或者在隔离层上形成的厚金属层。这些传感器也是昂贵的,并且前者可能对干扰场敏感并且可能受到与IC外部的电流引线的定位相关的缺陷的困扰。
因此,需要一种在使缺陷最小化的同时具有期望性质的流电隔离IC电流传感器。
发明内容
在一个实施例中,一种薄晶片集成电路电流传感器包括:电流导体;薄晶片半导体芯片,基本上没有从芯片边缘向内超过约10微米(μm)的划片缺陷;至少一个磁场感测元件,布置在薄晶片半导体芯片的表面上;以及隔离层,位于电流导体和薄晶片半导体芯片之间。
在一个实施例中,一种方法包括:从第一面划片小于硅晶片的整个厚度;将叠层带施加到硅晶片的第一面;对硅晶片的第二面进行背研磨;将划片带施加到硅晶片的第二面;移除叠层带;对硅晶片进行过刻蚀;对半导体晶片的半导体芯片进行分割;以及利用至少一个分割的半导体芯片形成磁场电流传感器。
在一个实施例中,一种薄晶片集成电路电流传感器包括:电流导体;薄晶片半导体芯片,具有至少一个过刻蚀的研磨前划片(DBG)边缘,该至少一个边缘包括从该至少一个边缘向内延伸约10微米(μm)的缺陷区域;至少一个磁场感测元件,布置在薄晶片半导体芯片上;以及隔离层,位于电流导体和薄晶片半导体芯片之间。
附图说明
考虑到结合附图的本发明的各种实施例的下面详细描述,可以更完整地理解本发明,其中:
图1示出了根据实施例的传感器的框图;
图2A示出了根据实施例的研磨前划片工艺的流程图;
图2B示出了根据实施例的研磨前划片工艺的流程图;
图3示出了根据实施例的晶片图像;
图4示出了根据实施例的传感器的框图;
图5示出了根据实施例的传感器的框图;
图6示出了根据实施例的传感器的框图。
尽管本发明经得起各种修改和替选形式的检验,但是其细节在附图中作为示例被示出并且将被详细描述。然而,应当理解,意图并非是使本发明限于所描述的特定实施例。相反,意图是涵盖落在如所附权利要求限定的本发明的精神和范围内的所有修改、等价物和替选方案。
具体实施方式
实施例涉及使用薄晶片制造工艺制造的IC电流传感器。这样的技术可以包括其中利用研磨前划片(DBG)的处理,这可以改进可靠性并且使应力效应最小化。尽管实施例利用面朝上安装(face-up mounting),但是通过针对与隔离层耦合的芯片表面的过孔(viathrough)接触或者其他接触,在其他实施例中使面朝下(face-down)安装是可能的。IC电流传感器实施例可以在使常常与传统的IC电流传感器相关联的缺陷最小化的同时呈现许多优点。
参照图1,IC电流传感器100的实施例包括电流导体102、在电流导体上形成的隔离层104、以及通过接合线110耦合到信号引脚108的薄晶片芯片106。在一个实施例中,薄晶片芯片106是根据薄晶片制造工艺制造的,该工艺可以包括晶片的研磨前划片以及可选的背面刻蚀并且将在下面更详细地讨论。
磁传感器元件112,诸如一个实施例中的霍尔效应元件,被布置在薄晶片芯片106的表面上。在一个实施例中,电流导体102包括一个或多个槽114,其可以有助于限定通过电流导体102的电流流动路径。当传感器元件102相对槽114定位时,每个槽114可以在策略上使电流流动线路集中以使每个传感器元件112附近的磁场最大化。申请人还引用共同所有的美国专利申请第12/630,596、12/711,471和12/756,652号,它们的整体内容通过引用合并于此。
利用薄晶片工艺,薄晶片芯片106可以具有比200 μm小得多的厚度,诸如在实施例中为约50 μm或更小或甚至约20 μm或更小。这样的厚度比传统的厚晶片的厚度小得多,减少了传感器元件112和电流导体102之间的竖直(相对于纸面上的图1的取向)距离d。这可以通过避免由于芯片厚度d与边缘距离e的较小比引起的应力效应来改进传感器100的精度。例如,在薄晶片制造实施例中,e可以是约75 μm并且d在约25 μm至约65 μm的范围内。尽管所有芯片经历某种程度的应力,但是跨越芯片的均匀应力好过具有不均匀应力的区域。在实施例中,不均匀区域出现在芯片100的边缘附近。因而,边缘距离e是临界应力距离,特别地如果e小于d的话。通过由于较薄的晶片而把传感器元件112定位为较接近边缘,芯片106的更多区域是均匀的而非不均匀的,因为距离e不是较小的也不与芯片厚度d相当。此外,期望的是将传感器元件112定位在槽114附近但是还使槽114在不增加芯片尺寸的情况下彼此隔开较远。因而,由于更均匀的应力以及更均匀的应力所呈现的相关定位优点,传感器100实现了芯片空间的更高效使用。再者,较小距离d的显著优点是鉴于传感器元件112和流过电流导体102的电流之间的较小距离的、传感器100的增加灵敏度。此外,与电流导体102的厚度相比芯片106的较小厚度可以提供更均匀的和/或更小的温度梯度和芯片上的电路的更好补偿、以及更高的精度。薄晶片制造还提供了芯片106的更清洁的、更平滑的边缘,具有更少的碎屑(chip)和其他缺陷以及以后显现的断裂,这可能影响可靠性、增加应力并且以其他形式减少传感器100的寿命性能。
参照图2A,图示了薄晶片制造工艺200的实施例。在202处,对硅晶片部分地(诸如在一个实施例中半切割(half-cut))划片。在204处,在206处进行背研磨以使晶片变薄之前将叠层带施加到硅晶片的一个面。在208处,在没有叠层带的面上,将划片带施加到晶片,随后在210处从晶片移除划片带。随后在212处执行过刻蚀工艺。
在图2B中示出了另一实施例。工艺201图示了206处的背研磨和208处的框或带安装之间的额外的等离子体刻蚀207。
与其他制造工艺相比,薄晶片工艺200包括研磨前划片,即202在206之前。此外,与锯穿晶片的整个厚度的传统工艺相比,202处的划片是部分切割划片。如工艺200中的研磨前划片导致了具有更平滑的边缘、没有与其他方法相关联的碎屑、断裂和其他缺陷的薄晶片。这可以在图3中看到,其示出了标准工艺(左侧)以及使用研磨前划片和等离子体刻蚀的薄晶片工艺(右侧)的图像。在标准工艺的晶片图像中,在锯条切穿硅晶片时由锯条引起的碎屑和断裂从锯切缝隙延伸到晶片中约40 μm。
相比而言,研磨前划片的晶片图像示出了仅从锯切缝隙延伸到晶片的边缘中约10μm或更小的碎屑。通常,电流传感器对由改变感测元件的灵敏度的压电效应引起的应力极为敏感,比其他传感器更是如此。尽管期望薄管芯,但是薄管芯具有应力挑战。使用过刻蚀作为研磨前划片薄晶片工艺的一部分进一步净化(refine)和改进芯片边缘,使得薄晶片适于用在电流传感器中。
在图4中示出了薄晶片电流传感器400的另一实施例。传感器400与传感器100相似,但是在薄晶片芯片表面106的顶部上安装到印刷电路板(PCB)416。PCB 416包括PCB 416的底面上的铜迹线418,并且焊接凸点420使薄晶片芯片表面106与PCB 416的迹线418耦合。
在图5中,薄晶片电流传感器500通过过孔(via through-hole)522面朝下安装到PCB 516的铜迹线518。如这里讨论的薄晶片制造工艺的实施例可以容易地适应通孔522,并且由于实施例允许从管芯的后面形成接触,因此过孔522不需要如传统的面朝下安装中的那样使导体小于管芯。因此,由于因芯片506的面朝下安装导致的传感器元件512和电流导体502之间的较小距离d2,所以传感器500可以具有增加的磁场信号。传感器元件512在这里被示出为布置在薄晶片芯片506的底表面上。
在图6中示出的另一面朝下安装实施例中,薄晶片电流传感器600包括通过接合线610与信号引脚608耦合的过孔622。与图5的传感器500相似,由于传感器元件612和电流导体602之间的较小距离d2,传感器600可以提供增加的磁场信号。
在另一实施例中,薄晶片半导体芯片耦合到包括例如玻璃或陶瓷的载体或信号传导层。该载体层基本上比薄晶片半导体芯片厚,诸如至少两倍厚。
这里已描述了系统、器件和方法的各种实施例。这些实施例仅被给出作为示例,并非意图限制本发明的范围。而且,应当认识到,已描述的实施例的各种特征可以以各种方式组合以产生许多额外的实施例。而且,尽管已描述了用于与所公开的实施例一起使用的各种材料、尺寸、形状、注入位置等,但是在不超出本发明的范围的情况下可以利用除了所公开的那些以外的其他事物。
相关领域的普通技术人员将认识到,本发明可以包括比上面描述的任何单独实施例中说明的少的特征。这里描述的实施例并非意味着穷举呈现可以组合本发明的各种特征的方式。因此,实施例不是相互排斥的特征组合;相反,如本领域的普通技术人员所理解的,本发明可以包括选自不同单独实施例的不同单独特征的组合。
上面通过引用对文献的任何并入受到限制,使得不会并入与此处的明确公开内容相左的主题内容。上面通过引用对文献的任何并入进一步受到限制,使得这些文献中包括的权利要求不会通过引用并入此处。此外,上面通过引用对文献的任何并入进一步受到限制,使得这些文献中提供的任何定义不会通过引用并入此处,除非这里明确包括。
出于解释本发明的权利要求的目的,明确的是,除非在权利要求中记载特定术语“用于…的装置”或者“用于…的步骤”,否则不要援引35 U.S.C.的第六段第112节的规定。
Claims (18)
1.一种用于制造磁场电流传感器的方法,包括:
从第一面划片出小于硅晶片的整个厚度的厚度;
将叠层带施加到所述硅晶片的所述第一面;
对所述硅晶片的第二面进行背研磨;
等离子体刻蚀所述硅晶片的第二面;
将划片带施加到所述硅晶片的所述第二面;
移除所述叠层带;
对所述硅晶片进行过刻蚀;
对所述硅晶片的半导体芯片进行分割;以及
利用至少一个分割的半导体芯片来形成所述磁场电流传感器,
其中形成磁场电流传感器包括:
在电流导体上提供隔离层;
在所述隔离层上提供至少一个分割的半导体芯片;以及
以离开芯片边缘的临界应力距离将至少一个磁场感测元件布置在所述至少一个半导体芯片的表面上。
2.根据权利要求1所述的方法,其中从第一面划片出小于硅晶片的整个厚度的厚度包括从所述第一面对所述硅晶片进行半切割划片。
3.根据权利要求1所述的方法,其中对所述硅晶片的第二面进行背研磨使所述硅晶片变薄并且分割所述硅晶片。
4.根据权利要求1所述的方法,其中所述划片在所述背研磨之前发生。
5.根据权利要求4所述的方法,其中背研磨之前的划片以及过刻蚀提供了分割的半导体芯片,所述半导体芯片从所述半导体芯片的边缘起超过10微米(μm)没有缺陷。
6.根据权利要求1所述的方法,进一步包括形成所述电流导体以包括至少一个磁场集中槽。
7.根据权利要求6所述的方法,其中在所述隔离层上提供所述至少一个分割的半导体芯片包括将所述至少一个分割的半导体芯片布置为使得至少一个磁场感测元件接近至少一个磁场集中槽的末端。
8.一种用于制造磁场电流传感器的方法,包括:
从第一面划片出小于硅晶片的整个厚度的厚度;
对所述硅晶片的第二面进行背研磨;以及
由所述硅晶片的分割的半导体芯片形成所述磁场电流传感器,其中形成所述磁场电流传感器包括:
在电流导体上提供隔离层;
在所述隔离层上提供所述分割的半导体芯片;以及
以离开芯片边缘的临界应力距离将至少一个磁场感测元件布置在所述半导体芯片的表面上。
9.根据权利要求8所述的方法,其中所述划片在所述背研磨之前执行。
10.根据权利要求9所述的方法,进一步包括对所述硅晶片进行过刻蚀。
11.根据权利要求10所述的方法,其中所述划片在所述过刻蚀之前被执行,并且其中执行背研磨之前的划片以及过刻蚀提供了所述硅晶片的分割的半导体芯片,所述半导体芯片从所述半导体芯片的边缘起超过10微米(μm)没有缺陷。
12.根据权利要求8所述的方法,进一步包括:
将第一带施加到所述硅晶片的所述第一面。
13.根据权利要求12所述的方法,其中所述第一带包括叠层带。
14.根据权利要求12所述的方法,进一步包括:
将第二带施加到所述硅晶片的所述第二面;
从所述第一面移除所述第一带;以及
对所述硅晶片的半导体芯片进行分割,其中所述半导体芯片被用于形成所述磁场电流传感器。
15.根据权利要求14所述的方法,其中所述第二带包括划片带。
16.根据权利要求14所述的方法,其中对所述硅晶片的第二面进行背研磨使所述硅晶片变薄并且分割所述硅晶片。
17.根据权利要求8所述的方法,其中从第一面划片出小于硅晶片的整个厚度的厚度包括从所述第一面对所述硅晶片进行半切割划片。
18.根据权利要求8所述的方法,进一步包括形成所述电流导体以包括至少一个磁场集中槽。
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CN102401851A (zh) | 2012-04-04 |
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US8283742B2 (en) | 2012-10-09 |
US9029966B2 (en) | 2015-05-12 |
US8679895B2 (en) | 2014-03-25 |
CN102401851B (zh) | 2016-09-21 |
US20140183534A1 (en) | 2014-07-03 |
DE102011081474A1 (de) | 2012-03-01 |
US20120049304A1 (en) | 2012-03-01 |
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