CN105229775B - 形成衬底开口的方法 - Google Patents

形成衬底开口的方法 Download PDF

Info

Publication number
CN105229775B
CN105229775B CN201480028217.1A CN201480028217A CN105229775B CN 105229775 B CN105229775 B CN 105229775B CN 201480028217 A CN201480028217 A CN 201480028217A CN 105229775 B CN105229775 B CN 105229775B
Authority
CN
China
Prior art keywords
substrate
etching
wall
section
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201480028217.1A
Other languages
English (en)
Other versions
CN105229775A (zh
Inventor
马克·基尔鲍赫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN105229775A publication Critical patent/CN105229775A/zh
Application granted granted Critical
Publication of CN105229775B publication Critical patent/CN105229775B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B44DECORATIVE ARTS
    • B44CPRODUCING DECORATIVE EFFECTS; MOSAICS; TARSIA WORK; PAPERHANGING
    • B44C1/00Processes, not specifically provided for elsewhere, for producing decorative surface effects
    • B44C1/22Removing surface-material, e.g. by engraving, by etching
    • B44C1/227Removing surface-material, e.g. by engraving, by etching by etching
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00103Structures having a predefined profile, e.g. sloped or rounded grooves
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523Etching material
    • B81C1/00531Dry etching
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/136Integrated optical circuits characterised by the manufacturing method by etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00Basic microelectromechanical structures
    • B81B2203/03Static structures
    • B81B2203/0315Cavities
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00Basic microelectromechanical structures
    • B81B2203/03Static structures
    • B81B2203/0323Grooves
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00Basic microelectromechanical structures
    • B81B2203/03Static structures
    • B81B2203/0323Grooves
    • B81B2203/033Trenches
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00Basic microelectromechanical structures
    • B81B2203/03Static structures
    • B81B2203/0323Grooves
    • B81B2203/0338Channels
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00Basic microelectromechanical structures
    • B81B2203/03Static structures
    • B81B2203/0353Holes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mechanical Engineering (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Re-Forming, After-Treatment, Cutting And Transporting Of Glass Products (AREA)

Abstract

本发明涉及一种形成衬底开口的方法,所述方法包含在衬底中形成多个并排开口。紧邻并排开口中的至少一些开口在所述衬底中形成到相对于彼此不同的深度。移除横向介于所述并排开口之间的壁以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于所述经移除壁通过所述侧壁表面。

Description

形成衬底开口的方法
技术领域
本文中所揭示的实施例涉及在衬底中形成开口的方法。
背景技术
集成电路通常形成于例如硅晶片或其它半导电材料的半导体衬底上。一般来说,为半导电、导电或电绝缘的各种材料层用以形成集成电路。以实例的方式,各种材料可使用各种过程经掺杂、离子植入、沉积、蚀刻、生长等。半导电处理的持续目标是减小个别电子组件的大小,借此实现较小及较密集的集成电路。
用于图案化及处理半导体衬底的一种技术是光刻。此可包含可图案化掩蔽层在下伏衬底材料上方的沉积。所述掩蔽层可经图案化以形成具有期望形状及配置的穿过其的开口。所述下伏衬底材料可经由掩蔽材料中的开口(例如,通过离子植入、蚀刻等)经处理以在下伏衬底材料中产生具有或近似掩蔽层中的图案的所期望改变。可使用的掩蔽层可称为抗蚀剂,其中光学光刻中所使用的光致抗蚀剂是一个实例。在特定例子中,使用光致抗蚀剂及/或光致抗蚀剂与硬掩蔽及其它材料的组合的多个不同层。此外,图案可在不使用抗蚀剂或光致抗蚀剂的情况下形成于衬底上。
附图说明
图1是根据本发明的实施例的过程中的衬底片段的图解性俯视平面图。
图2是穿过图1中的线2-2截取的横截面图。
图3是穿过图1中的线3-3截取的横截面图。
图4是处于在由图1所展示的步骤之后的处理步骤处的图1衬底的视图。
图5是穿过图4中的线5-5截取的横截面图。
图6是穿过图4中的线6-6截取的横截面图。
图7是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图8是处于在由图7所展示的步骤之后的处理步骤处的图7衬底的视图。
图9是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图10是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图11是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图12是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图13是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图14是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图15是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图16是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图17是根据本发明的实施例的过程中的替代衬底片段的图解性俯视平面图。
图18是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
图19是根据本发明的实施例的过程中的替代衬底片段的图解性俯视平面图。
图20是穿过图19中的线20-20截取的横截面图。
图21是穿过图19中的线21-21截取的横截面图。
图22是处于在由图19所展示的步骤之后的处理步骤处的图19衬底的视图。
图23是穿过图22中的线23-23截取的横截面图。
图24是穿过图22中的线24-24截取的横截面图。
图25是根据本发明的实施例的过程中的替代衬底片段的图解性横截面图。
具体实施方式
参考图1到6描述形成衬底开口的方法的初始实例性实施例。可在制作集成电路时及/或在制作其它结构时使用根据本发明的方法。参考图1到3,衬底片段10包括其中已形成多个并排开口12、13、14、15、16、17、18的衬底20。在一个实施例中,衬底10是半导体衬底。在本文件的上下文中,术语“半导体衬底”或“半导电衬底”经定义以意指包括半导电材料的任一构造,所述半导电材料包含但不限于块体半导电材料(例如,半导电晶片)(单独地或在包括其上的其它材料的组合件中)及半导电材料层(单独地或在包括其它材料的组合件中)。术语“衬底”是指包含但不限于上文所描述的半导电衬底的任何支撑结构。衬底10可包含电介质材料及/或导电材料,且不管怎样不需要为半导电衬底。作为另一实例,衬底10可包括(举例来说)供在制作LED及/或其它装置时使用的蓝宝石。
衬底20的材料可为均质或非均质的。本文中所描述的材料及/或结构中的任一者可为均质或非均质的,且不管怎样可在此类材料所上覆的任何材料上方为连续或不连续的。进一步除非另外陈述,否则使用任何适合或尚待开发的技术形成每一材料,其中原子层沉积、化学气相沉积、物理气相沉积、外延生长、扩散掺杂及离子植入是实例。集成电路的其它部分或完全制作的组件可形成为衬底20的所描绘材料的一部分或竖立在衬底20的所描绘材料里面,且与本文中所揭示的本发明关系并非特别密切。
衬底20展示为包括七个并排开口12到18,但可使用更多或更少的开口。不管怎样,并排开口中的紧邻开口中的至少一些开口在衬底20中形成到相对于彼此不同的深度。壁21横向介于并排开口12到18之间。开口12到18中的紧邻开口可彼此相等地间隔开(如所展示)借此壁21统一地为相同横向宽度。替代地作为实例,紧邻开口可包含相对于彼此的多个间距(未展示),借此壁21统一地具有至少两个不同横向宽度(即,至少在衬底20的竖直最外表面处)。壁21展示为垂直延伸且具有恒定横向宽度。可使用其它壁构造。在此文件中,“水平”是指沿着在制作期间相对于其处理衬底的主要表面的大体方向,且“垂直”是大体正交于其的方向。进一步如本文中所使用,“垂直”及“水平”是在三维空间中独立于衬底的定向的相对于彼此大体垂直方向。进一步在此文件中,“竖直”及“竖直地”通常参考垂直方向。
在一个实施例中,开口12到18是使用等离子蚀刻形成,且在一个实施例中仅使用单个掩蔽步骤来形成开口12到18。替代地且较不理想的,可能使用一个以上掩蔽步骤来形成并排开口12到18。在一个实施例中,蚀刻掩模(未展示)可提供于衬底20上方。所述蚀刻掩模可直接抵靠衬底20或不直接抵靠衬底20。在此文件中,当存在材料或结构相对于彼此的至少某一物理触摸接触时,所述材料或结构是“直接抵靠”另一者。相比来说,前面没有“直接”的“在…上方”、“在…上”及“抵靠”囊括“直接抵靠”以及其中介入材料或结构不导致所述材料或结构相对于彼此的物理触摸接触的构造。蚀刻掩模可包括其中此类开口中的至少一些紧邻开口具有相对于彼此不同的最小宽度的多个并排开口。举例来说,在一个实施例中,此类开口可具有如图1中所展示的俯视图中的开口12到18的确切大小及形状。不管怎样,蚀刻掩模可为在衬底20上方竖直地提供的光掩模/光罩,且借此与衬底20间隔开。替代地作为实例,蚀刻掩模可能包括沉积在衬底20顶部上或形成衬底20的竖直最外部分的光致抗蚀剂及/或硬掩蔽材料且经处理以具有所述蚀刻掩模并排开口。
在一个实施例中,接着使用蚀刻掩模经由并排开口将等离子蚀刻进行到衬底20中。与经由蚀刻掩模中的较窄最小宽度开口蚀刻的衬底开口相比,经由蚀刻掩模中的较宽最小宽度开口蚀刻的所述衬底开口将更深地经蚀刻进入到衬底中(举例来说)以形成如图1到3中所描绘的结构。作为实例,可使用从约200瓦特到约1,500瓦特的顶部功率范围在电感耦合等离子蚀刻反应器中进行等离子蚀刻,基座/衬底偏压从约10瓦特到约500瓦特,衬底温度从约20℃到约100℃,且室压力从约20mTorr到约300mTorr。当经蚀刻的衬底材料包括氮化硅、非晶硅及/或晶体硅时,作为馈送气体的实例性蚀刻化学品包含体积流量比率分别为约0.5到2:0.5到2:0.5到2的SF6、O2、HBr,其中1:1:1的比率是特定实例。作为进一步实例,NF3及/或CF4可替代SF6,及/或Cl2可替代HBr。在经蚀刻的衬底材料包括SiO2的情况下,实例性蚀刻馈送气体化学品包含实例性体积流量比率分别为约0.5到2及0.5到2的CF4及O2,其中1:1是特定实例。可替代CF4或除CF4之外使用氢氟碳化物。
在一个实施例中,衬底开口12到18经形成以个别地具有恒定深度(例如,如由图3中的开口12的基底29的水平线所展示)。
参考图4到6,已移除横向于并排开口12到18(未展示)之间的壁21(未展示)以形成较大开口30(即,比个别开口12到18大)。较大开口30包括侧壁32,所述侧壁具有非垂直侧壁表面34,其中在至少一个直线垂直横截面中移除所述壁21,所述至少一个直线垂直横截面正交于所述经移除壁21通过所述侧壁表面34。由图2及5所描绘的横截面是此直线垂直横截面的实例。图4到6实施例中的非垂直侧壁表面34在点“A”与点“B”之间延伸,且因此在一个实施例中如所展示延伸到衬底20的竖直最外表面33(即,在移除可能直接抵靠衬底20或构成衬底20的竖直最外材料的任一蚀刻掩模之后)。
在一个实施例中,在其间具有壁的多个并排开口是亚微米,且在一个实施例中较大开口是亚微米。在一个实施例中,较大开口经形成为正交于至少一个直线横截面而纵向伸长的,举例来说如图4及6中所展示。
移除壁以产生类似图4到6的构造的构造可通过任何现有或尚待开发的方式而发生。在一个实施例中,移除壁的动作通过(举例来说)使用湿式及/或干式各向同性蚀刻动作的蚀刻而发生以移除壁。在一个实施例中,形成在其间具有壁的多个并排开口的动作包括在做出移除那些壁的动作时进行蚀刻。在一个此实施例中,形成的动作及移除的动作包括单独不同化学品的时间间隔蚀刻步骤。在其中开口通过蚀刻形成且壁通过蚀刻移除的再一个实施例中,形成开口的动作的蚀刻及移除壁的动作的蚀刻包括从形成到移除的单个连续蚀刻步骤。举例来说且仅以实例的方式,将如图1到3中所展示的衬底20视为具有直接抵靠衬底20的竖直最外表面的蚀刻掩模(例如,光致抗蚀剂及/或硬掩模)。所述蚀刻掩模可能经制作以最初具有对应于如出现于图1中的开口的开口。可进行等离子蚀刻以蚀刻图1到3中所展示的所描绘开口,其中蚀刻掩模的厚度及材料经选择使得等离子蚀刻的继续导致移除蚀刻掩模的开口之间的壁(例如,通过横向蚀刻)。此蚀刻将借此在蚀刻继续时暴露下伏壁21的竖直最外表面,借此蚀刻掉在并排衬底开口之间的那些壁。导致蚀刻在形成或接近形成非垂直侧壁表面34时有效地停止的蚀刻条件及材料可经选择,其中在不必存在用于蚀刻壁的单独的时间间隔移除步骤的情况下蚀刻掩模自身的持续蚀刻发生。蚀刻条件及或许化学品可稍后在连续蚀刻期间改变以实现比连续蚀刻动作中早期发生的蚀刻掩模的任何移除大的蚀刻掩模的材料的移除。
图1到3展示其中并排开口12到18中的每一紧邻开口在衬底中相对于彼此具有不同深度的实例性实施例。具体来说,在每一紧邻对开口12/13、13/14、14/15、15/16、16/17、17/18中,每一开口在每一对中的衬底中具有不同深度。此外,图1到3展示其中所有并排开口12到18相对于彼此具有不同深度(即,开口12到18中的任何两者在衬底20内均不具有相同深度)的实例性实施例。在替代实施例中,紧邻并排开口中的仅一些开口在衬底中形成到相对于彼此不同的深度,举例来说如由图7中的替代衬底片段10a所展示。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差别是以后缀“a”指示。举例来说,衬底片段10a具有相同深度相对衬底20的紧邻对个别开口12、13、14、15、16,其中紧邻衬底开口12/13、13/14、14/15、15/16之间的深度为相对于彼此不同的。图8展示图7的壁21(未展示)的后续移除,借此形成其中移除壁的非垂直侧壁表面34a。可采用如上文所描述的任何其它属性。
图4到6展示其中非垂直侧壁表面34经形成以沿着如图5中所展示的直线垂直横截面沿着其长度的至少大部分(即,50%以上)为直线性的实例性实施例。在一个实施例中且还如图5中所展示,非垂直侧壁表面34沿着在直线垂直横截面中的实质上所有(即,95%以上)其长度为直线性的。图8描绘其中较大开口30a的非垂直侧壁表面34a沿着其长度的大部分并非直线性的而是(举例来说)具有所描绘不同成角度区段35的替代实施例。可采用如上文所描述的任何其它属性。
图8还描绘其中非垂直侧壁表面34a经形成以具有不同成角度直线性区段35(举例来说,所描绘水平成角度区段)与实质上相对于彼此成相同角度(例如,仅与垂直总体不同的两个角度)的所描绘向上/向下成角度区段的组合的实例性实施例。图9展示图8的衬底片段的替代实施例衬底片段10b。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差别是以后缀“b”指示。在图9中,较大开口30b的非垂直侧壁表面34b具有两个以上不同成角度区段35b。此可由类比于且稍微不同于图7的那些开口的适当深度并排开口形成。可采用如上文所描述的任何其它属性。
因此,较大开口的非垂直侧壁表面可通过使最初形成的并排开口的深度变化而具有任何所期望配置。进一步举例来说,非垂直侧壁表面可经形成以沿着直线垂直横截面沿着其长度的至少大部分且在一个实施例中沿着其长度的实质上全部为弯曲的。在图10及图11中分别关于衬底片段10c及10d展示实例性此类实施例。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异分别是以后缀“c”及后缀“d”指示。衬底片段10c包含较大开口30c。其侧壁32c包含非垂直凹面侧壁表面34c。衬底片段10d包含较大开口30d。其侧壁32d包含非垂直凸面侧壁表面34d。可采用如上文所描述的任何其它属性。
在一个实施例中,非垂直侧壁表面经形成以具有至少一个直线性区段与至少一个弯曲区段的组合,举例来说如关于图12中的衬底片段10e所展示。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异是以后缀“e”指示。较大开口30e包含侧壁32e,所述侧壁具有非垂直侧壁表面34e,所述非垂直侧壁表面具有直线性区段39及弯曲区段37。可采用如上文所描述的任何其它属性。
图4到6;8;9;10;11及12的上文所描述的实施例展示其中较大开口经形成以包括在所描绘直线垂直横截面中与非垂直侧壁表面34、34a、34b、34c、34d或34e横向相对的垂直侧壁表面41的实例。在一个实施例中,较大开口可经形成为无与非垂直侧壁表面横向相对的任何垂直侧壁表面,且在一个实施例中无任何垂直表面。举例来说,图13描绘替代实施例衬底片段10f。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异是以后缀“f”指示。衬底片段10f具有既无与非垂直侧壁表面横向相对的任何垂直侧壁表面又无任何垂直表面的较大开口30f。可采用如上文所描述的任何其它属性。
图14及15分别描绘进一步实例性此类替代实施例衬底片段10g、10h。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异分别是以后缀“g”及“h”指示。在图14中,衬底片段10g具有经形成以在所描绘直线垂直横截面中为“V”形状的较大开口30g。在图15中,衬底片段10h具有经形成以在所描绘直线垂直横截面中为“W”形状的较大开口30h。可使用其它形状。可采用如上文所描述的任何其它属性。
在一个实施例中,较大开口经形成以包括为垂直的且与非垂直侧壁表面接合的竖直最外侧壁表面。此实例性衬底片段10j展示于图16中。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异是以后缀“j”或以不同编号指示。较大开口30j包括侧壁32j,所述侧壁具有为垂直的且与非垂直侧壁表面34j接合的竖直最外侧壁表面50。可采用如上文所描述的任何其它属性。
在一个实施例中,所有并排开口经形成为正交于直线垂直横截面而纵向伸长的,举例来说如在观看图1的俯视图时固有的。在一个实施例中,并排衬底开口中的至少一者经形成为并非纵向伸长的。此举例来说在图17中关于衬底片段10k而展示。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异是以后缀“k”或不同编号指示。衬底片段10k具有并排衬底开口61、62、63、64、65、66、67,所述并排衬底开口在其间具有壁21。衬底开口61如所展示经形成为正方形的,借此(举例来说)与为纵向伸长(例如,矩形)的开口62到67中的每一者相比并非纵向伸长的。替代地,开口62到67中的一或多者可为正方形的(未展示)。可采用如上文所描述的任何其它属性。
图4到6的上文实例性实施例将较大开口30描绘为经形成以具有正交于直线垂直横截面的水平基底表面29(图6),所述直线垂直横截面正交于经移除壁(图4及5)通过侧壁表面。在一个实施例中且如所展示,水平基底表面29沿着正交于所述直线垂直横截面的较大开口的实质上所有部分(即,至少95%)延伸。替代地,较大开口可经形成以具有正交于直线垂直横截面的某一非水平基底表面,举例来说如图18中关于衬底片段10m所展示。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异是以后缀“m”指示。图18在位置上对应于图6的位置。衬底片段10m的较大开口30m展示为具有正交于所述直线垂直横截面(例如,类似图5的横截面的横截面)的非水平基底表面29m,且所述非水平基底表面沿着较大开口的实质上全部正交于所述直线垂直横截面延伸。可采用如上文所描述的任何其它属性。
此类非水平基底表面的形成可以任何适合方式实现。在一个此实施例中,并排衬底开口可经形成以个别地具有多个不同最外敞开尺寸,举例来说如关于图19到21中的替代实施例衬底片段10s所展示。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异是以后缀“s”或以不同编号指示。衬底片段10s具有形成于衬底20中的并排开口71、72、73、74。这些并排开口个别地具有多个不同最外敞开尺寸(举例来说),其中在俯视图(图19)中各自展示为具有渐缩侧壁。
参考图22到24,已移除壁21(未展示)以形成较大开口30s,所述较大开口具有其中在所描绘图23直线垂直横截面中移除壁的非垂直侧壁表面34s。图24展示为非水平的较大开口30s的基底29s。此可由图19到21中的开口71、72、73、74在一个纵向端处比在另一纵向端处宽导致,借此将较大开口30s形成为在衬底20中与较窄端相比在较宽端处较深。可采用如上文所描述的任何其它属性。
上文所描绘实施例展示所描绘视图中的仅单个较大开口。可能形成可能上百、上千或更多此类开口。此外,那些大开口可能平行或以其它方式相对于彼此定向,且相对于彼此具有任何间距。图25展示具有形成于其中的一系列紧密间隔的较大开口30的替代实施例衬底片段10x。已在适当的情况下使用来自上文所描述的实施例的相同编号,其中一些构造差异是以后缀“x”指示。可采用如上文所描述的任何其它属性。不管怎样,可在任何现有或尚待开发的设备中使用根据本发明的实施例形成的结构。举例来说,较大开口可用作光学或其它波导或用于铁电硅上液晶(FLCOS)装置中。
总结
在一些实施例中,形成衬底开口的方法包括在衬底中形成多个并排开口。紧邻并排开口中的至少一些开口在衬底中形成到相对于彼此不同的深度。移除横向介于并排开口之间的壁以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于所述经移除壁通过侧壁表面。
在一些实施例中,形成衬底开口的方法包括在衬底上方提供蚀刻掩模。蚀刻掩模包括多个并排开口。至少一些紧邻并排开口具有相对于彼此不同的最小宽度。多个并排开口使用蚀刻掩模等离子蚀刻到衬底中。与经由蚀刻掩模中的较窄最小宽度开口蚀刻的衬底开口相比,经由蚀刻掩模中的较宽最小宽度开口蚀刻的衬底开口更深地蚀刻到衬底中。移除横向介于并排衬底开口之间的壁以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于所述经移除壁通过侧壁表面。
按照条例,已在语言上关于结构及方法特征更特定或较不特定描述本文中所揭示的标的物。然而,应理解,由于本文中所揭示的方法包括实例性实施例,因此所述权利要求书不限于所展示及所描述的特定特征。因此,所述权利要求书是由字面措辞来提供完整范围,且根据等效内容的教义适当地予以解释。

Claims (44)

1.一种形成衬底开口的方法,其包括:
在衬底中形成多个并排开口,所述并排开口的紧邻的开口之间具有壁,紧邻的所述并排开口中的至少一些开口在所述衬底中形成到相对于彼此不同的深度;及
移除所述壁的所有部分以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于经移除的所述壁而通过所述非垂直侧壁表面,
其中所述形成包括蚀刻且所述移除包括蚀刻,所述形成的所述蚀刻及所述移除的所述蚀刻包括从所述形成到所述移除的单个连续蚀刻步骤。
2.根据权利要求1所述的方法,其中所述形成的所述蚀刻包括等离子蚀刻。
3.根据权利要求2所述的方法,其包括仅使用单个掩蔽步骤来形成在其间具有壁的所述并排开口。
4.根据权利要求1所述的方法,其中在其间具有壁的所述多个并排开口分别是亚微米的,且所述较大开口是亚微米的。
5.根据权利要求1所述的方法,其中在其间具有壁的紧邻并排开口中的仅一些开口在所述衬底中形成到相对于彼此不同的深度。
6.根据权利要求1所述的方法,其中在其间具有所述壁的每一紧邻并排开口在所述衬底中相对于彼此具有不同深度。
7.根据权利要求6所述的方法,其中在其间具有所述壁的所有并排开口相对于彼此具有不同深度。
8.根据权利要求1所述的方法,其中在其间具有所述壁的所有所述衬底开口经形成为正交于所述直线垂直横截面而纵向伸长的。
9.根据权利要求1所述的方法,其中在其间具有所述壁的所述衬底开口中的至少一者经形成为并非纵向伸长的。
10.根据权利要求1所述的方法,其中在其间具有所述壁的所述衬底开口经形成以个别地具有恒定深度。
11.根据权利要求1所述的方法,其中所述非垂直侧壁表面经形成以沿着所述至少一个直线垂直横截面沿着其长度的至少大部分为直线性的。
12.根据权利要求11所述的方法,其中所述非垂直侧壁表面经形成以沿着所述至少一个直线垂直横截面沿着其长度的实质上全部为直线性的。
13.根据权利要求1所述的方法,其中所述非垂直侧壁表面经形成以沿着所述至少一个直线垂直横截面沿着其长度的至少大部分为弯曲的。
14.根据权利要求13所述的方法,其中所述非垂直侧壁表面经形成以沿着所述至少一个直线垂直横截面沿着其长度的实质上全部为弯曲的。
15.根据权利要求14所述的方法,其中所述非垂直侧壁表面经形成为凹面的。
16.根据权利要求1所述的方法,其中所述非垂直侧壁表面经形成以具有至少一个直线性区段与至少一个弯曲区段的组合。
17.根据权利要求1所述的方法,其中所述非垂直侧壁表面经形成以具有不同成角度直线性区段的组合。
18.根据权利要求1所述的方法,其中所述较大开口经形成以包括在所述至少一个直线垂直横截面中与所述非垂直侧壁表面横向相对的垂直侧壁表面。
19.根据权利要求1所述的方法,其中所述较大开口经形成为无在所述至少一个直线垂直横截面中与所述非垂直侧壁表面横向相对的任何垂直侧壁表面。
20.根据权利要求1所述的方法,其中所述较大开口经形成为无任何垂直侧壁表面。
21.根据权利要求20所述的方法,其中所述较大开口经形成以在所述至少一个直线垂直横截面中为“V”形状。
22.根据权利要求20所述的方法,其中所述较大开口经形成以在所述至少一个直线垂直横截面中为“W”形状。
23.根据权利要求1所述的方法,其中所述非垂直侧壁表面在移除可能上覆于所述衬底上的任何蚀刻掩模之后延伸到所述衬底的竖直最外表面。
24.根据权利要求1所述的方法,其中所述较大开口经形成以包括为垂直的且与所述非垂直侧壁表面接合的竖直最外侧壁表面。
25.根据权利要求1所述的方法,其中所述较大开口经形成以具有正交于所述一个直线垂直横截面的水平基底表面。
26.根据权利要求25所述的方法,其中所述水平基底表面沿着所述较大开口的实质上全部正交于所述一个直线垂直横截面延伸。
27.根据权利要求1所述的方法,其中在其间具有所述壁的所述衬底开口经形成以个别地具有多个不同最外敞开尺寸,且所述较大开口经形成以具有正交于所述一个直线垂直横截面的非水平基底表面。
28.根据权利要求1所述的方法,其包括将所述较大开口形成为正交于所述至少一个直线横截面而纵向伸长的。
29.根据权利要求1所述的方法,其中所述连续蚀刻从开始至结束期间使用同样的蚀刻化学品。
30.根据权利要求1所述的方法,其中所述连续蚀刻从开始至结束期间为等离子蚀刻。
31.根据权利要求30所述的方法,其中所述连续蚀刻从开始至结束期间使用同样的蚀刻化学品。
32.根据权利要求30所述的方法,其中所述连续蚀刻从开始至结束期间使用不同的蚀刻化学品。
33.根据权利要求30所述的方法,其中所述连续蚀刻从开始至结束期间使用相同的蚀刻条件。
34.根据权利要求30所述的方法,其中所述连续蚀刻从开始至结束期间使用不同的蚀刻条件。
35.一种使用蚀刻掩模形成衬底开口的方法,所述蚀刻掩模包括多个并排开口,至少一些紧邻的并排开口具有相对于彼此不同的最小宽度,所述方法包括:
使用所述蚀刻掩模将多个并排开口等离子蚀刻到所述衬底中,所述衬底开口的紧邻的开口之间具有壁,与经由所述蚀刻掩模中的较窄最小宽度开口蚀刻的所述衬底开口相比,经由所述蚀刻掩模中的较宽最小宽度开口蚀刻的所述衬底开口更深地蚀刻到所述衬底中;及
继续所述等离子蚀刻以移除所述壁的所有部分以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于经移除的所述壁而通过所述非垂直侧壁表面。
36.根据权利要求35所述的方法,其中所述蚀刻掩模直接抵靠所述衬底。
37.根据权利要求35所述的方法,其中所述蚀刻掩模不直接抵靠所述衬底。
38.根据权利要求35所述的方法,其中所述蚀刻掩模直接抵靠所述衬底,且其中所述继续所述等离子蚀刻移除横向介于所述蚀刻掩模中的所述并排开口之间的壁,且借此竖直地暴露且蚀刻掉横向介于所述并排衬底开口之间的所述壁。
39.一种形成衬底开口的方法,其包括:
在衬底中形成多个并排开口,所述并排开口的紧邻的开口之间具有壁,紧邻的所述并排开口中的至少一些开口在所述衬底中形成到相对于彼此不同的深度;及
移除所述壁的所有部分以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于经移除的所述壁而通过所述非垂直侧壁表面,所述非垂直侧壁表面经形成为凸面的,
其中所述形成包括蚀刻且所述移除包括蚀刻,所述形成的所述蚀刻及所述移除的所述蚀刻包括从所述形成到所述移除的单个连续蚀刻步骤。
40.一种形成衬底开口的方法,其包括:
在衬底中形成多个并排开口,所述并排开口的紧邻的开口之间具有壁,紧邻的所述并排开口中的至少一些开口在所述衬底中形成到相对于彼此不同的深度;及
移除所述壁的所有部分以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于经移除的所述壁而通过所述非垂直侧壁表面,所述较大开口经形成以具有正交于所述一个直线垂直横截面的非水平基底表面,
其中所述形成包括蚀刻且所述移除包括蚀刻,所述形成的所述蚀刻及所述移除的所述蚀刻包括从所述形成到所述移除的单个连续蚀刻步骤。
41.根据权利要求40所述的方法,其中所述非水平基底表面沿着所述较大开口的实质上全部正交于所述一个直线垂直横截面延伸。
42.根据权利要求40所述的方法,其中所述衬底开口各自在形状上为梯形且其间具有所述壁,所述壁分别具有多个不同的最大外侧开口尺寸。
43.一种形成衬底开口的方法,其包括:
在衬底中形成多个并排开口,紧邻的并排开口中的至少一些开口在所述衬底中形成到相对于彼此不同的深度;及
移除横向介于所述并排开口之间的壁以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于经移除的所述壁而通过所述侧壁表面,所述形成包括蚀刻且所述移除包括蚀刻,所述形成的所述蚀刻及所述移除的所述蚀刻包括从所述形成到所述移除的单个连续蚀刻步骤,所述非垂直侧壁表面经形成以沿着所述至少一个直线垂直横截面沿着其长度的实质上全部为弯曲的,所述非垂直侧壁表面经形成为凸面的。
44.一种形成衬底开口的方法,其包括:
在衬底中形成多个并排开口,紧邻的并排开口中的至少一些开口在所述衬底中形成到相对于彼此不同的深度;及
移除横向介于所述并排开口之间的壁以形成较大开口,所述较大开口具有非垂直侧壁表面,其中在至少一个直线垂直横截面中移除所述壁,所述至少一个直线垂直横截面正交于经移除的所述壁而通过所述侧壁表面,所述非垂直侧壁表面完全形成为凸面,其中所述形成包括蚀刻且所述移除包括蚀刻,所述形成的所述蚀刻及所述移除的所述蚀刻包括从所述形成到所述移除的单个连续蚀刻步骤。
CN201480028217.1A 2013-05-29 2014-04-24 形成衬底开口的方法 Active CN105229775B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/904,933 2013-05-29
US13/904,933 US9005463B2 (en) 2013-05-29 2013-05-29 Methods of forming a substrate opening
PCT/US2014/035276 WO2014193569A1 (en) 2013-05-29 2014-04-24 Methods of forming a substrate opening

Publications (2)

Publication Number Publication Date
CN105229775A CN105229775A (zh) 2016-01-06
CN105229775B true CN105229775B (zh) 2018-07-27

Family

ID=51985596

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480028217.1A Active CN105229775B (zh) 2013-05-29 2014-04-24 形成衬底开口的方法

Country Status (8)

Country Link
US (2) US9005463B2 (zh)
EP (1) EP3005406A4 (zh)
JP (1) JP6259909B2 (zh)
KR (2) KR101970419B1 (zh)
CN (1) CN105229775B (zh)
SG (2) SG10201805849SA (zh)
TW (1) TWI569324B (zh)
WO (1) WO2014193569A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385132B2 (en) 2011-08-25 2016-07-05 Micron Technology, Inc. Arrays of recessed access devices, methods of forming recessed access gate constructions, and methods of forming isolation gate constructions in the fabrication of recessed access devices
US9005463B2 (en) 2013-05-29 2015-04-14 Micron Technology, Inc. Methods of forming a substrate opening
GB2583348A (en) * 2019-04-24 2020-10-28 Univ Southampton Photonic chip and method of manufacture
CN111427118A (zh) * 2020-03-25 2020-07-17 中山大学 一种应用于通讯波段的高效三维硫化物端面耦合器及其制备方法

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH682528A5 (fr) * 1990-03-16 1993-09-30 Westonbridge Int Ltd Procédé de réalisation par attaque chimique d'au moins une cavité dans un substrat et substrat obtenu par ce procédé.
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
JPH0669605A (ja) 1992-08-21 1994-03-11 Oki Electric Ind Co Ltd 回折格子の形成方法
US5814547A (en) 1997-10-06 1998-09-29 Industrial Technology Research Institute Forming different depth trenches simultaneously by microloading effect
US7759113B2 (en) * 1999-04-30 2010-07-20 The General Hospital Corporation Fabrication of tissue lamina using microfabricated two-dimensional molds
US6190971B1 (en) 1999-05-13 2001-02-20 International Business Machines Corporation Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region
JP3442004B2 (ja) * 1999-07-30 2003-09-02 キヤノン株式会社 光学素子の製造方法
JP2001114592A (ja) 1999-10-13 2001-04-24 Sony Corp エピタキシャル成長方法及び成膜用ウエハ
JP2002169011A (ja) 2000-12-05 2002-06-14 Minolta Co Ltd 回折光学素子および回折格子の表面形状の作製方法
JP2002189112A (ja) * 2000-12-22 2002-07-05 Canon Inc 回折光学素子の製造方法、回折光学素子の製造方法によって製造したことを特徴とする回折光学素子製造用金型、回折光学素子、および該回折光学素子を有する光学系、光学機器、露光装置、デバイス製造方法、デバイス
JP2002350623A (ja) * 2001-05-23 2002-12-04 Dainippon Printing Co Ltd 回折光学素子の製造方法
US6884732B2 (en) 2001-10-15 2005-04-26 The Regents Of The University Of Michigan Method of fabricating a device having a desired non-planar surface or profile and device produced thereby
JP2003139915A (ja) 2001-10-31 2003-05-14 Seiko Epson Corp マイクロレンズ及びその製造方法並びに電気光学装置
US6794268B2 (en) 2002-07-31 2004-09-21 Intel Corporation Fabricating deeper and shallower trenches in semiconductor structures
US7071043B2 (en) 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US6716709B1 (en) 2002-12-31 2004-04-06 Texas Instruments Incorporated Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps
US6887395B2 (en) * 2003-02-10 2005-05-03 Intel Corporation Method of forming sub-micron-size structures over a substrate
US6864152B1 (en) 2003-05-20 2005-03-08 Lsi Logic Corporation Fabrication of trenches with multiple depths on the same substrate
DE102004043233B4 (de) * 2003-09-10 2014-02-13 Denso Corporation Verfahren zum Herstellen eines beweglichen Abschnitts einer Halbleitervorrichtung
GB0404749D0 (en) 2004-03-03 2004-04-07 Koninkl Philips Electronics Nv Trench field effect transistor and method of making it
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7384849B2 (en) 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7541632B2 (en) 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US20070054464A1 (en) 2005-09-08 2007-03-08 Chartered Semiconductor Manufacturing Ltd. Different STI depth for Ron improvement for LDMOS integration with submicron devices
JP2007165862A (ja) 2005-11-15 2007-06-28 Toshiba Corp 半導体装置の製造方法
JP2008112036A (ja) 2006-10-31 2008-05-15 Osaka Prefecture 微細構造体の製造方法
US20080113483A1 (en) 2006-11-15 2008-05-15 Micron Technology, Inc. Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures
US7859050B2 (en) 2007-01-22 2010-12-28 Micron Technology, Inc. Memory having a vertical access device
US20080258206A1 (en) 2007-04-17 2008-10-23 Qimonda Ag Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same
US7985681B2 (en) 2007-06-22 2011-07-26 Micron Technology, Inc. Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during fabrication of a semiconductor device and electronic systems including the semiconductor device
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US8026170B2 (en) 2007-09-26 2011-09-27 Sandisk Technologies Inc. Method of forming a single-layer metal conductors with multiple thicknesses
KR100929302B1 (ko) 2007-12-26 2009-11-27 주식회사 하이닉스반도체 반도체 소자의 패턴 형성 방법
US8866254B2 (en) 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
JP2009262258A (ja) 2008-04-23 2009-11-12 Seiko Epson Corp シリコン構造体の製造方法
JP2009269120A (ja) * 2008-05-07 2009-11-19 Seiko Epson Corp シリコン構造体の製造方法
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
KR20100082170A (ko) 2009-01-08 2010-07-16 삼성전자주식회사 실리콘 산화막 패턴 및 소자 분리막 형성 방법
MY162405A (en) * 2009-02-06 2017-06-15 Solexel Inc Trench Formation Method For Releasing A Thin-Film Substrate From A Reusable Semiconductor Template
KR101077453B1 (ko) 2009-03-31 2011-10-26 주식회사 하이닉스반도체 반도체 소자의 패턴 형성 방법
KR20100111798A (ko) 2009-04-08 2010-10-18 서울대학교산학협력단 워드라인 더블 패터닝 공정방법 및 이에 의하여 구현된 낸드 플래시 메모리 어레이
TWI396240B (zh) 2009-05-08 2013-05-11 Anpec Electronics Corp 製造功率半導體元件的方法
KR101631599B1 (ko) * 2009-12-02 2016-06-27 삼성전자주식회사 발광 소자 및 그 제조 방법
DE102010000888B4 (de) 2010-01-14 2019-03-28 Robert Bosch Gmbh Verfahren zum Ausbilden von Aussparungen in einem Halbleiterbauelement und mit dem Verfahren hergestelltes Bauelement
US8039340B2 (en) 2010-03-09 2011-10-18 Micron Technology, Inc. Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate
JP5721422B2 (ja) * 2010-12-20 2015-05-20 キヤノン株式会社 面発光レーザ及びアレイ光源
JP5278632B2 (ja) 2011-03-14 2013-09-04 東レ株式会社 感光性導電ペーストおよび導電パターンの製造方法
FR2985602B1 (fr) 2012-01-05 2014-03-07 Commissariat Energie Atomique Procede de gravure d'un motif complexe
US9005463B2 (en) 2013-05-29 2015-04-14 Micron Technology, Inc. Methods of forming a substrate opening

Also Published As

Publication number Publication date
US9005463B2 (en) 2015-04-14
SG10201805849SA (en) 2018-08-30
WO2014193569A1 (en) 2014-12-04
EP3005406A4 (en) 2017-01-11
US20140357086A1 (en) 2014-12-04
US20150214100A1 (en) 2015-07-30
TWI569324B (zh) 2017-02-01
JP6259909B2 (ja) 2018-01-10
KR101970419B1 (ko) 2019-04-18
SG11201508998PA (en) 2015-12-30
TW201511126A (zh) 2015-03-16
KR20160003179A (ko) 2016-01-08
CN105229775A (zh) 2016-01-06
JP2016521012A (ja) 2016-07-14
US9443756B2 (en) 2016-09-13
KR20170063976A (ko) 2017-06-08
EP3005406A1 (en) 2016-04-13

Similar Documents

Publication Publication Date Title
CN101889326B (zh) 用于形成高密度图案的方法
US10768526B2 (en) Method of forming patterns
CN105229775B (zh) 形成衬底开口的方法
US9153458B2 (en) Methods of forming a pattern on a substrate
EP1998362A2 (en) Frequency Tripling Using Spacer Mask Having Interposed Regions
US20140127909A1 (en) Methods Of Forming A Pattern On A Substrate
KR20110011571A (ko) 마이크로-로딩을 저감시키기 위한 플라즈마 에칭 방법
US9564342B2 (en) Method for controlling etching in pitch doubling
US9741580B2 (en) Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate
US20020102500A1 (en) Method for raising etching selectivity of oxide to photoresist
KR100679826B1 (ko) 엠아이엠 영역의 잔류 폴리머 제거 방법
KR20100076608A (ko) 반도체 장치의 콘택홀 형성방법
US20090269935A1 (en) Method of Forming Pattern of Semiconductor Device
KR20050010668A (ko) 반도체 소자의 캐패시터 모니터 패턴 형성방법
KR20070003032A (ko) 반도체 장치의 제조방법
KR20050073046A (ko) 게이트 패턴 형성 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant