CN105190879B - 铜柱附连基板 - Google Patents

铜柱附连基板 Download PDF

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Publication number
CN105190879B
CN105190879B CN201480014113.5A CN201480014113A CN105190879B CN 105190879 B CN105190879 B CN 105190879B CN 201480014113 A CN201480014113 A CN 201480014113A CN 105190879 B CN105190879 B CN 105190879B
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CN
China
Prior art keywords
trace
line
solder mask
assembly according
parallel
Prior art date
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Active
Application number
CN201480014113.5A
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English (en)
Chinese (zh)
Other versions
CN105190879A (zh
Inventor
N·夏海迪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN105190879A publication Critical patent/CN105190879A/zh
Application granted granted Critical
Publication of CN105190879B publication Critical patent/CN105190879B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
CN201480014113.5A 2013-03-13 2014-03-10 铜柱附连基板 Active CN105190879B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/798,678 2013-03-13
US13/798,678 US8896118B2 (en) 2013-03-13 2013-03-13 Electronic assembly with copper pillar attach substrate
PCT/US2014/022334 WO2014164402A1 (en) 2013-03-13 2014-03-10 Copper pillar attach substrate

Publications (2)

Publication Number Publication Date
CN105190879A CN105190879A (zh) 2015-12-23
CN105190879B true CN105190879B (zh) 2018-07-03

Family

ID=51523877

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480014113.5A Active CN105190879B (zh) 2013-03-13 2014-03-10 铜柱附连基板

Country Status (4)

Country Link
US (1) US8896118B2 (enExample)
JP (1) JP6503334B2 (enExample)
CN (1) CN105190879B (enExample)
WO (1) WO2014164402A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6777148B2 (ja) * 2016-07-28 2020-10-28 三菱電機株式会社 半導体装置
JP6691031B2 (ja) * 2016-10-05 2020-04-28 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222647A (zh) * 2010-04-16 2011-10-19 台湾积体电路制造股份有限公司 半导体裸片及形成导电元件的方法
CN102903690A (zh) * 2011-07-29 2013-01-30 台湾积体电路制造股份有限公司 在半导体器件和封装组件中的凸块结构

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11191672A (ja) * 1997-12-25 1999-07-13 Victor Co Of Japan Ltd プリント配線基板
JP3891838B2 (ja) * 2001-12-26 2007-03-14 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
KR100722645B1 (ko) * 2006-01-23 2007-05-28 삼성전기주식회사 반도체 패키지용 인쇄회로기판 및 그 제조방법
JP2008098402A (ja) * 2006-10-12 2008-04-24 Renesas Technology Corp 半導体装置およびその製造方法
KR20090080623A (ko) * 2008-01-22 2009-07-27 삼성전기주식회사 포스트 범프 및 그 형성방법
JP5088489B2 (ja) * 2008-03-03 2012-12-05 セイコーエプソン株式会社 半導体モジュール及びその製造方法
US7851345B2 (en) * 2008-03-19 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of forming oxide layer on signal traces for electrical isolation in fine pitch bonding
WO2010103934A1 (ja) * 2009-03-12 2010-09-16 ナミックス株式会社 アンダーフィル材、及び、電子部品の実装方法
KR101609023B1 (ko) 2009-12-23 2016-04-04 스카이워크스 솔루션즈, 인코포레이티드 표면 마운트 스파크 갭
US8367467B2 (en) 2010-04-21 2013-02-05 Stats Chippac, Ltd. Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222647A (zh) * 2010-04-16 2011-10-19 台湾积体电路制造股份有限公司 半导体裸片及形成导电元件的方法
CN102903690A (zh) * 2011-07-29 2013-01-30 台湾积体电路制造股份有限公司 在半导体器件和封装组件中的凸块结构

Also Published As

Publication number Publication date
JP2016519420A (ja) 2016-06-30
US8896118B2 (en) 2014-11-25
US20140264829A1 (en) 2014-09-18
CN105190879A (zh) 2015-12-23
JP6503334B2 (ja) 2019-04-17
WO2014164402A1 (en) 2014-10-09

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