CN105122447A - 用于包括通过接合包含覆盖低熔点材料层的非低熔点材料层的两个接合部件而形成的高熔点合金的微电子组件的接合结构以及对应制造方法 - Google Patents
用于包括通过接合包含覆盖低熔点材料层的非低熔点材料层的两个接合部件而形成的高熔点合金的微电子组件的接合结构以及对应制造方法 Download PDFInfo
- Publication number
- CN105122447A CN105122447A CN201380071665.5A CN201380071665A CN105122447A CN 105122447 A CN105122447 A CN 105122447A CN 201380071665 A CN201380071665 A CN 201380071665A CN 105122447 A CN105122447 A CN 105122447A
- Authority
- CN
- China
- Prior art keywords
- layer
- attachment
- material layer
- conducting element
- alloy block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000463 material Substances 0.000 title claims abstract description 345
- 239000000956 alloy Substances 0.000 title claims abstract description 153
- 229910045601 alloy Inorganic materials 0.000 title claims abstract description 152
- 238000004377 microelectronic Methods 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000002844 melting Methods 0.000 title abstract description 12
- 230000008018 melting Effects 0.000 title abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 257
- 239000011241 protective layer Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000010438 heat treatment Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims description 49
- 239000004020 conductor Substances 0.000 claims description 40
- 239000013078 crystal Substances 0.000 claims description 40
- 238000001465 metallisation Methods 0.000 claims description 29
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 27
- 229910052733 gallium Inorganic materials 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 21
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 229910052738 indium Inorganic materials 0.000 claims description 20
- 239000000203 mixture Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- VNTLIPZTSJSULJ-UHFFFAOYSA-N chromium molybdenum Chemical compound [Cr].[Mo] VNTLIPZTSJSULJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- MOWMLACGTDMJRV-UHFFFAOYSA-N nickel tungsten Chemical compound [Ni].[W] MOWMLACGTDMJRV-UHFFFAOYSA-N 0.000 claims description 2
- SIBIBHIFKSKVRR-UHFFFAOYSA-N phosphanylidynecobalt Chemical compound [Co]#P SIBIBHIFKSKVRR-UHFFFAOYSA-N 0.000 claims description 2
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 2
- 238000000429 assembly Methods 0.000 claims 13
- 230000000712 assembly Effects 0.000 claims 13
- 230000004048 modification Effects 0.000 description 12
- 238000012986 modification Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 9
- 238000003466 welding Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000013459 approach Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000004927 fusion Effects 0.000 description 5
- 238000012958 reprocessing Methods 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000010992 reflux Methods 0.000 description 3
- 101100400452 Caenorhabditis elegans map-2 gene Proteins 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000967 As alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000521 B alloy Inorganic materials 0.000 description 1
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001096 P alloy Inorganic materials 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 208000018875 hypoxemia Diseases 0.000 description 1
- 210000001161 mammalian embryo Anatomy 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/02—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by means of a press ; Diffusion bonding
- B23K20/023—Thermo-compression bonding
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
- H05K13/046—Surface mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
- H05K13/046—Surface mounting
- H05K13/0465—Surface mounting by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05157—Cobalt [Co] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05164—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05171—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/0518—Molybdenum [Mo] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05181—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/11452—Chemical vapour deposition [CVD], e.g. laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13017—Shape in side view being non uniform along the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/13078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13105—Gallium [Ga] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/165—Material
- H01L2224/16501—Material at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/165—Material
- H01L2224/16501—Material at the bonding interface
- H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/165—Material
- H01L2224/16505—Material outside the bonding interface, e.g. in the bulk of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
- H01L2224/2745—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
- H01L2224/27452—Chemical vapour deposition [CVD], e.g. laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2746—Plating
- H01L2224/27462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2746—Plating
- H01L2224/27464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29023—Disposition the whole layer connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
- H01L2224/29082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29105—Gallium [Ga] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
- H01L2224/32501—Material at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
- H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81053—Bonding environment
- H01L2224/81054—Composition of the atmosphere
- H01L2224/81075—Composition of the atmosphere being inert
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81141—Guiding structures both on and outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/8182—Diffusion bonding
- H01L2224/81825—Solid-liquid interdiffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83054—Composition of the atmosphere
- H01L2224/83075—Composition of the atmosphere being inert
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/8382—Diffusion bonding
- H01L2224/83825—Solid-liquid interdiffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/381—Pitch distance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
一种微电子组件(10、110、210、310、410)包括:第一衬底(12、112、212、312、412、512、612、712、812、912),具有第一导电元件(26、126、226、326、426、526、626、726、826、926、1022);以及第二衬底(14、114、214、314、414),具有第二导电元件(26、126、226、326、426)。该组件还包括导电合金块(16、116),接合至第一和第二导电元件(26、126、226、326、426、526、626、726、826、926、1022),包括第一、第二和第三材料。导电合金块(16、116)的第一和第二材料的熔点均低于合金的熔点。第一材料的浓度从朝向第一导电元件(26、126、226、326、426、526、626、726、826、926、1022)设置的位置处的相对较大量向朝向第二导电元件(26、126、226、326、426)的相对较小量变化,并且第二材料的浓度从朝向第二导电元件(26、126、226、326、426)设置的位置处的相对较大量向朝向第一导电元件(26、126、226、326、426、526、626、726、826、926、1022)的相对较小量变化。通过将具有第一接合部件(30、230、330、430)的第一衬底(12、112、212、312、412、512、612、712、812、912)与具有第二接合部件(40、240、340、440)的第二衬底(14、114、214、314、414)对准来形成微电子组件(10、110、210、310、410),使得第一(30、230、330、430、1030)和第二(40、240、340、440)接合部件彼此接触,第一接合部件(30、230、330、430、1030)包括邻近第一导电元件(26、126、226、326、426、526、626、726、826、926、1022)的第一材料层(36、536、636、736、836、936)以及上覆第一材料层(36、536、636、736、836、936)的第一保护层(38、538、638、738、838、938),第二接合部件(40、240、340、440)包括邻近第二导电元件(26)的第二材料层(46)以及上覆第二材料层(46)的第二保护层(48),并且加热第一(30、230、330、430、1030)和第二(40、240、340、440)接合部件使得第一(36、536、636、736、836、936)和第二(46)材料层的至少部分一起扩散以形成使第一(12、112、212、312、412、512、612、712、812、912)和第二(14、114、214、314、414)衬底彼此接合的合金块(16、116)。可以在第一衬底(12、112、212、312、412、512、612、712、812、912)上形成多个第一导电元件(26、126、226、326、426、526、626、726、826、926、1022)以及在第二衬底(14、114、214、314、414)上形成多个第二导电元件(26、126、226、326、426),由多个导电合金块(16、116)接合。导电合金块(116)还可以包围并密封内部容积。<!-- 2 -->
Description
背景技术
封装微电子设备和相关连接部件(诸如中介片等)使用各种结构来利于与其他封装微电子设备或连接部件的附接,从而形成各种微电子组件。这种结构可以包括在设备或部件的表面处露出的导电金属的放大面积形式的接触焊盘。可选地,这种结构可以为金属化过孔、导电销、柱等的露出端的形式。当与另一设备或部件中的类似连接部件对准时,可以使用例如导电接合材料(诸如焊料块等)将连接部件接合到一起。诸如图1A所示焊料块1的焊料块通常被用于形成这种接合件,因为它们相对较低的熔化温度而容易在结构之间接合。此外,这种导电接合块可以再加工或回流,允许修复或调整接合件。
然而,这种接合块的使用可以具有一些缺陷,尤其当被熔化以在例如接触焊盘等之间形成接合件时,这种接合件会经受横向变形。这可以在冷却之前的块加宽的过程中显示出来,导致接合件宽于初始沉积的块。此外,这种加宽会由于接合件的加热而在微电子组件的正常使用期间增加。因此,如图1C所示,一般接受的是,导电连接元件(诸如接触焊盘2(图1B)等)之间的最小间隔P等于导电连接元件2本身的宽度W的1.5倍。此外,由于导电接合块(诸如焊料等)的宽度直接与其高度相关(由于形成期间的表面张力,其发生在液态),所以这种接合件的期望高度越高,宽度越大。这种关系会仅基于期望的接合高度而需要大接触焊盘2和大间隔P。
对于相对较大接触焊盘2或其他连接部件的需求会导致沿着这些部件的接合表面3增加凹陷。具体地,当微电子设备或连接部件的表面通过抛光(通过化学或机械装置)完成时,连接部件会产生凹面。这种凹面可以在相对较大的部件中增加。这种凹陷会不利地影响接合强度并且通常是不期望的。
发明内容
本公开的一个方面涉及一种微电子组件,其包括:第一衬底,具有表面和第一导电元件;以及第二衬底,具有表面和第二导电元件。该组件还包括接合至第一和第二导电元件的导电合金块。导电合金块包括第一材料、第二材料和第三材料。第一和第二材料的熔点均低于合金的熔点。第一材料的浓度从朝向第一导电元件设置的位置处的相对较大量向朝向第二导电元件的相对较小量变化,并且第二材料的浓度从朝向第二导电元件设置的位置处的相对较大量向朝向第一导电元件的相对较小量变化。在一个示例中,第一衬底和第二衬底中的至少一个为半导体材料或介电材料中的至少一种材料。
合金块可具有小于5微米的厚度。在又一示例中,合金块具有小于1微米的厚度。第一材料和第二材料中的至少一种材料的浓度从相对较大浓度向相对较小浓度单调地变化。第一材料的相对较大浓度的位置可以与第一导电元件相邻。
第三材料可包括铜、镍、钨、钴、磷、钯、硼、金或银或这些材料的合金等中的至少一种。第一材料和第二材料中的每一个都可在未与第三材料合金化的状态下具有小于200摄氏度的熔点。在又一示例中,第一材料和第二材料中的至少一种材料在未与第三材料合金化的状态下具有小于50℃的熔点。第一和第二材料可以是低熔点材料。例如,第一和第二材料可以是从锡、铟和镓中选择的不同材料。
在一个示例中,第一导电元件可包括块状导体块,导电合金块上覆块状导体块。第一材料的一部分可扩散到块状导体块中。在另一示例中,第一导电元件还可以包括上覆块状导体块的阻挡层,导电合金块可以接合至阻挡层。
第一衬底可以包括半导体和介电材料中的至少一种材料的第一支持材料层。在这种示例中,支持材料层限定第一衬底的表面,并且第一导电元件可以是延伸穿过第一支持材料层的一部分并且在第一表面处露出的金属化过孔。第一导电元件可以限定端面和远离端面延伸的边缘面,并且边缘面的一部分可以接触过孔内的第一支持材料层。此外,边缘面的一部分可以在第一支持材料外延伸。在这种示例中,第二衬底可以包括半导体和介电材料中的至少一种材料并限定第二元件的表面的第二支持材料。第二导电元件还可以是延伸穿过第二支持材料层的一部分并在表面处露出的金属化过孔,并且导电合金块的至少一部分可以设置在第二支持材料层内。
第一导电元件和第二导电元件在与导电合金块的相应接合界面处均具有小于25微米的宽度。在又一示例中,第一导电元件和第二导电元件在与导电合金块的相应接合界面处均具有小于3微米的宽度。
第一元件可包括多个第一导电元件,并且第二元件可包括多个第二导电元件。在这种示例中,多个导电合金块可以接合在相应的第一导电元件和第二导电元件之间。在又一示例中,第一导电元件均具有一宽度,并且第一导电元件在横向上相互隔开的间距小于第一导电元件的宽度。
第一导电元件可包括在朝向第二元件的方向上延伸的多个毛细结构,并且导电合金块可以环绕并接合至多个毛细结构中的至少一些单个的毛细结构。
第一元件可以包括限定第一元件的表面并在横向上延伸的衬底,且第一导电元件为远离表面延伸的柱的形式。
第一元件还可以包括与第一导电元件电连接的微电子元件。
本公开的另一方面涉及一种微电子组件,包括限定表面的第一衬底和限定表面的第二衬底。该组件还包括合金块,接合至第一元件和第二元件的表面。合金块包括第一材料、第二材料和第三材料。第一材料的浓度从朝向第一元件设置的位置处的相对较大量向朝向第二元件的相对较小量变化。第二材料的浓度从朝向第二元件设置的位置处的相对较大量向朝向第一元件的相对较小量变化。合金块的熔点大于第一材料处于未合金状态的熔点并且大于第二材料处于未合金状态的熔点。
在一个示例中,导电合金块可环绕在第一元件和第二元件的表面的对面部分之间限定的内部容积。此外,内部容积被密封。
在另一示例中,第一元件和第二元件可分别包括第一导电元件和第二导电元件,第一导电元件和第二导电元件限定第一元件和第二元件的表面的接合至导电合金块的部分。
本发明的另一方面涉及一种用于制造微电子组件的方法。该方法包括:将第一接合部件与第二接合部件对准,使得第一接合部件和第二接合部件相互接触。第一接合部件包括在第一元件中,第一元件具有限定表面和表面处露出的第一导电元件的衬底。第一接合部件包括与第一导电元件相邻的第一材料层和上覆第一材料层的第一保护层。第二接合部件包括在第二元件中,第二元件包括限定表面和在该表面处露出的第二导电元件的衬底。第二接合部件包括与第二导电元件相邻的第二材料层和上覆第一材料层的第二保护层。该方法还包括加热第一接合部件和第二接合部件,使得至少第一材料层和第二材料层一起扩散以形成将第一元件和第二元件相互接合的合金块。
可以以第一温度执行加热步骤,并且合金块的熔点处于大于第一温度的第二温度。在加热以进一步形成合金块的步骤期间,第一保护层和第二保护层与第一材料层和第二材料层一起扩散。可以执行加热步骤,使得第一接合部件和第二接合部件的温度达到30℃和200℃之间。在加热步骤之后,导电合金块的熔点在200℃和800℃之间。在一个示例中,合金块的熔点比第一或第二材料的熔点大至少30摄氏度。
第一材料层可包括在加热之前在第二材料层中不存在的至少一种材料组分。第一保护层和第二保护层可以为类似组成。第一材料层和第二材料层可以为低熔点材料。在一个示例中,第一和第二低熔点材料可以是从锡、铟、镓和/或它们的对应合金中选择的不同材料。第一保护层可以包括铜,并且第二保护层可包括铜、镍、钨、钴、磷、钯、硼、金、银和/或它们对应的合金中的至少一种。
第一导电元件可包括块状导体层和上覆块状导体层的晶种层。第一接合部件可接合至晶种层。该方法可进一步包括:通过晶种层的厚度控制在加热步骤期间温度会升高的第一材料层和第一保护层的熔点。晶种层可包括铜。在加热步骤期间,晶种层还可以与第一材料层和第二材料层一起扩散。在又一示例中,在加热期间,第一材料层的一部分可扩散到块状导体层中。第一导电元件可以包括位于块状导体层和晶种层之间的阻挡层。在这种示例中,阻挡层可以防止第一材料在加热步骤期间扩散到块状导体层中。阻挡层可包括钽、氮化钽、钼、铬-钼、镍、磷、钨、钴、钯、氮化钛、镍磷、钴磷、钛钨、镍钨或它们的组合中的至少一种。
第一衬底可以是限定第一元件的表面的第一支持材料层,并且第一导电元件可以是延伸穿过第一支持材料层的一部分的金属化过孔。在这种示例中,该方法可进一步包括通过在上覆第一元件的表面的光刻胶层的开口内沉积第一材料层来在金属化过孔之上形成第一接合部件,开口与金属化过孔对准。形成第一接合部件的步骤还可以包括:在光刻胶层的开口内沉积第一保护层。
在开口内沉积第一材料层之前,晶种层可以位于第一元件的表面和光刻胶层之间,并且可以进一步上覆金属化过孔的端面。此外,可以在开口内的晶种层上覆沉积第一材料层,并且该方法可进一步包括去除光刻胶层和晶种层的未被第一材料层覆盖的部分。
第一衬底可以是限定第一元件的表面的第一支持材料层,并且第一导电元件可位于第一支持材料层内的开口中。在这种示例中,第一导电元件的端面和第一接合部件可以在开口内凹陷,并且将第一接合部件与第二接合部件对准的步骤可以包括在第一支持材料层的开口内定位第二接合部件。在又一示例中,第一导电元件的端面和第一接合部件可以在孔内凹陷,使得第一保护层的外表面基本与第一支持材料层的表面共面。
本发明的另一方面涉及一种用于制造微电子组件的方法。该方法包括:将第一元件的表面处露出的第一接合部件与第二元件的表面处露出的第二接合部件对准,使得第一接合部件和第二接合部件相互接触。第一元件和第二元件中的每一个元件均包括衬底,并且第一接合部件包括第一材料层和上覆第一材料层的第一保护层。第二接合部件包括第二材料层和上覆第二材料层的第二保护层。该方法进一步包括加热第一接合部件和第二接合部件,使得至少第一材料层和第二材料层一起扩散以形成将第一元件和第二元件接合到一起的合金块。在加热之前合金块的熔点高于第一材料层和第二材料层的熔点。在加热以进一步形成合金块的步骤之前,第一保护层和第二保护层与第一材料层和第二材料层一起扩散。
第一接合部件可环绕第一元件的表面的区域,第二接合部件可环绕第二元件的表面的区域。在这种示例中,将第一接合部件与第二接合部件对准可以在第一接合部件、第二接合部件以及第一元件和第二元件的表面的被环绕部分内限定容积。此外,加热步骤还可以使得内部容积变得被导电合金块密封。
第一元件和第二元件分别包括第一导电元件和第二导电元件,第一导电元件和第二导电元件限定第一元件和第二元件的表面的接合至接合部件的部分,并且加热步骤可以在第一导电元件和第二导电元件之间接合合金块。
附图说明
现在将参照附图描述本发明的各个示例。应该理解,这些附图仅示出了本发明的一些实施例,因此不用于限制其范围。
图1A至图1C示出了与本公开相关的技术中的各种结构;
图2示出了根据本公开一个方面的包括接合形成之前的对应接合部分的元件;
图3示出了根据本发明一个方面的接合图2的元件的合金块;
图4示出了合金接合块的高度范围内的示例性浓度等级;
图5示出了根据本发明另一方面的包括多个导电元件和相关合金块的元件;
图6和图7示出了根据本公开的方法的可用于形成合金块的接合部件;
图8和图9示出了合金块形成方法中的进一步的步骤;
图10至图15示出了根据本公开一个方面的在用于制造接合部件的方法的各个阶段期间的元件;
图16示出了根据本公开另一方面的组件,其具有相邻衬底的合金块接合表面和每个衬底内的导电元件;
图17示出了本公开另一方面的组件,其中接合部件可用于形成利用突出导电元件接合凹陷导电元件的合金块;
图18和图19示出了根据本公开又一方面的组件,其包括图16和图17的部件的组合;
图20至图24示出了可使用利用表面、导电元件和接合部件之间的可变关系的接合部件(诸如上面所讨论的)的结构;以及
图25示出了其中具有加强结构的导电元件之上的接合部件。
具体实施方式
参照附图,其中类似的参考标号用于表示类似的部件。图3示出了根据本公开一个方面的微电子组件10。组件10包括通过合金块16接合到一起的第一和第二元件。在图3中,其示出了接合图2的元件的合金块16,第一和第二元件被示为微电子设备的一部分,其可以是封装微电子元件、中介片、衬底等的形式。例如,第一和第二元件12和14在图2-图3中被示为包括支持材料层18,其例如可以是半导体或介电材料层(诸如在中介片结构中、在部分封装微电子元件中或者在部分半导体裸片中所找到的)。在一个示例中,支持材料层18可以是半导体材料或介电材料或半导体和介电材料的组合中的一种,诸如在图2-图3所示的示例中,其中支持材料层18包括半导体层19,其具有上覆半导体层19的介电层20。在这种示例中,介电层20可用于绝缘形成在支持材料层18的表面28上的布线或其他导电部件。
第一和第二元件12和14可以包括导电元件,其可以是导线、焊盘、柱等。在图2-图3所示示例中,导电元件是金属化过孔22,其包括至少通向表面28的位于支持材料层18中的开口23内的块状导电块26。在各个示例中,开口48可以为盲孔,其终止在支持材料层18内。在其他示例中,开口48可以是完全延伸穿过支持材料层18的过孔。此外,在支持材料层18包括半导体材料的示例中,绝缘层可以包括在块状导电层26和支持材料层18之间的开口48内。金属化过孔22可以被结构化,使得过孔22的端面54在支持材料层18的表面28处露出。如在本公开中参照衬底所使用的,在衬底的表面处“露出”导电元件的表述表示:当衬底不与任何其他元件组装时,导电元件可用于与在垂直于衬底的表面的方向上从衬底外侧朝向衬底表面移动的理论点接触。因此,位于衬底表面处的端子或其他导电元件可以从这种表面突出;可以与这种表面平齐;或者可以相对于这种表面在衬底中的孔或凹部中凹陷。
例如,端面54可以与表面28平齐,或者在表面28下方凹陷。在另一示例中,金属化过孔22的端面54可定位在表面28的外侧,使得边缘面56还在支持材料层的表面28处露出。
如上所述,合金块16可以定位在第一元件12和第二元件14之间以将封装12和14接合到一起。在图3所示示例中,合金块16接合在金属化过孔22的对面(confronting)端面54之间。在这种示例中,合金块16可以是导电的,使得过孔22可以机械且电地接合在一起,从而可以从第一元件12向第二元件14传输电信号等。使用合金块16的接合类型可用于连接第一元件12(例如为封装微电子元件的形式)和第二元件14(中介片等的形式,其可以进一步电连接至用于电子设备或作为部分电子系统的印刷电路板(“PCB”))。在各个示例中,合金块16可根据结构具有大约1000埃至大约2000埃之间的高度H,尽管可以具有更大或更小的高度。
合金块16可包括至少三种材料,它们的相应浓度在单个的合金块16的整个结构中不同。如图4所示,在一个示例中,合金块16可以包括镓(Ga)、铜(Cu)和铟(In),并且合金材料内的这些材料的浓度总体上可以在合金块16的整个结构中不同,至少在第一元件12和第二元件14之间的方向上。如图4的示图所示,镓的量根据与第一元件12的距离而变化,其中朝向元件12设置峰值浓度等级70。在图4的示图所示的具体示例中,合金块16内的镓的峰值浓度等级70可以位于合金块16和第一元件12的过孔22之间的附接点处。
图4所示所有材料的浓度等级是示例性的,并且例如可以通过合金块16连接的元件12和14的结构来影响。通过说明,图4所示示例性组件10包括过孔22,它们均包括位于块状导体层26和合金块16之间的阻挡层32。阻挡层32的存在可以防止合金块16中存在的任何材料扩散到或者以其他方式进入到块状导体层26内。因此,不具有阻挡层的结构可以在整个合金块16的各个位置处具有不同的浓度等级,包括在块状导体层26和合金块16之间的接合界面周围。然而,即使在这种示例中,镓的峰值浓度等级可以位于合金块16和块状导体层26之间的接合界面内或界面处。
类似地,合金块16内的铟的浓度可以在一般设置为朝向第二元件14的位置处具有峰值等级74。此外,如上面参照镓的浓度所讨论的,铟的浓度概况可以偏离图4所示。例如,合金中的铟的浓度可以在接近第一元件12的点处具有峰值。如上所述,这种概况可以依赖于各种因素,包括处理温度、处理时间、初始浓度概况、其他处理条件或者根据组件10的各种结构因素,诸如阻挡层的存在或不存在。此外,合金块16中包括的材料可以变化。例如,合金块16可以包括第一材料,如上所述,其可以为诸如镓的低熔点(“LMP”)材料。一般来说,这种LMP材料具有低于大约250℃的熔点,并且可以包括镓、锡、铟等。在一些示例中,诸如图4的示例中,其中合金块16接合在导电过孔之间,第一材料优选为导电材料。
合金块16包括也为LMP材料的第二材料,其还可以为导电材料,并且可以从任何上面列出的LMP材料中进行选择。在一些示例中,第一和第二材料优选是不同的LMP材料,诸如如上所述,其中第一材料为镓,而第二材料为铟。如上所述,合金块16可以包括第三材料,诸如在图4的示例中为铜。第三材料可以是非LMP材料,诸如熔点大于约160℃的材料。在一些示例中,第三材料可以具有大于300℃的熔点。与第一和第二材料一样,第三材料可以是导电材料,尤其当用于将其他导电部件接合到一起的时候。
当三种材料被扩散到一起时,诸如以类似于图4所示的方式,合金块16可以具有大于其中找到的两种LMP材料的任一种的熔点。此外,合金块16的熔点可以沿着其至少一部分小于300℃,使得通过合金块16形成在第一和第二元件12和14之间的接合可以至少部分地“再加工”。在一个示例中,在再加工接合件中,合金块16可以至少部分地通过加热到小于300℃的温度而回流,使得合金块16的至少一部分熔化,允许元件12和14相对于彼此的部分至少部分地被调整或者进一步允许元件12和14相互分离。
如图4的示图所示,根据所使用的特定LMP材料层的特性,在合金块16的形成期间,LMP材料可以远离表面(诸如过孔22的端面54)迁移。因此,铟的峰值浓度74被示为远离元件14的对应表面54间隔,其下具有铜的增加等级。注意,在一些示例中,铟的峰值浓度可以趋于与镓的峰值浓度颠倒。与其相关联的保护层48的增加厚度可以降低铟或类似材料的迁移并且可以防止这种颠倒。
当用于第一和第二材料的浓度峰值的位置被描述为朝向第一或第二元件12或14中的任一个“设置”时,这种峰值可以接近期望朝向设置的元件12或14。例如,图4中镓的浓度峰值70被描述为朝向第一元件12设置,这可以表示峰值70与第二元件14相比更接近第一元件12。此外,在这种约定下,第二材料(例如图4中所示的镓)的峰值浓度74被描述为朝向第二元件14设置,这可以表示该峰值74与第一元件12相比更接近第二元件14。可选地,朝向元件12或14中的一个或另一个设置可以表示这种峰值与其他材料的峰值浓度相比更接近这种元件12或14。例如,在图4的示例中,镓的峰值浓度70可以认为是朝向第一元件12设置,因为其比铟的峰值浓度74更接近第一元件,反之亦然。
可选地,材料的峰值浓度是否朝向元件12或14设置可以通过这种峰值浓度是否在与元件的特定距离(诸如合金块16的整个高度的百分比距离)内来确定。例如,镓的峰值你浓度70可以被认为是朝向第一元件12设置,因为其在第一元件12的小于第一元件12和第二元件14之间的距离(或者分别为第一元件12和第二元件14的过孔22的端面54之间的距离)的50%的距离内。在又一些示例中,这种百分比距离可以小于元件12和14之间的总距离的25%,或小于10%。
如图4进一步所示,第三或非LMP材料也可以具有峰值浓度,诸如图4的示图所示的铜的峰值浓度72。如图所示,非LMP材料的峰值浓度72可以位于第一和第二LMP材料(在图4的示例中分别为镓和铟)的峰值浓度70和74之间。因此,当确定LMP材料的峰值浓度70或74以相对关系朝向哪个元件12或14设置时,该峰值浓度70或74可以比另一LMP材料的峰值浓度74或70和非LMP材料的峰值浓度72更接近该元件12或14。
合金块16内的材料的分布和相对浓度可以通过合金块16利用其形成在元件12和14之间的方法来影响。根据本公开的一个方面,在图6至图9中示出了用于制造接合在第一元件12和第二元件14中的金属化过孔22的对面端面54之间并电连接端面54的合金块16的方法。在图6中,第一元件12的一部分被示为具有金属化过孔22,金属化过孔22至少部分地穿过支持层18并在其面板28处露出。阻挡层32上覆过孔内的块状导体26,并且在该示例中,限定金属化过孔22的端面54。如上所述,金属化过孔22可以不具有阻挡层,使得通过块状导体26来限定端面54。块状导体可以是导电金属,诸如铜、镍、钨或包括这些或其他适当材料的各种合金。如果存在的话,阻挡层32可以是诸如氮化钽(TaN)、钼、钼-铬等的材料。晶种层34可以任选地形成在阻挡层和/或块状导体26之上。晶种层可用于利于在阻挡层32之上形成附加层,例如在特定材料的块状导体26之上。晶种层还可以用于贡献以该方法或类似方法形成的合金块16的各种特性,如以下所讨论的。在其他情况下,诸如当块状导体26是铜且不存在阻挡层时,可以不需要晶种层34。如果存在的话,晶种层34可以是铜或类似导电金属,并且可以根据以下讨论的标准来选择。
第一LMP材料36上覆至少块状导体26,其中上述阻挡层32和/或晶种层34任选地定位在块状导体26和第一LMP材料层36之间。LMP材料层36可以包括任何上面列出的LMP材料。LMP层36可以包括单个LMP材料(诸如镓,如上面参照图4所描述的示例),或者与诸如铜等的其他金属进行组合。例如,LMP层可以是镓的单层、镓-铜合金的单层、铟-镓-铜合金的单层或者具有镓和铜的多个子层、或者预定配置的镓、铜和铟等的一个或多个子层的结构,以为LMP材料层36给出LMP材料36的期望总体百分比,其还可以在层36的整个高度中创建LMP材料的梯度浓度等级。如此,如本文其他地方限定的,LMP材料层本身可以不具有“低”熔点,但是可以包含本文讨论的一种LMP材料的期望量。
第一保护层38可以上覆第一LMP材料层36并且可以包括与块状导体26、晶种层34或LMP材料层36中包括的任何非LMP材料类似的材料。在其他示例中,硒闪光层可用于保护层38。例如,保护层38可以为LMP材料层34提供针对氧化等或者处理元件12期间的损伤的保护。如上面参照4进一步讨论的,保护层还可以提供完成合金块16内的非LMP材料的源的至少一部分。如以下讨论的,保护层38的厚度,具体为相对于LMP材料层和/或晶种层34的相对厚度可以影响合金块16形成的后续步骤期间接合部分30的行为。在一个示例中,保护层38可以具有大约200埃的厚度,尽管可以例如根据上述标准使用更厚或更薄的保护层38。可以使用电镀、无电镀、蒸镀、化学气相沉积(“CVD”)等来形成第一接合部分30或任何其他类型接合部分的各个层。
与第一接合部分30一样,第二接合部分40可以接合至第二元件14或以其他方式与第二元件14连接。在图7所示示例中,第二接合部分40上覆至少穿过第二元件14的支持材料层18的一部分的金属化过孔22的端面54。类似于第一接合部分30,第二接合部分40可以任选地包括晶种层44,其可以上覆过孔22的块状导体25,并且过孔22可以任选地包括位于晶种层44和块状导体26之间的阻挡层42。阻挡层42和晶种层44可以具有与上面参照图6讨论的阻挡层32和晶种层34类似的结构和类似的组成。
第二接合部分40进一步包括上覆第二元件14的过孔22并且进一步上覆阻挡层42和晶种层44(当结构中存在的话)的LMP材料层46。LMP材料层46可以包括上文参照图4讨论的一种LMP材料,并且可以进一步包括不同于LMP材料层36的LMP材料。例如,如图4所示,LMP材料可以包括铟。此外,LMP材料46可以包括附加材料,诸如铜等的导电金属。LMP材料层46内的任何附加非LMP材料可以以合金的形式与LMP材料混合并且可以包括在LMP材料层46的多个子层中,其可以被配置为在层46内提供期望的材料浓度和/或在层46的整个厚度中提供期望的材料梯度。
如图8所示,第一元件12和第二元件14可以被定位为使得相应的表面29相互面对,并且使得第一接合部分30与第二接合部分40对准并沿着其保护层38和48相互接触。然后,至少接合部分30和40可以被加热到预定温度,以使得相应LMP材料层36和46内的LMP材料熔化并消耗在保护层38和48、晶种层34和44或者在LMP材料层36和46自身的任何一个中找到的非LMP材料。在这种加热期间,合金块16可以形成为消耗的非LMP材料变成在LMP材料的液相中悬浮的固态颗粒并且形成为液体LMP材料混合到一起。这种混合物将具有针对混合物整体的对应熔点,其将根据组成的百分比(重量或原子量)而变化,在该点处,非LMP材料也将熔化到混合物中并且整个系统将处于液相。类似地,诸如镓的LMP材料(其熔点低于诸如铟的另一LMP材料)可以在其熔点(在镓的示例中为30℃)之上但是在另一LMP材料的熔点(对于铟来说为大约156℃)之下消耗另一LMP材料。
在接合部分30和40的一些变型中,可以不需要保护层38或48。例如,在接合部分30和40的变型中,其中LMP材料36包括LMP材料和非LMP材料的图案的多个镀层,这些层的最上部可以是保护的非LMP材料,诸如铜。在其他变型中,LMP材料36或46的组成可以是梯度合金结构,至少足够的保护材料在其上部附近以取消对于分别的保护层38和48的需求。在该变型以及可能的其他变型(诸如保护层是在加热期间蒸发的易失性材料)中,LMP材料层的材料可以不与任何保护层材料扩散。在其他情况下,保护层可以不是必须的,诸如当第一和第二元件12和14在具有低氧等级的环境中形成和组装时或者在可以发生氧化之前形成和组装到一起时。
此外,可以被液体LMP材料消耗的非LMP材料的量随着系统的温度而变化。即,用于消耗这种系统内的非LMP材料的温度随着非LMP材料的量的增加而增加。因此,接合部分30和40内的LMP材料与非LMP材料的比率增加,消耗保护层36和46所要求的温度增加,因此增加接合部分30和40的对应材料和组成变得充分混合以形成接合至第一元件12和第二元件14的合金块16所要求的温度。如图4的示例性示图所示,混合物不需要同质以实现合金块16的形成,但是至少应该消耗所有的保护层38和48。在一些示例中,合金块16可以在暴露给禁止(proscribed)温度的10分钟和30分钟之间的时间之后充分形成。这可以允许合金块16内的材料足够混合为使得当冷却时,第一和第二元件将接合到一起,并且在图9的组件10的情况下,相应元件12和14的过孔22电连接到一起。
由于用于合金块16形成所需的温度随着接合部分30和40内包括的非LMP材料的量而增加,所以该温度(可以称为“接合温度”)可以通过接合部分30和40中存在的保护层38和48以及任何晶种层(诸如晶种层34和44)的厚度来控制。通过从上文列出的材料中选择各种材料并通过调整接合部分30和40内的各种LMP材料和非LMP材料的相对量,可以在30℃至150℃的范围内实现焊接温度。在参照图6至图9讨论的示例中,其中第一LMP材料包括铟,第二LMP材料包括镓,并且晶种层34和44以及保护层38和48为铜,晶种层的初始厚度可以为30-600nm,镓的第一材料层的初始厚度可以为100-500nm,并且保护层的初始厚度可以为10-100nm。类似厚度可用于第二接合部分40。在接合部分30和40的变型中(在LMP材料层36或46中包括非LMP材料),这种非LMP材料与LMP材料的比例还可以影响接合部分30和40的接合温度。
来自接合部分30和40的各个层的材料一起扩散到合金块16产生具有较高熔点(高于其中包括的LMP材料(诸如上述示例所使用的镓和铟)的熔点)的结构。此外,一旦合金块16冷却和固化,其随后的熔点可以高于在其形成中所使用的焊接温度。对于接合部分30和40内的层的上文列出的材料的各种组合可以使得接合部分30和40具有在上文给出的范围内的焊接温度,其可以形成具有也在上文给出的范围内的熔化温度的合金块16。接合部分的特定焊接温度以及所生成的合金块16的熔化温度可以通过如上所述调整接合部分30和40的组成的相对比例来控制或调整。换句话说,可以选择非LMP材料以增加包括非LMP材料和至少一种其他LMP材料的合金的熔点。
根据各种标准,接合部分30和40的选择性组成可以被设计为控制其适当的焊接温度和所得到的合金块16的熔化温度。例如,可以期望其形成可以在可达到的温度处再加工的合金块16而不对相关元件(诸如元件12或14)的其他部分引起损伤或者甚至不会使得相同封装10等内的其他接合本身变得再加工。这种标准可以利用相对较高的LMP材料和非LMP材料组成的比率来实现。类似地,期望可用于一些接合部分,它们用于形成合金块以具有低焊接温度,使得它们可以被熔化并接合到一起而不引起已经形成的接合件或接合回流或受损伤。另一方面,可以期望用于一些合金块16,它们被用于将元件接合到一起以具有相对较高的熔化温度,使得它们更加耐受更高温度的应用或者在创建随后的合金块16或组件中的其他接合件期间不会回流。接合部分30和40可以根据上述标准来制造以实现这些特性并且在用于形成它们的合金块16中实现这种特性。
如上所述,这种合金块16可用于接合元件,其中元件在其各个部件处具有多个不同的微电子应用。在上述示例中,合金块16被用于电且机械地接合元件中的导电过孔22,其中元件可以是中介片、微电子裸片、封装微电子元件等。虽然只有单个合金块16被示为连接至每个第一元件12和第二元件14中的对应金属化过孔22,但这种组件10可以在每一个第一元件和第二元件中包括多个金属化过孔22,其中对应的合金块16附接在相应的多个过孔22之间。这种过孔可以以微电子组件或封装微电子设备中使用的任何数量的结构来配置,诸如以过孔22(例如,隔开最小间距等)的行和列的阵列进行配置。可以使用本文讨论的类型的合金块来接合类似阵列中的其他部件,诸如接合焊盘与一个或多个其他导电部件(诸如导线等)或者导电销或柱(可以上覆接触焊盘并与接合焊盘电连接)等连接。
在其他应用中,这种部件可以与大量焊料或其他接合金属接合,这要求接合部件之间的最小间距至少为该部件的宽度的1.5倍(如图1C所示)。如图5所示,上述的接合部分30和40可用于通过在应用中形成合金块16来接合导电部件,其中导电部件位于具有小于导电部件本身的宽度的最小间距P的阵列中。此外,在导电部件(形成有大量导电接合材料)之间具有接合件的组件中,这种焊料、接合高度或元件之间的间距可以直接与用于这种导电部件所需的宽度相关。即,较大的接合高度需要导电部件的较大宽度。在使用用于接合导电部件的前述合金块16的结构中,这种部件可以具有小于6μm的宽度W,并且在一些情况下小于3μm,接合高度例如大于6μm,尽管更大的宽度也是可以的。在相应的接合界面处具有减小的宽度的导电部件的使用还可以产生一种结构,其可以更加可靠地制造为在导电部件的界面表面处具有较少的凹陷。如图1B所示,与其他接合结构连接所使用的大接触焊盘2由于形成这种元件的凹陷或其他步骤而可以沿着表面3显示出凹陷(或者形成凸面)。这会导致降低接合件可靠性,无论在制造还是使用这种元件期间。
前文示例中讨论的类型的接合部分30和40可以通过图10至图15所示的方法形成在导电部件上。在该具体示例中,接合部分30和40被示为形成在至少部分地穿过支持结构18的导电过孔22的端面54之上。这种元件可以通过在半导体或介电层中形成孔、如果需要的话涂覆这种孔以及在其中沉积导电金属来制造。这种孔可以是盲孔,并且可以源于与表面28相对的表面。在这种方法中,在半导体层19之上沉积介电层20之前,半导体层19可以反转并被蚀刻以露出过孔的端部,其可以被抛光以露出金属化过孔22的端面54,以实现图10所示的结构。尽管在图10的封装中仅示出了单个过孔22,但可以使用类似方法在封装中同时形成多个过孔。还可以使用过孔形成的其他方法。
如图11所示,如果期望阻挡层32、42和/或晶种层34、44,则可以在元件12的表面28之上沉积这些层所期望的材料的层32’和34’。光刻胶层52可以位于表面28之上并且位于元件12上所具有的任何接合材料层32’或晶种材料层34’之上,并且开口50可以形成或以其他方式存在于光刻胶层52中,其覆盖过孔22或期望接合部分30的任何其他位置。根据上述任何组成,LMP材料层36可以沉积在开口50内,然后保护层38可以沉积在LMP材料层36之上。然后,可以去除光刻胶层52,在期望位置中在元件12上留下期望数量的接合部分30。随后,可以剥离掉LMP材料层36外的接合材料层32’和晶种材料层34’的部分。如图15所示,类似方法可用于在元件14上制造接合部分40。然后,如上所述,将元件12和14对准并加热以制造合金块16。类似方法可用于在其他导电部件(诸如焊盘、柱等)上制造类似的接合部分。
上文讨论的创建用于将元件接合到一起的合金块的类型的接合部分可在上面讨论的元件的变型中使用,诸如图16所示,其中附接合金块116被用于在不包括导电部件的表面28的部分处将封装112和114的支持材料层118接合到一起。如图所示,可以在相同的封装中使用一些合金块116以接合诸如金属化过孔122的导电元件,尽管在一些应用中,合金块116可用于仅沿着表面128接合元件112和114。通过在光刻胶层52内包括不覆盖任何导电部件的开口50,通过上述相同的方法可以制造接合至表面128的合金块116。在图16所示的又一变型中,可以沿着表面128在一个或多个横向上延伸合金块116,使得合金块116可以与表面128的对面部分一起限定内部容积。在一些应用中,该类型的单个连续合金块116可以完全包围该内部容积,并且在又一示例中密封该容积。
如图17所示,与上文描述类似的接合部分230和240可以上覆导电过孔222或者在一个元件212中凹陷并且在另一元件214中从表面228之上突出的其他部件。在变型中,根据接合部分240在与过孔222相关联的开口内凹陷的深度,封装212的过孔222可以与表面228平齐并且只有接合部分230可以从表面228之上突出。在任意形式中,这种布置可以导致接合部分230和240在组装期间自对准。一旦接合部分230和240被对准,它们就可以熔化,如上所述以制造将元件212和214接合到一起的合金块。在图18和图19示出了这种组件的又一些变型,其中,图18的组件310与图17的示例相同包括突出和凹陷的过孔22,连同参照图16描述的表面接合的接合部分330和304一起。如图19所示,这种接合部分430和440可进一步被用于包括边缘芯片结构462的组件410中。
此外,如图20至图23所示,用于导电部件和相关接合部分的各种不同结构在上文讨论的框架内都是可能的,在图20至图24中示出其示例。如图20所示,过孔522的端面524可以凹陷到表面528下方,使得LMP材料536或546还可以位于表面528下方,保护层538或548与表面528对准或平齐。在图21的示例中,只有LMP材料层636或646的部分可以位于表面529下方,剩余部分从其之上突出,使得保护层538或548位于表面528之上。图22示出了一种变型,其中接合部分730或740可以沿着LMP材料736或746的部分呈锥形,使得保护层738或748沿着其部分包括顶点739。图23示出了一种变型,其中块状导体826的一部分从表面828之上突出,其中接合部分830或840形成在其上并在表面828之上隔开。这种结构可用于在元件之间提供更大的间隔,或者创建自对准部件(如参照图17所讨论的)。在又一可选示例中,图24示出了接合部分930位于导电柱962上。这种结构可用于与接合至导电焊盘、另一柱等的另一接合部分连接。
如图25所示,本文所讨论的类型的一个或两个接合部分可以包括强化结构来帮助接合部分在上述焊接或回流期间保持其形状。在一个示例中,在图25中,接合部分1030被示为在导电过孔1022的块状导体上。多个毛细结构1058从金属化过孔1022的块状导体层1026的端面1054突出。毛细结构1058可以是柔性材料(诸如聚酰亚胺等),并且可以是耐热至少达到接合部分1030的预期焊接温度的材料。毛细结构1058可以在端面1054上隔开,使得接合部分1030可以与金属化过孔22进行足够的电连接。此外,毛细结构1058可以具有充分的大小和密度,使得接合部分1030的表面张力在熔化时保持期望用于接合部分1030和所得合金块的一般成形。因此,接合部分1030可以通常形成为比不具有毛细元件的类似组成的接合部分具有更高的接合温度。毛细结构1058的任何柔性可以使得毛细结构耐受在其组装期间元件之间的压力下的断裂等。毛细结构1058可以通过在晶种层1034之上沉积聚酰亚胺层、然后将聚酰亚胺层图案化为毛细结构1058的期望形状和密度并露出晶种层来形成。此外,晶种层1034的存在可以使得块状导体1022内的金属间结构的形成最小化。
尽管参照具体实施例进行了描述,但应该理解,这些实施例仅是本公开的原理和应用的说明。因此,应该理解,可以对所示实施例进行多种修改并且可以得到其他配置而不背离所附权利要求限定的本公开的精神和范围。
Claims (53)
1.一种微电子组件,包括:
第一衬底,具有表面和第一导电元件;
第二衬底,具有表面和第二导电元件;以及
导电合金块,接合至所述第一导电元件和所述第二导电元件,其中,所述导电合金块包括第一材料、第二材料和第三材料,所述第三材料被选择为增加包括所述第三材料以及所述第一材料和所述第二材料中的至少一种材料的合金的熔点,其中所述第一材料的浓度从朝向所述第一导电元件设置的位置处的相对较大量向朝向所述第二导电元件的相对较小量变化,并且其中所述第二材料的浓度从朝向所述第二导电元件设置的位置处的相对较大量向朝向所述第一导电元件的相对较小量变化。
2.根据权利要求1所述的组件,其中所述第一衬底和所述第二衬底中的至少一个为半导体材料和介电材料中的至少一种材料。
3.根据权利要求1所述的组件,其中所述合金块具有小于5微米的厚度。
4.根据权利要求1所述的组件,其中所述第一材料和所述第二材料中的至少一种材料的浓度从相对较大浓度向相对较小浓度单调地变化。
5.根据权利要求1所述的组件,其中所述第三材料包括铜、镍、钨、钴、磷、钯、硼、金和银中的至少一种。
6.根据权利要求1所述的组件,其中所述第一材料的相对较大浓度的位置与所述第一导电元件相邻。
7.根据权利要求1所述的组件,其中所述第一材料和所述第二材料中的每一种材料在未与所述第三材料合金化的状态下均具有小于200摄氏度的熔点。
8.根据权利要求7所述的组件,其中所述第一材料和所述第二材料中的一种材料具有小于50℃的熔点。
9.根据权利要求1所述的组件,其中由所述第三材料以及所述第一材料和所述第二材料中的至少一种材料形成的合金的熔点比所述第一材料和所述第二材料的熔点高至少30℃。
10.根据权利要求1所述的组件,其中所述第一材料不同于所述第二材料,并且所述第一材料和所述第二材料包括锡、铟或镓中的至少一种。
11.根据权利要求1所述的组件,其中所述第一导电元件包括块状导体块,所述导电合金块上覆所述块状导体块,并且其中所述第一材料的一部分扩散到所述块状导体块中。
12.根据权利要求11所述的组件,其中所述第一导电元件还包括上覆所述块状导体块的阻挡层,所述导电合金块接合至所述阻挡层。
13.根据权利要求1所述的组件,其中所述第一衬底包括半导体材料和介电材料中的至少一种材料的第一支持材料层,所述支持材料层限定所述第一衬底的表面,并且其中所述第一导电元件是延伸穿过所述第一支持材料层的一部分并且在所述第一表面处露出的金属化过孔。
14.根据权利要求13所述的组件,其中所述金属化过孔的一部分位于所述第一支持材料层的外部。
15.根据权利要求14所述的组件,其中所述第二元件包括半导体材料或介电材料中的至少一种材料的第二支持材料以及限定所述第二元件的表面的层,其中所述第二导电元件是延伸穿过所述第二支持材料层的一部分的金属化过孔,所述第二元件的至少一部分位于所述表面处,并且其中所述导电合金块的至少一部分设置在所述第二支持材料层内。
16.根据权利要求1所述的组件,其中所述第一导电元件和所述第二导电元件在与所述导电合金块的相应接合界面处均具有小于25微米的宽度。
17.根据权利要求1所述的组件,其中所述第一导电元件和所述第二导电元件在与所述导电合金块的相应接合界面处均具有小于3微米的宽度。
18.根据权利要求1所述的组件,其中所述第一元件包括多个第一导电元件,所述第二元件包括多个第二导电元件,并且其中多个导电合金块接合在相应的所述第一导电元件和所述第二导电元件之间。
19.根据权利要求18所述的组件,其中所述第一导电元件均具有一宽度,并且其中所述第一导电元件在横向上相互隔开的间距小于所述第一导电元件的宽度。
20.根据权利要求1所述的组件,其中所述第一导电元件包括在朝向所述第二元件的方向上延伸的多个毛细结构,所述导电合金块环绕并接合至所述多个毛细结构中的至少一些单个的毛细结构。
21.根据权利要求1所述的微电子组件,其中所述第一元件包括限定所述第一元件的表面并在横向上延伸的衬底,所述第一导电元件为远离所述表面延伸的柱的形式。
22.根据权利要求1所述的微电子组件,其中所述第一元件还包括与所述第一导电元件电连接的微电子元件。
23.一种微电子组件,包括:
第一衬底,限定表面并具有形成在其中的第一元件;
第二衬底,限定表面并具有形成在其中的第二元件;以及
合金块,接合至所述第一元件和所述第二元件的表面,其中所述合金块包括第一材料、第二材料和第三材料,其中所述第一材料的浓度从朝向所述第一元件设置的位置处的相对较大量向朝向所述第二元件的相对较小量变化,其中所述第二材料的浓度从朝向所述第二元件设置的位置处的相对较大量向朝向所述第一元件的相对较小量变化,其中所述合金块的熔点大于所述第一材料处于未合金状态的熔点并且大于所述第二材料处于未合金状态的熔点。
24.根据权利要求23所述的组件,其中所述导电合金块环绕在所述第一元件和所述第二元件的表面的对面部分之间限定的内部容积。
25.根据权利要求24所述的组件,其中所述内部容积被密封。
26.根据权利要求23所述的组件,其中所述第一元件和所述第二元件分别包括第一导电元件和第二导电元件,所述第一导电元件和所述第二导电元件限定所述第一元件和所述第二元件的表面的接合至所述导电合金块的部分。
27.一种用于制造微电子组件的方法,包括:
将第一接合部件与第二接合部件对齐,使得所述第一接合部件和所述第二接合部件相互接触,所述第一接合部件包括在第一元件中,所述第一元件具有限定表面和所述表面处的第一导电元件的衬底,所述第一接合部件包括与所述第一导电元件相邻的第一材料层和上覆所述第一材料层的第一保护层,所述第二接合部件包括在第二元件中,所述第二元件包括限定表面和在所述表面处露出的第二导电元件的衬底,所述第二接合部件包括与所述第二导电元件相邻的第二材料层和上覆所述第一材料层的第二保护层;以及
加热所述第一接合部件和所述第二接合部件,使得所述第一材料层和所述第二材料层的至少一部分一起扩散以形成将所述第一元件和所述第二元件相互接合的合金块。
28.根据权利要求27所述的方法,其中以第一温度执行加热步骤,并且其中所述合金块具有处于大于所述第一温度的第二温度的熔点。
29.根据权利要求27所述的方法,其中在加热以进一步形成所述合金块的步骤期间,所述第一保护层和所述第二保护层与所述第一材料层和所述第二材料层一起扩散。
30.根据权利要求27所述的方法,其中执行加热步骤,使得所述第一接合部件和所述第二接合部件的温度达到30℃和200℃之间。
31.根据权利要求30所述的方法,其中在加热步骤之后,所述导电合金块具有在200℃和800℃之间的熔点。
32.根据权利要求27所述的方法,其中所述第一材料层包括在加热之前在所述第二材料层中不存在的至少一种材料组分。
33.根据权利要求27所述的方法,其中所述第一保护层和所述第二保护层为类似组成。
34.根据权利要求27所述的方法,其中所述第一材料层和所述第二材料层的熔点低于由来自所述第一材料层和所述第二材料层的材料以及所述第一保护层和所述第二保护层形成的合金的熔点。
35.根据权利要求34所述的方法,其中所述第一材料不同于所述第二材料,并且所述第一材料和所述第二材料包括锡、铟或镓中的至少一种。
36.根据权利要求35所述的方法,其中所述第一保护层包括铜,并且其中所述第二保护层包括铜、镍、钨、钴、磷、钯、硼、金和银中的至少一种。
37.根据权利要求27所述的方法,其中所述第一导电元件包括块状导体层和上覆所述块状导体层的晶种层,所述第一接合部件接合至所述晶种层。
38.根据权利要求37所述的方法,包括:基于所述晶种层的厚度控制所述第一材料层和所述第一保护层的熔点。
39.根据权利要求37所述的方法,其中所述晶种层包括铜。
40.根据权利要求37所述的方法,其中在加热步骤期间,所述晶种层还与所述第一材料层和所述第二材料层一起扩散。
41.根据权利要求37所述的方法,其中在加热期间,所述第一材料层的一部分扩散到所述块状导体层中。
42.根据权利要求37所述的方法,还包括:在所述块状导体层和所述晶种层之间提供阻挡层,所述阻挡层防止所述第一材料在加热步骤期间扩散到所述块状导体层中。
43.根据权利要求42所述的方法,其中所述阻挡层包括钽、氮化钽、钼、铬-钼、镍、磷、钨、钴、钯、氮化钛、镍磷、钴磷、钛钨、镍钨或它们的组合中的至少一种。
44.根据权利要求27所述的方法,其中所述第一衬底是限定所述第一元件的表面的第一支持材料层,以及其中所述第一导电元件是延伸穿过所述第一支持材料层的一部分的金属化过孔,所述方法还包括通过在上覆所述第一元件的表面的光刻胶层的开口内沉积所述第一材料层来在所述金属化过孔之上形成所述第一接合部件,所述开口与所述金属化过孔对齐。
45.根据权利要求44所述的方法,其中形成所述第一接合部件的步骤还包括:在所述光刻胶层的开口内沉积所述第一保护层。
46.根据权利要求44所述的方法,还包括:
在所述开口内沉积所述第一材料层之前,在所述第一元件的表面和所述光刻胶层之间定位晶种层,并进一步上覆所述金属化过孔的端面,
在所述开口内的所述晶种层之上沉积所述第一材料层,以及
去除所述光刻胶层和所述晶种层的未被所述第一材料层覆盖的部分。
47.根据权利要求27所述的方法,其中所述第一衬底是限定所述第一元件的表面的第一支持材料层,并且其中所述第一导电元件位于所述第一支持材料层内的开口中,所述第一导电元件的端面和所述第一接合部件在所述开口内凹陷,并且其中将所述第一接合部件与所述第二接合部件对齐的步骤包括在所述第一支持材料层的开口内定位所述第二接合部件。
48.根据权利要求27所述的方法,其中所述第一衬底是限定所述第一元件的表面的第一支持材料层,并且其中所述第一导电元件位于所述第一支持材料层的开口内,所述第一导电元件的端面和所述第一接合部件在所述开口内凹陷,使得所述第一保护层的外表面基本与所述第一支持材料层的表面共面。
49.一种用于制造微电子组件的方法,包括:
将第一元件的表面处露出的第一接合部件与第二元件的表面处露出的第二接合部件对齐,使得所述第一接合部件和所述第二接合部件相互接触,所述第一元件和所述第二元件中的每一个元件均包括衬底,所述第一接合部件包括第一材料层和上覆所述第一材料层的第一保护层,并且所述第二接合部件包括第二材料层和上覆所述第二材料层的第二保护层;以及
加热所述第一接合部件和所述第二接合部件,使得至少所述第一材料层和所述第二材料层一起扩散以形成将所述第一元件和所述第二元件接合到一起的合金块,在加热之前所述合金块的熔点高于所述第一材料层和所述第二材料层的熔点。
50.根据权利要求49所述的方法,其中在加热以进一步形成所述合金块的步骤之前,所述第一保护层和所述第二保护层与所述第一材料层和所述第二材料层一起扩散。
51.根据权利要求49所述的方法,其中所述第一接合部件环绕所述第一元件的表面的区域,其中所述第二接合部件环绕所述第二元件的表面的区域,并且其中将所述第一接合部件与所述第二接合部件对齐以在所述第一接合部件、所述第二接合部件以及所述第一元件和所述第二元件的表面的被环绕部分内限定容积。
52.根据权利要求51所述的方法,其中加热步骤还使得所述内部容积变得被所述导电合金块密封。
53.根据权利要求49所述的方法,其中所述第一元件和所述第二元件分别包括第一导电元件和第二导电元件,所述第一导电元件和所述第二导电元件限定所述第一元件和所述第二元件的表面的接合至接合部件的部分,并且其中加热步骤在所述第一导电元件和所述第二导电元件之间接合所述合金块。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/692,148 | 2012-12-03 | ||
US13/692,148 US9024205B2 (en) | 2012-12-03 | 2012-12-03 | Advanced device assembly structures and methods |
PCT/US2013/072675 WO2014088966A2 (en) | 2012-12-03 | 2013-12-02 | Advanced device assembly structures and methods |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105122447A true CN105122447A (zh) | 2015-12-02 |
CN105122447B CN105122447B (zh) | 2017-07-04 |
Family
ID=49877011
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201380071665.5A Active CN105122447B (zh) | 2012-12-03 | 2013-12-02 | 用于包括通过接合包含覆盖低熔点材料层的非低熔点材料层的两个接合部件而形成的高熔点合金的微电子组件的接合结构以及对应制造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US9024205B2 (zh) |
EP (1) | EP2920810A2 (zh) |
KR (1) | KR101583609B1 (zh) |
CN (1) | CN105122447B (zh) |
TW (1) | TW201436150A (zh) |
WO (1) | WO2014088966A2 (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9237648B2 (en) | 2013-02-25 | 2016-01-12 | Invensas Corporation | Carrier-less silicon interposer |
CN104022090B (zh) * | 2013-02-28 | 2018-01-23 | 日月光半导体制造股份有限公司 | 半导体接合结构及方法,以及半导体芯片 |
US9691693B2 (en) | 2013-12-04 | 2017-06-27 | Invensas Corporation | Carrier-less silicon interposer using photo patterned polymer as substrate |
US9972593B2 (en) | 2014-11-07 | 2018-05-15 | Mediatek Inc. | Semiconductor package |
US9548273B2 (en) | 2014-12-04 | 2017-01-17 | Invensas Corporation | Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies |
TWI620485B (zh) * | 2014-12-09 | 2018-04-01 | 英特爾公司 | 具有銅合金導電線路結構之微電子基板 |
JP6227803B2 (ja) * | 2014-12-09 | 2017-11-08 | インテル・コーポレーション | 銅合金導電性経路構造体を備えるマイクロ電子基板 |
US9437536B1 (en) | 2015-05-08 | 2016-09-06 | Invensas Corporation | Reversed build-up substrate for 2.5D |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US10211160B2 (en) | 2015-09-08 | 2019-02-19 | Invensas Corporation | Microelectronic assembly with redistribution structure formed on carrier |
US9666560B1 (en) | 2015-11-25 | 2017-05-30 | Invensas Corporation | Multi-chip microelectronic assembly with built-up fine-patterned circuit structure |
EP3208028B1 (en) * | 2016-02-19 | 2021-04-07 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. | A method and device for reversibly attaching a phase changing metal to an object |
US9620434B1 (en) | 2016-03-07 | 2017-04-11 | Toyota Motor Engineering & Manufacturing North America, Inc. | High temperature bonding processes incorporating metal particles and bonded substrates formed therefrom |
TWI822659B (zh) | 2016-10-27 | 2023-11-21 | 美商艾德亞半導體科技有限責任公司 | 用於低溫接合的結構和方法 |
US10446441B2 (en) | 2017-06-05 | 2019-10-15 | Invensas Corporation | Flat metal features for microelectronics applications |
CN107267832B (zh) * | 2017-06-13 | 2019-03-22 | 清华大学 | 一种温控不可逆相变多孔液态金属材料及其制备和应用 |
US11244916B2 (en) | 2018-04-11 | 2022-02-08 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
US10790262B2 (en) | 2018-04-11 | 2020-09-29 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03106564A (ja) * | 1989-09-18 | 1991-05-07 | Fujitsu Ltd | フラックスレスはんだ接合方法 |
US20020090756A1 (en) * | 2000-10-04 | 2002-07-11 | Masamoto Tago | Semiconductor device and method of manufacturing the same |
US20030215981A1 (en) * | 2002-05-14 | 2003-11-20 | Motorola Inc. | Solder compositions for attaching a die to a substrate |
US20070166875A1 (en) * | 2005-12-29 | 2007-07-19 | Intel Corporation | Method of forming a microelectronic package and microelectronic package formed according to the method |
US20080029888A1 (en) * | 1999-11-01 | 2008-02-07 | International Business Machines Corporation | Solder Interconnect Joints For A Semiconductor Package |
CN101681888A (zh) * | 2007-06-04 | 2010-03-24 | 株式会社村田制作所 | 电子零部件装置及其制造方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3141238A (en) | 1960-11-22 | 1964-07-21 | Jr George G Harman | Method of low temperature bonding for subsequent high temperature use |
US3839727A (en) * | 1973-06-25 | 1974-10-01 | Ibm | Semiconductor chip to substrate solder bond using a locally dispersed, ternary intermetallic compound |
JPH0266953A (ja) | 1988-08-31 | 1990-03-07 | Nec Corp | 半導体素子の実装構造およびその製造方法 |
GB8920101D0 (en) * | 1989-09-06 | 1989-10-18 | Marconi Electronic Devices | Methods of joining components |
US5280414A (en) * | 1990-06-11 | 1994-01-18 | International Business Machines Corp. | Au-Sn transient liquid bonding in high performance laminates |
JP3297177B2 (ja) | 1993-12-22 | 2002-07-02 | 株式会社東芝 | 半導体装置の製造方法 |
US5985692A (en) | 1995-06-07 | 1999-11-16 | Microunit Systems Engineering, Inc. | Process for flip-chip bonding a semiconductor die having gold bump electrodes |
US6330967B1 (en) * | 1997-03-13 | 2001-12-18 | International Business Machines Corporation | Process to produce a high temperature interconnection |
US6025649A (en) * | 1997-07-22 | 2000-02-15 | International Business Machines Corporation | Pb-In-Sn tall C-4 for fatigue enhancement |
US5990560A (en) * | 1997-10-22 | 1999-11-23 | Lucent Technologies Inc. | Method and compositions for achieving a kinetically controlled solder bond |
US6342442B1 (en) * | 1998-11-20 | 2002-01-29 | Agere Systems Guardian Corp. | Kinetically controlled solder bonding |
JP2000340366A (ja) | 1999-05-27 | 2000-12-08 | Tdk Corp | 発光ダイオード |
GB0307105D0 (en) * | 2003-03-27 | 2003-04-30 | Pillarhouse Int Ltd | Soldering method and apparatus |
US7242097B2 (en) * | 2003-06-30 | 2007-07-10 | Intel Corporation | Electromigration barrier layers for solder joints |
US7060601B2 (en) | 2003-12-17 | 2006-06-13 | Tru-Si Technologies, Inc. | Packaging substrates for integrated circuits and soldering methods |
JP3994980B2 (ja) * | 2004-03-29 | 2007-10-24 | 株式会社日立製作所 | 素子搭載用基板及びその製造方法並びに半導体素子実装方法 |
KR100659579B1 (ko) | 2004-12-08 | 2006-12-20 | 한국전자통신연구원 | 발광 소자 및 발광 소자의 제조방법 |
JP4182996B2 (ja) | 2006-08-10 | 2008-11-19 | ソニー株式会社 | 電子装置及びその製造方法 |
US20080218068A1 (en) | 2007-03-05 | 2008-09-11 | Cok Ronald S | Patterned inorganic led device |
US7777233B2 (en) | 2007-10-30 | 2010-08-17 | Eastman Kodak Company | Device containing non-blinking quantum dots |
AT10735U1 (de) * | 2008-05-21 | 2009-09-15 | Austria Tech & System Tech | Verfahren zur herstellung einer leiterplatte sowie verwendung und leiterplatte |
JP5620698B2 (ja) | 2010-03-29 | 2014-11-05 | 株式会社テラプローブ | 半導体構成体及び半導体構成体の製造方法 |
US8492891B2 (en) | 2010-04-22 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with electrolytic metal sidewall protection |
KR20120091691A (ko) | 2011-02-09 | 2012-08-20 | 삼성전자주식회사 | 휨 방지용 접합패턴을 갖는 반도체 소자 및 그 제조방법 |
US8240545B1 (en) * | 2011-08-11 | 2012-08-14 | Western Digital (Fremont), Llc | Methods for minimizing component shift during soldering |
JP5608824B2 (ja) * | 2011-12-27 | 2014-10-15 | パナソニック株式会社 | 接合構造体 |
-
2012
- 2012-12-03 US US13/692,148 patent/US9024205B2/en active Active
-
2013
- 2013-12-02 KR KR1020157017369A patent/KR101583609B1/ko active IP Right Grant
- 2013-12-02 WO PCT/US2013/072675 patent/WO2014088966A2/en active Application Filing
- 2013-12-02 CN CN201380071665.5A patent/CN105122447B/zh active Active
- 2013-12-02 EP EP13811692.6A patent/EP2920810A2/en not_active Withdrawn
- 2013-12-03 TW TW102144300A patent/TW201436150A/zh unknown
-
2015
- 2015-04-30 US US14/700,780 patent/US20150231732A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03106564A (ja) * | 1989-09-18 | 1991-05-07 | Fujitsu Ltd | フラックスレスはんだ接合方法 |
US20080029888A1 (en) * | 1999-11-01 | 2008-02-07 | International Business Machines Corporation | Solder Interconnect Joints For A Semiconductor Package |
US20020090756A1 (en) * | 2000-10-04 | 2002-07-11 | Masamoto Tago | Semiconductor device and method of manufacturing the same |
US20030215981A1 (en) * | 2002-05-14 | 2003-11-20 | Motorola Inc. | Solder compositions for attaching a die to a substrate |
US20070166875A1 (en) * | 2005-12-29 | 2007-07-19 | Intel Corporation | Method of forming a microelectronic package and microelectronic package formed according to the method |
CN101681888A (zh) * | 2007-06-04 | 2010-03-24 | 株式会社村田制作所 | 电子零部件装置及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20140153210A1 (en) | 2014-06-05 |
KR101583609B1 (ko) | 2016-01-19 |
TW201436150A (zh) | 2014-09-16 |
KR20150085098A (ko) | 2015-07-22 |
WO2014088966A2 (en) | 2014-06-12 |
EP2920810A2 (en) | 2015-09-23 |
US20220097166A1 (en) | 2022-03-31 |
CN105122447B (zh) | 2017-07-04 |
WO2014088966A3 (en) | 2015-01-15 |
US20150231732A1 (en) | 2015-08-20 |
US9024205B2 (en) | 2015-05-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105122447A (zh) | 用于包括通过接合包含覆盖低熔点材料层的非低熔点材料层的两个接合部件而形成的高熔点合金的微电子组件的接合结构以及对应制造方法 | |
CN101582396B (zh) | 半导体器件及半导体器件的制造 | |
TWI493672B (zh) | 半導體裝置、電子裝置及半導體裝置之製造方法 | |
US7935408B2 (en) | Substrate anchor structure and method | |
TW201232737A (en) | Interconnect structure | |
KR101594220B1 (ko) | 전자 부품, 전자 장치의 제조 방법 및 전자 장치 | |
US20080258277A1 (en) | Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same | |
KR20070035457A (ko) | 열 싱크로의 열 전도를 강화하기 위하여 야금 본드를통합한 집적회로 장치 | |
CN105637633A (zh) | 具有预形成过孔的嵌入式封装 | |
JP2019515511A (ja) | 3d集積デバイスにおける相互接続のためのバリア層 | |
JP2000156457A (ja) | 半導体デバイスの製造方法 | |
KR20110014598A (ko) | 인쇄회로기판을 제조하는 방법, 용도 및 인쇄회로기판 | |
US7411303B2 (en) | Semiconductor assembly having substrate with electroplated contact pads | |
TW201624656A (zh) | 半導體基板及具有半導體基板之半導體封裝結構 | |
CN102290357A (zh) | 键合封装及其方法 | |
CN102239555A (zh) | 包含降低金属柱应力之组构的半导体器件 | |
CN105895603A (zh) | 具有衬底隔离和未掺杂的沟道的集成电路结构 | |
US10629361B2 (en) | Inductance device and method of manufacturing the same | |
US20140374912A1 (en) | Micro-Spring Chip Attachment Using Solder-Based Interconnect Structures | |
KR20200035197A (ko) | 반도체 장치 및 그 제조 방법 | |
KR20160020566A (ko) | 제1 및 제2 구성요소들의 조립 후에 금속 커넥터를 도금함으로써 마이크로전자 조립체를 형성하는 방법 및 대응하는 장치 | |
US7205659B2 (en) | Assemblies for temporarily connecting microelectronic elements for testing and methods therefor | |
CN103681538B (zh) | 半导体芯片及其制造方法和焊接半导体芯片与载体的方法 | |
US11999001B2 (en) | Advanced device assembly structures and methods | |
CN113517246A (zh) | 包括嵌入式焊接连接结构的半导体封装 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |