CN103681538B - 半导体芯片及其制造方法和焊接半导体芯片与载体的方法 - Google Patents

半导体芯片及其制造方法和焊接半导体芯片与载体的方法 Download PDF

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CN103681538B
CN103681538B CN201310532609.9A CN201310532609A CN103681538B CN 103681538 B CN103681538 B CN 103681538B CN 201310532609 A CN201310532609 A CN 201310532609A CN 103681538 B CN103681538 B CN 103681538B
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sublayer
chip
metallization
semiconductor chip
semiconductor
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CN103681538A (zh
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N·厄施勒
K·特鲁诺夫
F·翁巴赫
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及半导体芯片及其制造方法和焊接半导体芯片与载体的方法。公开了一种半导体芯片，具有半导体本体和施加到半导体本体上的芯片金属化，该芯片金属化具有背离半导体本体的下侧。具有数目为N1≥1或者N1≥2的第一子层以及数目为N2≥2的第二子层的层堆叠被施加到下侧上。第一子层和第二子层交替地相继地被布置，使得在能够由第一子层构成的每一个第一对的第一子层之间布置有至少一个第二子层，并且在能够由第二子层构成的每一个第二对的第二子层之间布置有至少一个第一子层。每一个第一子层都具有合金金属或者由合金金属组成，每一个第二子层都具有焊料或者由焊料组成，该焊料能够与邻接有关的第二子层的第一子层的合金金属一起构成金属间相。

Description

半导体芯片及其制造方法和焊接半导体芯片与载体的方法
技术领域
本发明涉及半导体芯片和半导体芯片与载体的金属化的焊接。一些时间以来为焊接半导体芯片与载体的金属化使用扩散钎焊连接。在此，通过使用焊料来焊接半导体芯片的金属化与载体的金属化。在钎焊过程期间金属从半导体芯片和载体的金属化扩散到液态焊料中并且与该液态焊料一起在凝固后构成一种或者多种高强度的和在温度变化下稳定的金属间相。
背景技术
因为金属从半导体芯片和载体的金属化扩散到液态焊料中的扩散过程为达到为构成金属间相所需的混匀需要不可忽略的时间，所以与制造这样的钎焊连接关联的处理时间非常长。此外扩散进入的金属的浓度随离开半导体芯片和载体的各自的金属化的距离增加而降低。由此在熔液的不同的区域内出现不同的化学计算的成分。这导致，熔液在凝固后不仅仅由金属间相组成，而且由很大部分的简单的合金组成，这些合金不具有晶格结构，因此不是金属间相。因为传统的合金相较于金属间相具有较小的强度和较小的温度变化下稳定性所以需要一种改进的解决方案。
发明内容
为此本发明尤其提供一种半导体芯片、一种用于制造半导体芯片的方法以及一种用于制造钎焊连接的方法。本发明的扩展方案和改进方案是从属权利要求的主题。
根据本发明的一个方面，半导体芯片包括半导体本体、被施加到该半导体本体上的芯片金属化、以及层堆叠，该层堆叠被施加到芯片金属化的背离半导体本体的下侧上。层堆叠具有数目为N1≥1或者N1≥2的第一子层，以及数目为N2≥2的第二子层。第一子层和第二子层交替地相继地被布置，使得在能够由第一子层构成的每一个第一对的第一子层之间布置有第二子层中的至少一个，并且在能够由第二子层构成的每一个第二对的第二子层之间布置有第一子层中的至少一个。第一子层中的每一个都具有合金金属或者由合金金属组成。第二子层中的每一个都具有焊料或者由焊料组成，其中该焊料能够与邻接有关的第二子层的第一子层的合金金属一起构成金属间相。相应地，能够与至少一个邻接第一子层的第二子层一起构成金属间相的金属或者合金被理解为该第一子层的“合金金属”。在此，第一子层中的每一个都由与邻接该第一子层的第二子层不同的材料或者不同的材料成分组成。
为了制造这样的半导体芯片，通过每次一个第一子层和每次一个第二子层交替地相继地被施加，在配备有芯片金属化的半导体本体上施加所述层堆叠。为此可以使用任意的涂层技术，例如溅射、蒸镀、气相沉积、电镀、无电流沉积，也可以以任意的彼此组合使用这些涂层技术。
为了将预制的、具有如上所述的半导体芯片的构造的半导体芯片连接到载体上，通过低熔的第二子层的熔化和随后的扩散钎焊过程来连接芯片金属化与载体的金属化的表面区段。第一子层的金属原子和第二子层的金属原子以及表面区段的金属原子的相互扩散导致构成金属间相，这些金属间相具有与低熔的第二子层的一个或者多个熔点相比显著提高的熔点。
通过使用具有多个薄的焊料或者含焊料的低熔的第二子层的层堆叠，在理想情况下实现相互扩散，使得产生连接层，该连接层连接芯片金属化与表面区段，并且该连接层以至少90体积％由一种或者多种金属间相组成。替代地或者附加地，该相互扩散可以导致构成连接层，该连接层具有一条或者多条路径，其中的每一条都连续地在芯片金属化和金属化的表面区段之间延伸并且完全由一种或者多种金属间相组成。在多条路径的情况下，这些路径也可以彼此间隔开，使得连接层的不包含金属间相的区段位于两条任意的路径之间。
与在现有技术的相应连接的情况下不同，不仅来自半导体芯片和载体的金属化的金属有助于构成一种(或多种)金属间相，而且来自第一子层的一种或者多种金属也有助于构成一种(或多种)金属间相。所需要的扩散距离以及随之而来所需要的钎焊时间由此显著缩短。
附图说明
下面借助实施例参考附图更详细地说明本发明。只要不另外说明，在图中相同的附图标记表示相同的或者彼此对应的元件。
图1示出通过电路载体和半导体芯片之间的复合结构(Verbund)的横截面。
图2示出根据图1的视图的放大的部分。
图3示出在焊接半导体芯片与载体之前的根据图2的部分。
图4A-4F示出一种用于制造半导体芯片的方法的不同步骤，该半导体芯片具有施加在其芯片金属化上的层堆叠。
图5示出具有施加在其芯片金属化上的层堆叠的半导体芯片，其中该层堆叠的最接近半导体本体设置的子层是第二子层。
具体实施方式
图1示出电路载体2的横截面，其中半导体芯片1被钎焊到该电路载体2上。电路载体2具有绝缘载体20、例如陶瓷，该绝缘载体配备有上金属化21以及可选的下金属化22。如所示的，上金属化层21可以被结构化为印制导线和/或导线面。然而，替代于这样的电路载体2，一般也可以将例如金属的引线框架(“Leadframe”)用作电路载体2。
如借助根据图2的放大的部分可以识别的，半导体芯片1具有由半导体基材、例如硅、碳化硅、砷化镓或者任意的其他的半导体材料构成的仅示意性示出的半导体本体10。该半导体本体10在其下侧12配备有芯片金属化11。芯片金属化11涉及传统的芯片金属化，其可以由一个层或者多个子层组成，如其通常在半导体芯片技术中被用于制造负载连接金属化那样。这样的负载连接金属化例如可以涉及功率半导体器件的漏极金属化、源极金属化、集电极金属化、发射极金属化、阳极金属化或者阴极金属化。芯片金属化可以与所描述的连接过程协调一致地被适配。特别是可以舍弃对于传统的连接技术、如焊接来说所需的层。例如可以舍弃使用镍层或者含镍的层。另一方面，使用另外的或者附加的、避免第一焊接层与芯片金属化反应的层可能是有利的。
芯片金属化11在其背离半导体本体10的一侧具有下侧15，该下侧的粗糙度显著小于电路载体2的上金属化层21的表面25的粗糙度。因此，当以材料决定的方式连接半导体芯片1与上金属化层21所利用的连接材料5’的量被测定为使得在芯片金属化11和上金属化层21之间不留下任何空隙时，是有利的。换句话说，所使用的连接材料5’的量被测定为使得补偿上金属化层21的表面25的全部不平部。
为了制造如在图1和2中示出的装置，通过扩散钎焊过程利用芯片安装区27来连接半导体芯片与上金属化层21。芯片安装区27通过表面25的区段给出，在该区段上安装半导体芯片1。因此，芯片安装区段27的面积基本上与芯片金属化11的基面相同。
如从图3得知的，在将半导体芯片1扩散钎焊到上金属化层21上之前，给半导体芯片1配备层堆叠5。该层堆叠被施加到芯片金属化11的背离半导体本体10的下侧15上。
层堆叠5包括数目为N1的第一子层31-36以及数目为N2的第二子层41-46。在此，第一子层31-36和第二子层41-46交替地彼此重叠地布置，使得在能够由第一子层31-36构成的每一个第一对的第一子层31-36之间布置有第二子层41-46中的至少一个，并且在能够由第二子层41-46构成的每一个第二对的第二子层41-46之间布置有第一子层31-36中的至少一个。
第一子层31-36中的每一个都具有合金金属或者由合金金属组成。此外，第二子层41-46中的每一个都具有焊料或者由焊料组成，该焊料能够与至少一个与该第二子层41-46邻接的第一子层31-36的合金金属构成金属间相。
由于层堆叠的构造，第二子层41-46中的每一个都邻接第一子层31-36中的至少一个，使得在随后的、第二子层41-46被熔化的钎焊过程中在这些第一子层31-36中所包含的合金金属能够扩散进入到有关的第二子层41-46内，并且由此在熔液凝固后能够有助于构成金属间相。也就是说，配备有层堆叠5的常规的半导体芯片1与层堆叠5一起构成根据本发明修改的半导体芯片1’。
如在图3中通过箭头所示的，修改后的半导体芯片1’为了与上金属化层21焊接而被安放到芯片安装区27上。然后，层堆叠5被加热到全部第二子层41-46熔化的那个时候，使得金属能够从分别邻接的第一子层31-36扩散进入到有关的熔化的第二子层41-46内。在扩散钎焊过程结束后，在半导体芯片1未改变地位于芯片安装区27上期间构成了连续的金属间相，使得在半导体芯片1和上芯片金属化21之间产生固定的钎焊连接。通过钎焊过程，由层堆叠5以及必要时由从芯片金属化11和上金属化层21扩散进入到该层堆叠中的金属构成在图1和2中示出的焊料层5’，该焊料层基本上由金属间相组成，金属间相的熔化温度远高于原来的第二子层41-46的焊料的熔化温度和在先前的扩散钎焊过程中应用的最大温度。
下面参考图4A到4F说明用于制造配备有这样的层堆叠5的半导体芯片1’的方法。出发点是如在图4A中示出的常规的半导体芯片1。半导体芯片1具有带有下侧12的半导体本体10。该下侧12配备有芯片金属化11，该芯片金属化又具有下侧15，该下侧通过芯片金属化11的背离半导体本体10的一侧给出。芯片金属化可以与常规的金属化不同，使得省略为传统的连接技术所使用的层，或者使得使用附加的禁止扩散钎焊过程到达半导体芯片的缓冲层。
在芯片金属化11的该下侧15上，如在图4B中所示的，施加第一子层31。其后在该第一子层31的背离半导体本体10的一侧上施加第二子层41，这作为结果在图4C中示出。然后又在该第二子层41的背离半导体本体10的一侧上施加另一个第一子层32，这作为结果在图4D中示出。现在又跟随另一个第二子层42，它被施加在该另一个第一子层32的背离半导体本体10的一侧上，这作为结果在图4E中示出，等等。
以这种方式，交替地分别相继地彼此重叠地施加第一子层、第二子层、第一子层、第二子层等等，使得产生层堆叠5，如在图4F中所示。以这种方式构成的修改后的半导体芯片1’与在图3中示出的半导体芯片1’相同。为了将第一子层31-36和第二子层41-46施加到芯片金属化11上，可以使用不同的方法，也可以以任意的彼此组合使用这些方法。适宜的方法例如是溅射、蒸镀、气相沉积、电镀或者无电流沉积。
在所示的实例中，层堆叠5的子层中最接近芯片金属化11设置的子层是第一子层31。然而，替代于此，第一个被施加到芯片金属化11上的子层可以是第二子层41，这在图5中示范性地示出。
与层堆叠5的子层31-36、41-46中最接近半导体芯片1设置的子层是第一子层31还是第二子层41无关，第一子层31-36中的每一个以及第二子层41-46中每一个都以垂直于芯片金属化11的下侧15被测量的方式具有在制造过程期间可以调整的厚度。在图4F和5中仅示范性地画出了第一子层31和34的厚度d31和d34以及第二子层41和44的厚度d41和d44。第一子层31-36彼此、第二子层41-46彼此的厚度、以及第一子层31-36的厚度与第二子层41-46的厚度相比基本上都可以彼此独立地选择。这样例如第一子层31-36中的每一个的厚度都可以小于或者等于10μm或者小于或者等于5μm。与此无关地，第二子层41-46中的每一个都可以具有小于或者等于10μm或者小于或者等于5μm的厚度。此外，层堆叠5的全部第一子层31-36的厚度d31-d36的总和可以小于或者等于20μm。与此无关地，层堆叠5的全部第一子层31-36和全部第二子层41-46的厚度d31-d36的总和d5、也就是说层堆叠5的厚度d5至少为0.5μm和/或小于或者等于20μm。
层堆叠5的全部第一子层31-36的厚度d31-d36和层堆叠5的全部第二子层41-46的厚度可以彼此协调一致，使得其在扩散钎焊过程的情况下以最优的方式和最少的时间形成合金的金属间相。
完成的层堆叠5的总厚度d5可以适配于上金属化21的芯片安装面27所具有的表面粗糙度。此外，该厚度d5最大可以为芯片安装面27的表面粗糙度的2倍，以便避免所制造的连接层5的厚度显著大于为平衡芯片安装面27的表面粗糙度所需要的厚度。在此，关于芯片安装区27的表面粗糙度的全部说明涉及根据ENISO4287的平均的粗糙度Rz。
由于制造技术的原因，全部第一子层由相同的金属来制造可能是有利的。相应地，全部第二子层41-46由相同的材料来制造可能是有利的，然而这种材料与第一子层的材料不同。然而，不同的第一子层31-36基本上可以由不同的材料组成。与此无关地，相应的内容也适用于不同的第二子层41-46。层堆叠5的第二子层41-46的数目N2例如可以至少为2或者至少为3。因为制造成本随着非常高数目的子层而升高，所以此外当全部第一和第二子层31-36、41-46的数目N1+N2被选择为小于或者等于11时可能是有意义的。
在层堆叠5的第一子层31-36中的一个、多于一个或者每一个子层中，合金金属可以是铜(Cu)、镍(Ni)、银(Ag)或者金(Au)。
此外，层堆叠5的第二子层41-46中的一个、多于一个或者每一个子层的焊料可以具有下述材料中的一种或者由下述材料中的一种组成：锡(Sn)；锡-银(SnAg)或者金-锡(AuSn)或者另外的锡、锌、或者铅合金。
修改后的半导体芯片1’与上金属化21的焊接例如可以通过如下方式进行，即在钎焊过程期间仅熔化第二子层41-46而不熔化第一子层31-36。为此第二子层中的每一个子层都可以具有熔点，其小于第一子层31-36中的每一个子层的熔点。例如第二子层中的每一子层在Sn焊料的情况下可以具有小于或者等于250℃的熔点，或者在AuSn焊料的情况下具有小于300℃的熔点。在这种情况下过程温度可以被选择为比构成的金属间相的、具有最低熔点的那个金属间相的熔点低。例如该过程温度可以被选择为比450℃低。

Claims (24)

1.半导体芯片(1’)，包括：
半导体本体(10)；
施加在所述半导体本体(10)上的芯片金属化(11)，该芯片金属化具有背离所述半导体本体(10)的下侧(12)；
施加到所述下侧(12)上的层堆叠(5)，该层堆叠具有数目为N1≥1的第一子层(31-36)，以及数目为N2≥2的第二子层(41-46)，其中所述第一子层(31-36)和所述第二子层(41-46)交替地相继地被布置，使得在能够由所述第一子层(31-36)构成的每一个第一对的第一子层(31-36)之间布置有所述第二子层(41-46)中的至少一个，并且在能够由所述第二子层(41-46)构成的每一个第二对的第二子层(41-46)之间布置有所述第一子层(31-36)中的至少一个，
其中，
所述第一子层(31-36)中的每一个都具有合金金属或者由合金金属组成，其中能够与至少一个邻接第一子层的第二子层一起构成金属间相的金属或者合金为该第一子层的合金金属；
所述第二子层(41-46)中的每一个都具有焊料或者由焊料组成，该焊料能够与邻接有关的第二子层(41-46)的第一子层(31-36)的合金金属一起构成金属间相。
2.根据权利要求1所述的半导体芯片(1’)，其中，所述第一子层(31-36)的数目为N1≥2。
3.根据权利要求1或2所述的半导体芯片(1’)，其中，所述第一和第二子层(31-36、41-46)中最接近半导体本体(10)设置的是所述第一子层(31-36)之一。
4.根据权利要求1或2所述的半导体芯片(1’)，其中，所述第一和第二子层(31-36、41-46)中最接近半导体本体(10)设置的是所述第二子层(41-46)之一。
5.根据权利要求1或2所述的半导体芯片(1’)，其中，所述第一子层(31-36)中的每一个都具有小于或者等于10μm的厚度(d31、d34)。
6.根据权利要求5所述的半导体芯片(1’)，其中，所述第一子层(31-36)中的每一个都具有小于或者等于5μm的厚度(d31、d34)。
7.根据权利要求1或2所述的半导体芯片(1’)，其中，所述第二子层(41-46)中的每一个都具有小于或者等于10μm的厚度(d41-d44)。
8.根据权利要求7所述的半导体芯片(1’)，其中，所述第二子层(41-46)中的每一个都具有小于或者等于5μm的厚度(d41-d44)。
9.根据权利要求1或2所述的半导体芯片(1’)，其中，所述第二子层(41-46)中的每一个都具有小于或者等于300℃的熔点。
10.根据权利要求9所述的半导体芯片(1’)，其中，所述第二子层(41-46)中的每一个都具有小于或者等于250℃的熔点。
11.根据权利要求1或2所述的半导体芯片(1’)，其中，N2至少为3。
12.根据权利要求1或2所述的半导体芯片(1’)，其中，所述第一子层(31-36)中的一个、多于一个或者每一个第一子层的合金金属是下述金属之一：铜(Cu)；镍(Ni)；银(Ag)；金(Au)。
13.根据权利要求1或2所述的半导体芯片(1’)，其中，所述第二子层(41-46)中的一个、多于一个或者每一个第二子层的焊料具有下述材料中的一种或者由下述材料中的一种组成：锡(Sn)；锡-银(SnAg)；金-锡(AuSn)或者具有金属锡、锌、和铅中的一种、两种任意的或者三种金属或者由金属锡、锌、和铅中的一种、两种任意的或者三种金属组成的另外的合金。
14.根据权利要求1或2所述的半导体芯片(1’)，其中，所述第二子层(41-46)中的每一个都具有比最接近有关的第二子层(41-46)设置的第一子层(31-36)的熔点更低的熔点。
15.根据权利要求1或2所述的半导体芯片(1’)，其中，全部第一子层(31-36)都由同样的材料组成。
16.根据权利要求1或2所述的半导体芯片(1’)，其中，全部第二子层(41-46)都由同样的材料组成。
17.根据权利要求1或2所述的半导体芯片(1’)，其中，所述层堆叠(5)具有至少0.5μm且小于或者等于20μm的厚度(d5)。
18.根据权利要求1或2所述的半导体芯片(1’)，其中，所述层堆叠(5)具有小于或者等于20μm的厚度(d5)。
19.用于制造根据上述权利要求之一构造的半导体芯片(1’)的方法，具有步骤：
提供半导体本体(10)，将芯片金属化(11)施加到该半导体本体上，所述芯片金属化具有背离所述半导体本体(10)的下侧(12)；以及
通过以下方式将具有数目为N1的第一子层(31-36)以及数目为N2的第二子层(41-46)的层堆叠(5)施加到所述下侧(12)上，即每次一个第一子层(31-36)和每次一个第二子层(41-46)交替地彼此重叠地被施加，使得在完成的层堆叠(5)中在能够由所述第一子层(31-36)构成的每一个第一对的第一子层(31-36)之间布置有所述第二子层(41-46)中的至少一个，并且在能够由所述第二子层(41-46)构成的每一个第二对的第二子层(41-46)之间布置有第一子层(31-36)中的至少一个，其中，
所述第一子层(31-36)中的每一个都具有合金金属或者由合金金属组成，其中能够与至少一个邻接第一子层的第二子层一起构成金属间相的金属或者合金为该第一子层的合金金属；
所述第二子层(41-46)中的每一个都具有焊料或者由焊料组成，该焊料能够与最接近有关的第二子层(41-46)设置的第一子层(31-36)的合金金属一起构成金属间相。
20.用于焊接半导体芯片(1’)与载体(2)的方法，包括步骤：
提供具有金属化(21)的载体(2)；
提供根据上述权利要求之一构造的半导体芯片(1’)；
通过制造被布置在芯片金属化(11)和金属化(21)的表面区段(27)之间的连接层来连接所述芯片金属化(11)与所述表面区段(27)，其中该连接层以至少90体积％由一种或者多种金属间相组成，通过熔化全部第二子层(41-46)来制造所述连接层。
21.用于焊接半导体芯片(1’)与载体(2)的方法，包括步骤：
提供具有金属化(21)的载体(2)；
提供根据权利要求1到18之一构造的半导体芯片(1’)；
通过制造被布置在芯片金属化(11)和金属化(21)的表面区段(27)之间的连接层来连接所述芯片金属化(11)与所述表面区段(27)，其中该连接层具有至少一条路径，该路径连续地在所述芯片金属化(11)和所述金属化(21)的表面区段(27)之间延伸，并且完全由一种或者多种金属间相组成。
22.根据权利要求20或者21所述的方法，其中，所述表面区段(27)具有表面粗糙度(Rz)，并且其中，所述层堆叠(5)具有厚度(d5)，该厚度最大为所述表面粗糙度(Rz)的2倍。
23.根据权利要求20或21所述的方法，其中，所述表面区段(27)具有至少0.5μm的表面粗糙度。
24.根据权利要求20或21所述的方法，其中，最大的为了熔化全部第二子层(41-46)所应用的钎焊温度低于一种金属间相的熔点，或者低于两种或者更多种金属间相中的每一种的熔点。
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