CN105097905A - 绝缘栅双极晶体管 - Google Patents

绝缘栅双极晶体管 Download PDF

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CN105097905A
CN105097905A CN201510247679.9A CN201510247679A CN105097905A CN 105097905 A CN105097905 A CN 105097905A CN 201510247679 A CN201510247679 A CN 201510247679A CN 105097905 A CN105097905 A CN 105097905A
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semiconductor
semiconductor layer
drift region
dopant
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CN105097905B (zh
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R.巴布尔斯克
F.J.尼德诺斯泰德
F.D.普菲尔施
V.范特里克
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Infineon Technologies AG
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Abstract

绝缘栅双极晶体管。根据本发明的一个示例,半导体部件包括半导体本体,其具有顶表面和底表面。第一pn结形成在体区和漂移区之间的过渡处。场截止区被布置在漂移区下面并邻接漂移区。利用与漂移区相同掺杂类型的掺杂剂来掺杂场截止区。然而,场截止区中的掺杂剂的浓度高于漂移区中的掺杂剂的浓度。由第一和第二半导体层构成的至少一对半导体层被布置在漂移区中。第一半导体层基本平行于半导体本体的顶表面延伸并用第一掺杂类型的掺杂剂掺杂,但是具有高于漂移区的掺杂剂浓度。第二半导体层被布置成邻近或者邻接第一半导体层并且用第二掺杂类型的掺杂剂掺杂。此外,第二半导体层被结构化成包括开口,使得通过漂移区提供垂直电流路径而没有居间pn结。

Description

绝缘栅双极晶体管
技术领域
本公开涉及具有改善的短路鲁棒性(robustness)的绝缘栅双极晶体管(IGBT)的领域。
背景技术
由并联连接的多个晶体管单元构成的垂直绝缘栅双极晶体管(IGBT)是功率半导体部件领域中已知的。在此类垂直IGBT中,电子电流在从半导体管芯的顶表面(或正面表面)到底表面(或背面表面)的垂直方向上流过半导体管芯,而空穴电流在相反的方向上流动。在n沟道IGBT的情况下,p掺杂的集电极区(在n沟道IGBT的情况下也称为p发射极区)位于半导体管芯的背面,在那里它被电连接到集电极电极。在每个晶体管单元中p掺杂的体区和n掺杂的源区被设置在半导体管芯的正面,由此每个单个晶体管单元的两个区域都连接到发射极电极。还已知的是提供所谓的场截止区(fieldstopregion),其邻接在半导体管芯的背面的p掺杂的集电极区。利用与集电极区相反掺杂类型的掺杂剂来掺杂场截止区。此外,在场截止区中的掺杂剂的浓度明显高于在所谓的漂移区中的掺杂剂的浓度,所述漂移区通过半导体管芯从在管芯的背面的场截止区延伸到在管芯的正面的体区。
通常,场截止区可以被提供在例如半导体部件中,所述半导体部件在关断状态具有在半导体管芯的正面的具有阻断pn结(在体区和漂移区之间)的垂直pnp结构。当施加的阻断电压如此高以致电场(或空间电荷区,也称为耗尽区)将向下延伸到半导体管芯的背面时,于是需要所提到的场截止区来避免将导致晶体管击穿的电场的“穿通”。场截止区比相邻的漂移区稍微更重地掺杂,并且减小在半导体管芯的背面处的电场,以及避免所提到的穿通。
当晶体管处于短路操作中时,即当晶体管在高集电极-发射极电压下操作同时大于阈值电压的栅极-发射极电压被施加到晶体管的栅电极时,电场的峰值可能出现在场截止区中。电场的此类峰值可能导致半导体部件的局部击穿并由此导致IGBT的毁坏。此外,在漂移区(邻接MOS沟道和体区)的正面的太低的电场可能在晶体管处于短路模式中时激励电流细丝的形成。这种电流细丝可能导致IGBT的局部热点和热毁坏。
发明内容
本文描述了一种半导体部件。根据本发明的一个示例,半导体部件包括半导体本体,其具有顶表面和底表面。利用第二掺杂类型的掺杂剂掺杂的体区被布置在半导体本体的顶表面处。漂移区被布置在体区下面并且用第一掺杂类型的掺杂剂掺杂,第一掺杂类型与第二掺杂类型互补。由此,第一pn结形成在体区和漂移区之间的过渡处。场截止区被布置在漂移区下面并邻接漂移区。利用与漂移区相同掺杂类型的掺杂剂来掺杂场截止区。然而,场截止区中的掺杂剂的浓度高于漂移区中的掺杂剂的浓度。由第一和第二半导体层构成的至少一对半导体层被布置在漂移区中。第一半导体层基本平行于半导体本体的顶表面延伸并用第一掺杂类型的掺杂剂掺杂,但是具有高于漂移区的掺杂剂浓度。第二半导体层被布置成邻近或者邻接第一半导体层并且用第二掺杂类型的掺杂剂掺杂。此外,第二半导体层被结构化成包括开口,使得通过漂移区提供垂直电流路径而没有居间pn结。
根据本发明的另一示例,半导体部件包括半导体本体,其具有顶表面和底表面。利用第二掺杂类型的掺杂剂掺杂的体区被布置在半导体本体的顶表面处。漂移区被布置在体区下面。漂移区用第一掺杂类型的掺杂剂掺杂,第一掺杂类型与第二掺杂类型互补。由此,第一pn结形成在体区和漂移区之间的过渡处。场截止区被布置在漂移区下面并邻接漂移区。利用与漂移区相同掺杂类型的掺杂剂来掺杂场截止区。然而,场截止区中的掺杂剂的浓度高于漂移区中的掺杂剂的浓度。至少一个第一半导体层被布置在漂移区中。第一半导体层基本平行于半导体本体的顶表面延伸并用第一掺杂类型的掺杂剂掺杂,但是具有高于漂移区的掺杂剂浓度。而且,第一半导体层位于漂移区的上部分中,其垂直地延伸到半导体本体中不超过半导体本体的总垂直厚度的40%。
附图说明
参考下面的图和描述可以更好地理解本发明。各图中的部件不一定按比例;而是将重点放置在说明本发明的原理上。而且,各图中类似的参考数字指定对应的部分。在图中:
图1示出常规绝缘栅双极晶体管(IGBT)单元的一个示例的截面图;
图2示意性地示出在场截止IGBT的示例性短路操作期间的电场强度和在图1的IGBT内的垂直位置上的对应施主(donor)浓度;
图3示出在漂移区中包括第一掺杂层的IGBT单元的一个示例的截面图,第一掺杂层具有与漂移区相同的掺杂类型,但是掺杂剂的浓度高于邻接的漂移区;
图4示出类似于图3的示例的IGBT单元,其具有邻接第一掺杂层并用与第一掺杂层的掺杂类型互补的掺杂类型的掺杂剂掺杂的第二掺杂层;
图5示出图4的示例的较小修改;
图6与图4的示例相同,除了第一和第二层的顺序被互换以外;
图7类似于图4的示例,其中多个第一和第二掺杂层被布置在漂移区中;
图8类似于图3的示例,其中多个第一掺杂层被布置在漂移区中;
图9类似于图4的示例,其中第一和第二掺杂层两者都在横向方向上被结构化;以及
图10是具有另外的第一掺杂层的与图4的示例基本相同的另一实例。
具体实施方式
图1示出具有场截止区的垂直n沟道IGBT的一个示例性晶体管单元。根据本示例,IGBT被集成在利用n型掺杂剂掺杂的半导体本体(衬底)中。在本示例中,栅电极G被设置在沟槽17中,该沟槽17从半导体本体的正面沿垂直方向延伸到半导体本体中。栅电极G通过隔离层18(也称为栅极氧化物)与周围的半导体材料隔离。
p掺杂的体区11形成在半导体本体的正面。体区11垂直延伸到半导体本体中并邻接沟槽17。然而,体区11没有像沟槽17那样延伸到半导体本体中如此深。在半导体本体的顶表面(前表面)处,体区11一般被更重掺杂。体区的重掺杂部分可以称为体接触区12,其也是利用p型掺杂剂掺杂的。n掺杂的源区13邻接半导体本体的顶表面(前表面)以及沟槽17,使得其余的体区垂直地位于源区13和低n掺杂的漂移区10之间。漂移区10通过大部分半导体本体向下延伸到其背面,在那里它邻接n掺杂的场截止区14(场截止层)。场截止区14位于漂移区10和集电极区15之间,其用p型掺杂剂掺杂并邻接半导体本体的后表面,在那里它被集电极电极C电接触。发射极电极E电连接到源区13和体接触区12,由此将源区13和体接触区12之间的pn结短路。
在晶体管关断的情况下(即当栅电极被放电或者相对于体区11的电势处于负电势并且存在低于晶体管的击穿电压的集电极-发射极电压时),空间电荷区(或耗尽区)在体区11和漂移区10之间的pn结处增强(buildup)。由于漂移区具有比较低的(n型)掺杂剂浓度(浓度ND在图2的图中被标记为n-),所以空间电荷区可以远远延伸到半导体本体中(取决于集电极-发射极电压)并且可以向下到达场截止层14(有时称为缓冲层),其具有比漂移区10更高的掺杂剂浓度(浓度ND在图2的图中被标记为n)。
如图1中所示,在沟槽17的右侧,晶体管单元可以具有浮置p区16,其将相邻单元分开。然而,相邻单元可以代替地被其它结构(例如无源沟槽)分开或者直接彼此邻接。
对IGBT的一个设计目标是抵抗短路事件的鲁棒性,即当连接到IGBT的负载被短路并且由此整个操作电压被施加在集电极和发射极端子之间、同时晶体管处于导通状态时。IGBT可以承受这种短路状况达一些时间(即几微秒)。已经观察到在短路操作期间,电场强度的峰值可以出现在场截止层14的边缘(margin)附近,其可能导致局部击穿并由此导致器件的毁坏(参见图2中的示例,在处于大约85%的垂直位置处的峰值场强度EMAX)。此外,在漂移区10的前面(即漂移区10的邻接体区11的部分,参见图2中的示例,在大约40%以下的垂直位置),在电场强度(电场强度EQPL)在短路操作期间太低的情况下可能出现电流细丝。在场截止层14处的最大电场强度可以降低,并且可以通过增加集电极区15中的p型掺杂剂的浓度和/或通过降低场截止层14中的n型掺杂剂的浓度来增加在漂移区10的前面部分中的低电场强度。然而,这些措施将分别引起较高的开关损耗和降低的击穿电压,这是不希望有的。可替换地,漂移区10中的掺杂剂浓度可以增加,其将引起降低的最大阻断电压。从上面的讨论可以看出,关于开关损耗、最大阻断电压和短路鲁棒性存在目标冲突。下面的示例可以解决该目标冲突或至少改善该情况。在图2的图中,这意味着在该图左侧的低电场强度水平被提高并且在右侧的峰值被降低,而没有明显增加损耗。在图2中,以半导体本体的总厚度H的百分比给出半导体本体内的位置x(也参见图1)。
图3中示出的示例与先前图1的示例基本相同。然而,IGBT具有布置在漂移区10中的附加第一半导体层20。利用与相邻的漂移区10相同掺杂类型的掺杂剂掺杂第一半导体层20(在本示例n沟道IGBT中是n型掺杂剂)。然而,第一半导体层20中的掺杂剂的浓度高于相邻漂移区10中的掺杂剂的浓度。第一半导体层20中的掺杂剂的浓度的绝对值依赖于漂移区10中的掺杂剂的浓度。通常,对于硅IGBT,第一半导体层20中的掺杂剂的剂量可以在1·1011cm-2和1·1012cm-2之间选择。在短路操作期间,布置在漂移区10中的第一半导体层20增大了漂移区10的前面部分中的电场,并且由此降低了漂移区10和场截止区14之间的过渡区中的最大电场强度的峰值。因此,改善了短路鲁棒性。然而,通过引入第一半导体层20降低了最大阻断电压。可以通过提供第二半导体层21来补偿后一影响,所述第二半导体层21(直接)邻接漂移区10中的第一半导体层20(或者位于其附近,与其紧密相邻)。利用与第一半导体层20的掺杂类型互补的掺杂类型(在本示例中是p型掺杂剂)的掺杂剂来掺杂第二半导体层21。所得到的IGBT结构在图4中示出。如提到的,第二半导体层21可以直接邻接第一半导体层20。可替换地,第一半导体层20和第二半导体层21可以布置成彼此相邻,即间隔开比较小的距离b,其小于第一半导体层20的垂直尺寸(厚度t)的例如两倍或五倍。后一示例在图5中示出,其与图4的示例基本相同,除了第一和第二半导体层20、21未彼此邻接,而是被定位成以(垂直)距离b紧挨着。
为了实现第二半导体层的补偿效应,第一半导体层20中的n型掺杂剂的剂量和第二半导体层21中的p型掺杂剂的剂量未相差超过30%。
尽管第一半导体层20可以平行于半导体本体的顶表面连续延伸(沿水平方向),但是邻接的第二半导体层21可以被结构化并且包括开口以避免贯穿整个半导体本体在第一和第二半导体层20、21之间(或者在第二半导体层21和漂移区10的下部分之间)的阻断pn结,其将使得器件不操作。然而,第二半导体层21中的p型掺杂剂至少部分地补偿第一半导体层20中的附加的n型掺杂剂。因此,可以减小或避免上面提到的IGBT的最大阻断电压(击穿电压)的降低。在图4的示例中,第二半导体层21布置在第一半导体层20下面,而在图6的替换示例中,第一和第二半导体层的位置被互换,从而第二半导体层21被布置在第一半导体层20上面。
在图3至6的示例中,第一半导体层20被布置在离半导体本体的顶表面(前表面)一定距离d处。距离d可以从总厚度H(即半导体本体的正面表面和背面表面之间的距离)的大约5%变动到40%。在图2至4的示例中,第一和第二半导体层20、21中的上面的一个与沟槽17的底部间隔开。然而,沟槽17的底部也可以向下到达(或者延伸通过)半导体层20和/或21。
多个第一和第二半导体层20、21可以被布置在漂移区10中,如图7的示例中所示。在本示例中,p掺杂的第二半导体层21被布置在对应的n掺杂的第一半导体层20下面,其中每个第二半导体层21邻接对应的第一半导体层20或者位于离它小的距离处。然而,第二半导体层21还可以被布置在对应的第一半导体层上面,如图6的示例中所示。第一和第二半导体层20、21的相邻的对可以沿垂直方向间隔开。
在图8的示例中,多个第一半导体层20布置在漂移区10中并且沿垂直方向彼此间隔开。类似于图2的示例,没有p掺杂的第二半导体层在本实例中被提供用于补偿n掺杂的第一半导体层20。
图9示出IGBT单元的另一示例,其与图4的示例基本相同。然而,不同于图4,第一(n掺杂的)半导体层20沿横向方向以类似于第二(p掺杂的)半导体层21的方式被结构化。然而,两个半导体层20、21的横向结构(图案)不一定是相同的。在多于两个第一和第二层(如图7和8中所示)的情况下,该横向结构可以对于所有层是相同的。此外,第一和第二半导体层20、21中的至少一个或全部的横向结构可以匹配半导体本体的背面的横向结构(例如与其是一致的或者与其互补)。针对横向结构化的背面的示例是具有局部增强的掺杂浓度的集电极区15(p发射极区)、如在反向导通IGBT(也称为RC-IGBT)中的中断的p发射极区和横向结构化的场截止区。最后,第一和第二层20、21可以在芯片的边缘区域中被中断(被结构化成包括开口)。贯穿芯片区的横向结构化的选择适用于本文描述的所有实施例。
图10示出附加示例,其与图4的示例相同,除了附加的第一半导体层20被布置在该对第一和第二半导体层下面以外。此示例说明了第一和第二半导体层20、21不一定必须成对提供,例如图7中所示的。作为替换,附加的(结构化的)p掺杂层21可以被布置在漂移区,而不是n掺杂层20中。也就是说,成对的第一和第二半导体层20、21被提供在漂移区中加上一个或多个附加的n掺杂的半导体层20或者一个或多个附加的p掺杂的半导体层21。相邻的层可以彼此邻接(例如图10中所示的)或者被置成以小的距离b彼此邻近(例如图5或7中所示的)。
在上面描述的示例中,第一和第二半导体层20、21可以使用外延、质子注入、离子注入、掺杂剂扩散或其任何组合来制造。尽管上面描述的示例涉及n沟道IGBT,但是所描述的技术特征也可以通过使用互补的掺杂类型以类似的方式用在p沟道IGBT中。本文描述的原理和技术特征也可以应用在反向导通的IGBT中,其在集电极侧不具有连续的p掺杂区(集电极区或p发射极区),而是具有附加的n掺杂条。另外,对不同于IGBT的在其背面具有场截止区的半导体部件的应用可以是有用的。
尽管已经关于一个或多个实施方式示出和描述了本发明,但是在不脱离所附权利要求的精神和范围的情况下,可以对所示示例进行改变和/或修改。具体而言,关于由上述部件或结构(组件、器件、电路、系统等)执行的各种功能,用于描述这种部件的术语(包括对“装置”的引用)旨在对应于(除非另外说明)执行所描述的部件的指定功能的任何部件或结构(例如,其是功能上等效的),即使在结构上不等效于在本发明的本文所示的示例性实施方式中执行该功能的所公开的结构。
另外,尽管可能已经关于几个实施方式中的仅一个公开了本发明的特定特征,但是这种特征可以与其它实施方式的一个或多个其它特征组合,这对于任何给定的或特定的应用来说可能是期望的和有利的。此外,就在具体实施方式和权利要求的任一个中使用术语“包含”、“包括”、“具有”、“含有”、“带有”或其变型来说,此类术语旨在以类似于术语“包括”的方式是包含性的。

Claims (21)

1.一种半导体部件,包括:
具有顶表面和底表面的半导体本体;
利用第二掺杂类型的掺杂剂掺杂的体区,所述体区被布置在半导体本体的顶表面处;
布置在体区下面的漂移区,所述漂移区用与第二掺杂类型互补的第一掺杂类型的掺杂剂掺杂,由此在体区和漂移区之间的过渡处形成第一pn结;
布置在漂移区下面并邻接漂移区的场截止区,所述场截止区用与漂移区相同掺杂类型的掺杂剂掺杂,并且场截止区中的掺杂剂的浓度高于漂移区中的掺杂剂的浓度;和
布置在漂移区中的由第一和第二半导体层构成的至少一对半导体层,所述第一半导体层基本平行于半导体本体的顶表面延伸并用第一掺杂类型的掺杂剂掺杂,但是具有高于漂移区的掺杂剂浓度,所述第二半导体层邻近或者邻接第一半导体层并且用第二掺杂类型的掺杂剂掺杂,所述第二半导体层被结构化成包括开口,使得通过漂移区提供垂直电流路径而没有居间pn结。
2.根据权利要求1所述的半导体部件,还包括:
布置在场截止区和半导体本体的底表面之间的集电极区,所述集电极区用第二掺杂类型的掺杂剂掺杂。
3.根据权利要求1所述的半导体部件,还包括:
嵌入体区中并邻接半导体本体的顶表面的源区,所述源区用第一掺杂类型的掺杂剂掺杂。
4.根据权利要求1所述的半导体部件,还包括:
相对于半导体本体被电隔离并布置成邻近源区和漂移区之间的体区的栅电极。
5.根据权利要求1所述的半导体部件,其中所述至少一对半导体层的第一半导体层被布置在第二半导体层上面。
6.根据权利要求1所述的半导体部件,其中所述至少一对半导体层的第一半导体层被布置在第二半导体层下面。
7.根据权利要求1所述的半导体部件,其中第一半导体层和第二半导体层定位成以一定的垂直距离彼此邻近。
8.根据权利要求7所述的半导体部件,其中所述垂直距离等于或小于第一半导体层的垂直尺寸的五倍。
9.根据权利要求1所述的半导体部件,其中第一半导体层位于漂移区的上部分中。
10.根据权利要求9所述的半导体部件,其中漂移区的上部分垂直地延伸到半导体本体中不超过半导体本体的总垂直厚度的40%。
11.根据权利要求1所述的半导体部件,还包括:
由布置在漂移区中的另外的第一和另外的第二半导体层构成的半导体层的至少一个另外的对。
12.根据权利要求1所述的半导体部件,还包括:
布置在漂移区中的至少一个另外的第一和/或至少一个另外的第二半导体层。
13.根据权利要求1所述的半导体部件,其中第一半导体层基本平行于顶表面并且位于离所述顶表面一定距离处,其大约在半导体本体的厚度的5%和40%之间。
14.根据权利要求1所述的半导体部件,其中第一半导体层基本平行于顶表面并且位于离所述顶表面一定距离处,其大约在半导体本体的厚度的10%和30%之间。
15.根据权利要求13所述的半导体部件,其中一对或多对半导体层位于离所述顶表面一定距离处,其大约在半导体本体的厚度的5%和40%之间。
16.根据权利要求1所述的半导体部件,其中第二半导体层中的掺杂剂的剂量与第一半导体层中的掺杂剂的剂量未相差超过30%。
17.根据权利要求4所述的半导体部件,其中栅电极布置在从半导体本体的顶表面延伸到半导体本体中的沟槽中。
18.根据权利要求1所述的半导体部件,其中第一和第二半导体层的至少一对在横向上被结构化。
19.一种半导体部件,包括:
具有顶表面和底表面的半导体本体;
利用第二掺杂类型的掺杂剂掺杂的体区,所述体区被布置在半导体本体的顶表面处;
布置在体区下面的漂移区,所述漂移区用与第二掺杂类型互补的第一掺杂类型的掺杂剂掺杂,由此在体区和漂移区之间的过渡处形成第一pn结;
布置在漂移区下面并邻接漂移区的场截止区,所述场截止区用与漂移区相同掺杂类型的掺杂剂掺杂,并且场截止区中的掺杂剂的浓度高于漂移区中的掺杂剂的浓度;和
布置在漂移区中的至少一个第一半导体层,所述第一半导体层基本平行于半导体本体的顶表面延伸并用第一掺杂类型的掺杂剂掺杂,但是具有高于漂移区的掺杂剂的浓度,
其中,第一半导体层位于漂移区的上部分中,其垂直地延伸到半导体本体中不超过半导体本体的总垂直厚度的40%。
20.根据权利要求19所述的半导体部件,还包括布置在漂移区的上部分中的至少一个另外的半导体层,所述至少一个另外的半导体层定位成邻近第一半导体层。
21.根据权利要求19所述的半导体部件,其中所述至少一个第一半导体层在横向上被结构化。
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