CN104992901B - 用于提供在低温衬底上的薄膜的横向热处理方法 - Google Patents

用于提供在低温衬底上的薄膜的横向热处理方法 Download PDF

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CN104992901B
CN104992901B CN201510261174.8A CN201510261174A CN104992901B CN 104992901 B CN104992901 B CN 104992901B CN 201510261174 A CN201510261174 A CN 201510261174A CN 104992901 B CN104992901 B CN 104992901B
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K·A·施罗德
R·P·文茨
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Abstract

本发明涉及用于提供在低温衬底上的薄膜的横向热处理方法。公开了一种用于以选择性方式热处理最小化吸收薄膜的方法。构图热接触薄膜的两个紧邻的吸收痕。使用脉冲辐射源加热两个吸收痕，并且通过在两个吸收痕之间的传导热处理薄膜。此方法可用于制造薄膜晶体管(TFT)，在其中薄膜是半导体并且吸收器是TFT的源极和漏极。

Description

用于提供在低温衬底上的薄膜的横向热处理方法
本申请是申请日为2011年6月2日、申请号为201180037944.0、名称为"用于提供在低温衬底上的薄膜的横向热处理方法"的专利申请的分案申请。
相关申请的交叉引用
基于35 U.S.C.§119(e)(1)，本申请基于并要求2010年6月2日提交的在临时申请号61/350,765的优先权，在此引入其整个内容作为参考。
技术领域
本发明一般地涉及用于固化衬底上的薄膜的方法，更具体地，涉及用于热处理在低温衬底上的薄膜的方法。
背景技术
一般地，热处理包括烧结、退火、固化、干燥、结晶、聚合、化学反应激发以及调制、掺杂剂驱入、除气等等。半导体薄膜的热处理典型地在高温环境中进行。例如，非晶硅(a-Si)在1100℃退火而硅纳米颗粒膜在900℃下烧结。因此，用于处理半导体薄膜高温要求通常需要使用如烧结的陶瓷或者石英的高温衬底作为承载半导体薄膜的衬底选择。
更不必说，因为成本相对低廉，更期望使用如硅酸硼或者碱石灰的低温衬底作为用于负载半导体薄膜的衬底选择。更期望的衬底材料是塑料(即，聚碳酸酯，聚酰亚胺、PET、PEN等等)或者纸，因为它们的成本更低。
然而，使用可以提供平衡工艺的如炉的设备对于在低温衬底上的半导体薄膜的热处理不是可行的选择。这是因为，退火和烧结大部分半导体薄膜(如果不是全部)要求的温度，明显高于如聚酰亚胺和PET的低温衬底的最大加工温度，该加工温度分别为约450℃和150℃。
本公开提供了一种用于热处理在低温衬底上的薄膜的方法。
发明内容
根据本发明的优选实施例，间隔开的两个吸收痕与位于衬底的顶上的薄膜热接触。利用脉冲辐射加热两个吸收痕，并且来自两个吸收痕的热随后在薄膜的平面内传导到两个吸收痕之间的薄膜以热处理薄膜。
上述工艺可以用于制造薄膜晶体管(TFT)。例如，可以由金属或者陶瓷构成的两个吸收痕被用来形成TFT的源极和漏极并且半导体薄膜被用来形成TFT的有源沟道。
在随后的详细描述中将明白本发明的所有特点和优点。
附图说明
当联系附图阅读时，通过参考示出的实施例的详细描述，将更好地理解本发明本身以及使用的优选模式、另外的目标及其优点，其中：
图1a-1b示出了根据本发明的一个实施例的热处理薄膜的方法；
图2a-2b示出了根据本发明的另一个实施例的热处理薄膜的方法；
图3a-3b示出了根据本发明的一个实施例的热处理在低温衬底上的极薄膜的方法；
图4示出了通过本发明的方法制造的薄膜晶体管(TFT)；
图5示出了硅酸硼玻璃上的e-束涂覆的非晶硅在暴露于脉冲辐射之前和之后的拉曼谱；
图6是示出了本发明的脉冲辐射横向热处理方法的选择性的图；以及
图7示出了来自图4的TFT的漏极电流对漏极-源极电压的图。
具体实施方式
当使用脉冲辐射热处理技术以热处理衬底上的薄膜时，从闪光灯、定向等离子体弧(DPA)、激光器、微波、感应加热器或者电子束发射的脉冲辐射具有优先加热在其衬底上的薄膜的能力。另外，因为衬底的热容量远高于薄膜的热容量，并且加热的时间远短于衬底的热平衡时间，所以衬底可以用作热沉以在热处理之后迅速快速冷却薄膜。
虽然脉冲辐射热处理允许薄膜被加热到比衬底在热平衡处正常承受的温度更高的温度，但是这样的热处理技术一般地依赖于薄膜吸收用于加热薄膜的辐射的能力。因此，当薄膜很薄和/或有点透明时，很难用脉冲辐射热处理技术直接热处理极薄膜，因为极薄膜典型地吸收很少的辐射。因此，要求一种改善的方法以热处理极薄膜。
现在参考附图，具体地参考图1a-1b，根据本发明的一个实施例，示出了用于在极薄膜上提供脉冲辐射热处理的方法。首先，通过公知的真空技术在衬底14上沉积极薄膜12。极薄膜12还可以涂覆或者印刷到衬底14上。极薄膜12可以是完全致密的膜或者颗粒膜。极薄膜12的厚度优选小于10微米。下一步，在极薄膜12的顶上沉积吸收痕11以形成薄膜叠层10，如图1a所示。优选由对脉冲辐射的吸收比极薄膜12更高的材料制造吸收痕11。吸收痕11的实例包括金属或者陶瓷。
当通过光源15瞬间辐射(即，通过脉冲辐射)薄膜叠层10时，优选在极薄膜12之前加热吸收痕11。光源15可以是闪光灯、定向等离子体弧(DPA)、激光器、微波产生器、感应加热器或者电子束。作为结果，通过热的吸收痕11热处理位于吸收痕11之下面以及邻接吸收痕的极薄膜12和衬底14中的区域(阴影区域)，如图1b所示。热处理的在极薄膜12内的距离d1可以是几十微米。
现在参考图2a-2b，根据本发明的另一个实施例，示出了用于在极薄膜上提供脉冲辐射热处理的方法。首先，通过公知的真空技术在衬底24上沉积极薄膜23。极薄膜23还可以涂覆或者印刷到衬底24上。极薄膜23可以是完全致密的膜或者颗粒膜。极薄膜23的厚度优选小于10微米。下一步，在极薄膜23上沉积吸收痕21、22以形成薄膜叠层20，如图2a所示。类似于图1a中的吸收痕11，优选由对脉冲辐射的吸收比极薄膜23更高的材料制造吸收痕21、22。吸收痕21、22的实例包括金属或者陶瓷。
虽然示出了在极薄膜23顶上形成吸收痕21、22，替代地吸收痕21、22可以在极薄膜23之下形成。
一旦暴露到来自光源25的脉冲辐射，优先加热在极薄膜23之上的吸收痕21、22。然后，来自吸收痕21、22的热量传导到吸收痕21、22之下和/或附近的极薄膜23的区域，如图2b所示。在图2b中，位于吸收痕21、22之间的极薄膜23中的区域d2被热处理。可以在吸收痕21和22之间热处理的间隙距离(即，区域d2)一般地大于图1b中的d1，因为其为通过两个吸收痕21、22传导的热量的重叠，并且优选小于100微米。另外，因为在位于吸收痕21和22之间的极薄膜23中的区域通过从两个吸收痕21、22传导的重叠的热量热处理，极薄膜23的热处理倾向于比仅邻近一个吸收痕的薄膜区域更均匀(例如，在图1b中)。
图1a-1b中的衬底14和图2a-2b中的衬底24优选是高温衬底。然而，通过在施加吸收痕之前或者之后施加热传播膜，还可以在低温衬底(即，最大加工温度为150℃或更低)上执行极薄膜的热处理。因为热传播膜的导热性高于低温衬底的导热性，所以在吸收痕被加热之后，热量优先在极薄膜和热传播膜而不是低温衬底的平面内传导。热传播膜还用作热阻挡层以保护低温衬底。另外，在极薄膜平面内的优先热传导增加了相对彼此放置吸收痕的距离。作为结果，更低能量的光脉冲可以用于处理极薄膜，因此使得工艺对低温衬底更加温和。热传播膜一般地比极薄膜厚，并且一般地对用于加热吸收痕的光透明。
现在参考图3a-3b，示出了根据本发明的一个实施例的用于热处理在低温衬底上的极薄膜的方法；首先，通过公知的真空技术在衬底34上沉积热传播膜35。热传播膜35可以涂覆或者印刷到衬底34上。然后，通过公知的真空技术在热传播膜35的顶上沉积极薄膜33。极薄膜33还可以涂覆或者印刷到热传播膜35上。极薄膜33可以是完全致密的膜或者颗粒膜。极薄膜33的厚度优选小于10微米。下一步，在极薄膜33上沉积吸收痕31、32以形成薄膜痕30，如图3a所示。类似于图2a中的吸收痕21、22，优选由对脉冲辐射的吸收比极薄膜33更高的材料制造吸收痕31、32。吸收痕31、32的实例包括金属或者陶瓷。
虽然示出了在极薄膜33顶上形成吸收痕31、32，吸收痕31、32可以在极薄膜33之下形成。虽然示出了在极薄膜33之下形成热传播膜35，但是可以在极薄膜33或者吸收痕31,32的顶上形成热传播膜35。
一旦暴露到来自光源35的脉冲辐射，优先加热在极薄膜33和热传播膜35上的吸收痕31、32。然后，来自吸收痕31、32的热传导到在吸收痕31、32之下和/或附近的极薄膜33和热传播膜35的区域，如图3b所示。在图3b中，位于吸收痕31、32之间的极薄膜33和热传播膜35中的区域d3被热处理。可以在吸收痕31和32之间热处理的间隙的距离优选小于100微米。
存在适合做热传播膜35的主要材料。对于如PET的低温衬底，那些材料可以包括高温聚合物(例如，聚酰亚胺)或者无机涂层，如溅射金属氧化物或者旋涂玻璃(SOG)。对于如聚酰亚胺的高温衬底，用于热传播膜35的更合适的材料包括无机涂层，如溅射金属氧化物或者SOG。优选热传播膜35稍微透明，以便保持极薄膜的透明度并且仍允许选择性加热发生。要求的热传播膜35的厚度是其热特征、下面的低温衬底的厚度和热特性、极薄膜33的期望的处理温度、吸收痕31、32的尺寸和间隔以及输入的辐射加热分布的函数。
向高温衬底施加热传播膜的一种方法是首先向高温衬底施加具有比高温衬底的热导率更低的热导率的聚合物涂层，然后施加热传播膜。此实践防止热量扩散进入导热衬底并且允许极薄膜被处理。聚合物涂层的另一种选择是使用高温、低热导率无机膜以便其在热处理期间可以经受更高的温度。
获得高温、低热导率无机膜的一种方法是通过使用SOG并用多孔颗粒加载使得无机膜多孔化。例如，通过使用加载在SOG中的硅石气凝胶纳米颗粒制造这样的无机膜。产生的无机膜表现出约(或者甚至低于)PET(即，0.24W/m-°K)的热导率。因为气凝胶颗粒具有SOG基质，无机膜比典型的气凝胶膜更耐久。
可以通过改变脉冲辐射的功率和长度调谐极薄膜的热处理。可以使用多个脉冲以及调节脉冲重复频率。可以使用脉冲宽度调制改变脉冲的形状以进一步调节加热分布。当脉冲长度比低温衬底的热平衡时间更短时，即，垂直于低温衬底的平面，可以在其中产生更强的热梯度和更高的峰值温度，从而优先加热邻近吸收痕的极薄膜。相对于远离吸收痕的区域，在吸收痕附近的在极薄膜中的温度被更强地增加。另外，脉冲辐射允许峰值处理温度大于衬底的最大平衡加工温度。例如，150微米厚的PET在约35ms中达到跨其厚度的热平衡。因此，用300μS脉冲比用10ms脉冲可以产生更强的热处理梯度以及更高的峰值温度而不破坏低温衬底。100ms脉冲仍能够加热位于吸收痕之间的极薄膜，但是可以保持的峰值温度很接近150℃的其最大平衡加工温度。总之，在不破坏低温衬底时，更长的脉冲在极薄膜中获得的最大峰值温度小于短脉冲，但是横向处理长度同样相对更长。因为极薄膜热处理通常是(阿伦纽斯)Arrhenius性质，即，热处理一般地涉及处理温度乘以时间的指数，处理极薄膜而不破坏低温衬底，更短的脉冲比更长的脉冲更有效。
吸收痕的厚度、宽度和间隔以及极薄膜以及底层的厚度和热特性同样对极薄膜在暴露于脉冲辐射之后所见的加热分布有贡献。
本发明的方法可以处理没有特定的辐射吸收的极薄膜。这具体与薄膜晶体管(TFT)的制造相关，因为它们的低成本和高性能，其被强烈期望。
现在参考图4，示出了通过上述脉冲辐射热处理技术制造的TFT40。如所示，薄介质层44放置于位于邻接极薄膜43的两个吸收痕41和42的顶上。导电痕45位于介质层44和吸收痕41和42的顶上。吸收痕41，42导电并且分别形成TFT的源极和漏极。导电痕45形成TFT的栅极。在被热处理的极薄膜43中位于吸收痕41和42之间的区域是形成TFT的有源沟道的半导体。如图4中所示，被固化的区域(阴影区域)包括栅极氧化物和栅极。然而，在固化极薄膜43之后，栅极氧化物和栅极两者被施加。
在吸收痕41和42之间，极薄膜43首先被固化，因此可以在很大的区域上构图(或印刷)源极和漏极，并且甚至在整个衬底46上覆盖极薄膜43。因为固化的半导体一般地具有比未固化时更高的导电性，所以事实上在TFT的沟道中的半导体首先被固化，半导体的寄生电容减少。对配准和临界尺寸装置的减小的需要意味着上述TFT可以被完全地群体(en mass)印刷。
如下描述用于制造如TFT 40的TFT的方法的实例。当制造TFT时，作为半导体，与非晶硅(a-Si)比较更期望微晶硅(μx-Si)，因为μx-Si具有更高的迁移率并且因此能够更快地切换TFT。通常，沉积a-Si接着热处理以将a-Si转化为μx-Si比直接沉积μx-Si更容易。例如，在500μm硅酸硼晶片上的200nm的a-Si膜可以通过使用来自PulseForge@3300系统(由NovaCentrix in Austin，Texas制造)的处于650V的阈值电压和100μs的脉冲长度的光脉冲转化为μx-Si(用N2净化(purge))。光脉冲具有约35kW/cm2的强度，其对应于约3.5J/cm2的辐射曝光。
现在参考图5，示出了在暴露到上述光脉冲之前和之后e-束溅射涂覆在硅酸硼玻璃上的200nm a-Si膜的拉曼谱。通过光脉冲退火a-Si膜并且转化为μx-Si。光脉冲需要克服200nm a-Si覆层仅吸收部分发射光的事实。
用金接触源极/漏极线构图一致硅酸硼晶片以形成各种宽度(5-50μm)和间隔(5-50μm)的产生的TFT。所有的痕是5mm长。金构图后，接着在硅酸硼晶片上一致散播(broadcast)电子束溅射沉积上述200nm的a-Si。然后通过上述PulseForge@3300系统在更低的电压下(即，550V下250μs)处理硅酸硼晶片。辐射功率为24kW/cm2，并且辐射曝光是5.9J/cm2。注意此水平的功率低于上述用于将a-Si转换到μx-Si的阈值强度。因为金更容易吸收光脉冲，所以更多能量在此位置被吸收。
现在参考图6，其示出了本发明的脉冲辐射热处理方法的选择性。该图示出了在具有两个不同金线对宽度(50μm和20μm)和相同间隔(50μm)的金痕之间的薄硅膜的拉曼谱。该图示出了在50μm痕之间的间隔被转化为μx-Si，然而在20μm宽痕之间的间隔没有转化。类似地，在晶片的剩余部分的硅膜没有转化。此技术仅将在构图的金痕之间的a-Si转化为μx-Si并且没有其他地方获得自动配准。
在获得在吸收痕之间的a-Si到μx-Si选择性转换之后，可以使用旋涂钛酸锶钡(BST)陶瓷作为介质层。此介质材料具有相对高的介电常数k(300)，其允许以低栅极电压向TFT的场效应沟道施加高电场。在BST栅极介质层上真空沉积银栅极金属以完成TFT。
可以在TFT上进行电测试以确定漏极电流是否可以通过施加正栅极电压增强。因为μx-Si是轻微的n型，正栅极电压应该增强沟道中的电子浓度并且导致增加的漏极电流(TFT)。
现在参考图7，其示出了表示来自图4的TFT40的漏极电流(Id)与漏极-源极电压(Vds)的图。注意，正栅极电压(Vds)、漏极电流(Id)被增强并且具有对于场效应TFT预期的饱和形状。当施加负栅极电压时，在负栅极电压处观察的线性I-V特性指示出TFT40呈现普通电阻器的特性。此时还了解此现象的原因，但可能是因为来自源极和漏极接触的空穴注入。如果出现，此效应一般通过适宜地掺杂接触区域以“阻止”空穴注入而减少/消除。
总之，使用具有横向位于金属源极-漏极接触之间的a-Si薄膜的脉冲光退火可以将源极-漏极接触之间区域“压阈值”退火到微晶状态。这对于微电子工业具有很大的益处，因为微(和纳)晶硅膜具有高载流子迁移率以及其它增强薄膜器件的性能的期望的特征。另外，因为可以仅转化在源极/漏极接触之间的区域中的a-Si，留下a-Si的周围区域保持在高电阻非晶状态，因而不要求构图或者隔离以限制如寄生电容的不利影响，该不利影响会限制器件的速度并且增加功率消耗。
如已经描述的，本发明提供了一种用于热处理在低温衬底上的薄膜的方法。本发明的方法还使得能够以顶栅极配置(即，在顶上的栅极)用最小配置来制造TFT。两个吸收痕形成TFT的源极和漏极。在施加栅极氧化物和栅极前，优先热处理在两个吸收痕之间的薄膜材料。本发明的方法具有选择性固化薄膜材料而不需要在TFT的沟道中精确沉积该材料的效果。
虽然参考具体的实施例示出并描述了本发明，本领域的技术人员应该明白，在不脱离本发明的精神和范围内可以进行形式和细节上的各种改变。

Claims (14)

1.一种用于热处理极薄膜的方法，所述方法包括：
邻近极薄膜构图两个吸收痕，其中所述两个吸收痕由金属构成，其中所述极薄膜位于衬底的顶上；
用至少一个电磁脉冲辐射所述两个吸收痕以加热所述两个吸收痕，其中所述至少一个电磁脉冲的脉冲长度比所述衬底的热平衡时间短；以及
允许来自所述两个吸收痕的热来热处理所述极薄膜。
2.根据权利要求1的方法，其中所述衬底具有小于450℃的最大加工温度。
3.根据权利要求1的方法，其中所述两个吸收痕由比所述极薄膜更多地吸收所述电磁脉冲的材料构成。
4.根据权利要求1的方法，其中所述方法还包括邻近所述极薄膜提供热传播层。
5.根据权利要求4的方法，其中所述方法还包括在所述热传播层和所述衬底之间提供高温、低热导率膜。
6.根据权利要求1的方法，其中从闪光灯提供所述电磁脉冲。
7.根据权利要求1的方法，其中从定向等离子体弧提供所述电磁脉冲。
8.一种用于制造薄膜晶体管的方法，所述方法包括：
邻近极薄膜构图两个吸收痕，其中所述两个吸收痕由金属构成，其中所述极薄膜位于衬底的顶上；
用至少一个电磁脉冲辐射所述两个吸收痕以加热所述两个吸收痕，其中所述至少一个电磁脉冲的脉冲长度比所述衬底的热平衡时间短，以及允许来自所述两个吸收痕的热来热处理所述极薄膜；
在所述两个吸收痕和所述极薄膜上沉积介质层；以及
通过在所述介质层的顶上沉积导电痕而形成栅极。
9.根据权利要求8的方法，其中所述衬底具有小于450℃的最大加工温度。
10.根据权利要求8的方法，其中所述两个吸收痕由比所述极薄膜更多地吸收所述电磁脉冲的材料构成。
11.根据权利要求8的方法，其中所述方法还包括邻近所述极薄膜提供热传播层。
12.根据权利要求11的方法，其中所述方法还包括在所述热传播层和所述衬底之间提供高温、低热导率膜。
13.根据权利要求8的方法，其中从闪光灯提供所述电磁脉冲。
14.根据权利要求8的方法，其中从定向等离子体弧提供所述电磁脉冲。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10000411B2 (en) 2010-01-16 2018-06-19 Cardinal Cg Company Insulating glass unit transparent conductivity and low emissivity coating technology
US9862640B2 (en) 2010-01-16 2018-01-09 Cardinal Cg Company Tin oxide overcoat indium tin oxide coatings, coated glazings, and production methods
US10000965B2 (en) 2010-01-16 2018-06-19 Cardinal Cg Company Insulating glass unit transparent conductive coating technology
US10060180B2 (en) 2010-01-16 2018-08-28 Cardinal Cg Company Flash-treated indium tin oxide coatings, production methods, and insulating glass unit transparent conductive coating technology
US11155493B2 (en) 2010-01-16 2021-10-26 Cardinal Cg Company Alloy oxide overcoat indium tin oxide coatings, coated glazings, and production methods
US9639001B2 (en) * 2014-02-04 2017-05-02 Raytheon Company Optically transitioned metal-insulator surface
US9728668B2 (en) 2014-02-04 2017-08-08 Raytheon Company Integrated photosensitive film and thin LED display
US10593821B2 (en) 2014-09-12 2020-03-17 Board Of Regents, The University Of Texas System Photonic curing of nanocrystal films for photovoltaics
JP7118463B2 (ja) * 2018-01-19 2022-08-16 エヌシーシー ナノ， エルエルシー 熱的に脆弱な基板上ではんだペーストを硬化させるための方法
US11028012B2 (en) 2018-10-31 2021-06-08 Cardinal Cg Company Low solar heat gain coatings, laminated glass assemblies, and methods of producing same
JP7203417B2 (ja) * 2019-01-31 2023-01-13 株式会社ブイ・テクノロジー レーザアニール方法、レーザアニール装置、およびｔｆｔ基板
EP3928966A1 (en) 2020-06-26 2021-12-29 Carl Zeiss Vision International GmbH Method for manufacturing a coated lens
TW202236550A (zh) * 2020-11-25 2022-09-16 美商應用材料股份有限公司 用於低溫處理的補充能量

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5302230A (en) * 1980-02-27 1994-04-12 Ricoh Company, Ltd. Heat treatment by light irradiation
EP0169485B1 (en) * 1984-07-17 1991-12-04 Nec Corporation Method and apparatus for inducing photochemical reaction
JPH0715881B2 (ja) * 1984-12-20 1995-02-22 ソニー株式会社 半導体薄膜の熱処理方法
JPH0727198B2 (ja) * 1987-02-18 1995-03-29 キヤノン株式会社 多層膜反射型マスク
JPH02275641A (ja) * 1989-04-17 1990-11-09 Seiko Epson Corp 半導体装置の製造方法
US5180226A (en) * 1991-10-30 1993-01-19 Texas Instruments Incorporated Method and apparatus for precise temperature measurement
CA2137632A1 (en) * 1993-12-17 1995-06-18 Douglas S. Dunn Ablative flashlamp imaging
JPH09116158A (ja) * 1995-10-17 1997-05-02 Hitachi Ltd 軽量基板薄膜半導体装置および液晶表示装置
US5950078A (en) * 1997-09-19 1999-09-07 Sharp Laboratories Of America, Inc. Rapid thermal annealing with absorptive layers for thin film transistors on transparent substrates
US6159832A (en) * 1998-03-18 2000-12-12 Mayer; Frederick J. Precision laser metallization
JP3586558B2 (ja) * 1998-04-17 2004-11-10 日本電気株式会社 薄膜の改質方法及びその実施に使用する装置
TW457553B (en) * 1999-01-08 2001-10-01 Sony Corp Process for producing thin film semiconductor device and laser irradiation apparatus
JP3980466B2 (ja) * 2001-11-09 2007-09-26 株式会社半導体エネルギー研究所 レーザー装置及びレーザー照射方法
US7364952B2 (en) * 2003-09-16 2008-04-29 The Trustees Of Columbia University In The City Of New York Systems and methods for processing thin films
JP2005150608A (ja) * 2003-11-19 2005-06-09 Seiko Epson Corp ガラス基板の光処理方法およびデバイス
TW200541079A (en) * 2004-06-04 2005-12-16 Adv Lcd Tech Dev Ct Co Ltd Crystallizing method, thin-film transistor manufacturing method, thin-film transistor, and display device
JP2006066902A (ja) * 2004-07-28 2006-03-09 Advanced Lcd Technologies Development Center Co Ltd 半導体装置の製造方法
US20070037346A1 (en) * 2005-02-22 2007-02-15 Grant Robert W Rapid thermal annealing of targeted thin film layers
US7943447B2 (en) * 2007-08-08 2011-05-17 Ramesh Kakkad Methods of fabricating crystalline silicon, thin film transistors, and solar cells
JP5447909B2 (ja) * 2008-04-25 2014-03-19 株式会社日本製鋼所 薄膜材料の結晶化方法及びその装置
US8410712B2 (en) * 2008-07-09 2013-04-02 Ncc Nano, Llc Method and apparatus for curing thin films on low-temperature substrates at high speeds
JP5167050B2 (ja) * 2008-09-30 2013-03-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法およびマスクの製造方法
US20100170566A1 (en) * 2009-01-06 2010-07-08 Arthur Don Harmala Apparatus and method for manufacturing polymer solar cells
JP2010219207A (ja) * 2009-03-16 2010-09-30 Sony Corp 金属−絶縁体相転移材料を用いた機能要素の形成方法及びこれによって形成された機能要素、並びに機能デバイスの製造方法及びこれによって製造された機能デバイス
JP7027198B2 (ja) 2018-03-06 2022-03-01 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置

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